Speed, power and reliability of analogue integrated circuits (IC) exhibit temperature dependency through the modulation of one or several of the following variables: band gap energy of the semiconductor, mobility, carrier diffusion, current density, threshold voltage, interconnect resistance, and variability in passive components. Some of the adverse effects of temperature variations are observed in current and voltage reference circuits, and frequency drift in oscillators. Thermal instability of a voltage-controlled oscillator (VCO) is a critical design factor for radio frequency ICs, such as transceiver circuits in communication networks, data link protocols, medical wireless sensor networks and microelectromechanical resonators. For example, frequency drift in a transceiver system results in severe inter-symbol interference in a digital communications system. Minimum transconductance required to sustain oscillation is specified by Barkhausen’s stability criterion. However it is common practice to design oscillators with much more transconductance enabling self-startup. As temperature is increased, several of the variables mentioned induce additional transconductance to the oscillator. This in turn translates to a negative frequency drift. Conventional approaches in temperature compensation involve temperature-insensitive biasing proportional-to-absolute temperature, modifying the control voltage terminal of the VCO using an appropriately generated voltage. Improved frequency stability is reported when compensation voltage closely follows the frequency drift profile of the VCO. However, several published articles link the close association between oscillation amplitude and oscillation frequency. To the knowledge of this author, few published journal articles have focused on amplitude control techniques to reduce frequency drift. This dissertation focuses on reducing the frequency drift resulting from temperature variations based on amplitude control. A corresponding hypothesis is formulated, where the research outcome proposes improved frequency stability in response to temperature variations. In order to validate this principle, a temperature compensated VCO is designed in schematic and in layout, verified using a simulation program with integrated circuit emphasis tool using the corresponding process design kit provided by the foundry, and prototyped using standard complementary metal oxide semiconductor technology. Periodic steady state (PSS) analysis is performed using the open loop VCO with temperature as the parametric variable in five equal intervals from 0 – 125 °C. A consistent negative frequency shift is observed in every temperature interval (≈ 11 MHz), with an overall frequency drift of 57 MHz. However similar PSS analysis performed using a VCO in the temperature stabilised loop demonstrates a reduced negative frequency drift of 3.8 MHz in the first temperature interval. During the remaining temperature intervals the closed loop action of the amplitude control loop overcompensates for the negative frequency drift, resulting in an overall frequency spread of 4.8 MHz. The negative frequency drift in the first temperature interval of 0 to 25 °C is due to the fact that amplitude control is not fully effective, as the oscillation amplitude is still building up. Using the temperature stabilised loop, the overall frequency stability has improved to 16 parts per million (ppm)/°C from an uncompensated value of 189 ppm/°C. The results obtained are critically evaluated and conclusions are drawn. Temperature stabilised VCOs are applicable in applications or technologies such as high speed-universal serial bus, serial advanced technology attachment where frequency stability requirements are less stringent. The implications of this study for the existing body of knowledge are that better temperature compensation can be obtained if any of the conventional compensation schemes is preceded by amplitude control. / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted

Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon. Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics. The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm. In summary, the dissertation is to expected to aid the state of the art in following ways: 1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with. 2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization. 3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well.

Radio Frequency (RF) and Microwave devices are typically implemented in Integrated Circuit (IC) form to minimize parasitics, increase precision and tolerances, and minimize size. Although IC fabrication for students and independent engineers is cost-prohibitive, an abundance of low-cost, easily accessible printed circuit board (PCB) and electronic component manufacturers allows affordable PCB fabrication. While nearly all microwave voltage-controlled oscillator (VCO) designs are IC-based, this study presents a discrete PCB-level cross-coupled, differential LC VCO to demonstrate this more affordable and accessible approach. This thesis presents a 65 mW, discrete component VCO PCB with industry-comparable RF performance. A phase noise of -103.7 dBc/Hz is simulated at a 100 kHz offset from a 4.05 GHz carrier. This VCO achieves a 532 MHz (13.25%) tuning bandwidth. A figure of merit, FOMP, [1] value of -177.7 dB (includes phase noise and power consumption) is calculated at 4.05 GHz. This surpasses the performance of an industry standard VCO (HMC430LPx, Analog Devices), -176.5 dB, and four other commercially available VCOs. Furthermore, this study presents novel discrete design implementations to minimize both power consumption and capacitive loading effects, while optimizing phase noise. Finally, this project serves as a reference for analyzing and implementing low-level, complex RF and Microwave circuits on a PCB accessible to all students and independent engineers.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

"2009" / Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010. / Bibliography: p. 163-166. / Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion. / Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices. / Mode of access: World Wide Web. / xxii, 166 p. : ill (some col.)

This research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted

The research conducted for this thesis seeks to understand issues associated with integrating a direct spread spectrum system (DSSS) transceiver on to a single chip. Various types of sequences, such as Kasami sequences and Gold sequences, are available for use in typical spread spectrum systems. For this thesis, complex spreading sequences (CSS) are used for improved cross-correlation and autocorrelation properties that can be achieved by using such a sequence. While CSS and DSSS are well represented in the existing body of knowledge, and discrete bulky hardware solutions exist – an effort to jointly integrate CSS and DSSS on-chip was identified to be lacking. For this thesis, spread spectrum architecture was implemented focussing on sub-systems that are specific to CSS. This will be the main contribution for this thesis, but the contribution is further appended by various RF design challenges: highspeed requirements make RF circuits sensitive to the effects of parasitics, including parasitic inductance, passive component modelling, as well as signal integrity issues. The integration is first considered more ideally, using mathematical sub-systems, and then later implemented practically using complementary metal-oxide semiconductor (CMOS) technology. The integration involves mixed-signal and radio frequency (RF) design techniques – and final integration involves several specialized analogue sub-systems, such as a class F power amplifier (PA), a low-noise amplifier (LNA), and LC voltage-controlled oscillators (VCOs). The research also considers various issues related to on-chip inductors, and also considers an active inductor implementation as an option for the VCO. With such an inductor a better quality factor is achievable. While some conventional sub-system design techniques are deployed, several modifications are made to adapt a given sub-system to the design requirements for this thesis. The contribution of the research lies in the circuit level modifications done at sub-system level aimed towards eventual integration. For multiple-access communication systems, where a number of independent users are required to share a common channel, the transceiver proposed in this thesis, can contribute towards improved data rate or bit error rate. The design is completed for fabrication in a standard 0.35-μm CMOS process with minimal external components. With an active chip area of about 5 mm2, the simulated transmitter consumes about 250 mW&the receiver consumes about 200 mW. AFRIKAANS : Die navorsing wat vir hierdie tesis onderneem is, beoog om kundigheid op te bou aangaande die kwessies wat met die integrasie van ‘n direkte spreispektrumstelsel (DSSS) sender-ontvanger op ‘n enkele skyfie verband hou. Verskeie tipes sekwensies, soos byvoorbeeld Kasami- en Gold-sekwensies, is vir gebruik in tipiese spreispektrumstelsels beskikbaar. Vir hierdie tesis is komplekse spreisekwensies (KSS) gebruik vir verbeterde kruis- en outokorrelasie-eienskappe wat bereik kan word deur so ‘n sekwensie te gebruik. Alhoewel DSSS en KSS reeds welbekend is, en diskrete hardeware oplossings reeds bestaan, is die vraag na gesamentlike geïntegreerde DSSS en KSS op een vlokkie geïdentifiseer. Vir hierdie tesis is spreispektrumargitektuur aangewend met die klem op KSS substelsels. Dit is dan ook die belangrikste bydrae van hierdie tesis, maar die bydrae gaan verder gepaard met verskeie RF-ontwerpuitdagings: hoëspoed-vereistes maak RF-stroombane sensitief vir die uitwerking van parasitiese komponente, met inbegrip van parasitiese induktansie, passiewe komponentmodellering en ook seinintegriteitskwessies. Die integrasie word eerstens meer idealisties oorweeg deur wiskundige substelsels te gebruik en dan later prakties te implementeer deur komplementêre metaaloksied-halfgeleiertegnologie (CMOS) te gebruik. Die integrasie behels gemengdesein- en radiofrekwensie(RF)-ontwerptegnieke – en finale integrasie behels verskeie gespesialiseerde analoë substelsels soos ‘n klas F-kragversterker (KV), ‘n laeruis-versterker (LRV), en LC-spanningbeheerde ossileerders (SBO’s). Die navorsing oorweeg ook verskeie kwessies in verband met op-skyfie induktors en oorweeg ook ‘n aktiewe induktorimplementering as ‘n opsie vir die SBO. Met sodanige induktor is ‘n beter kwaliteitsfaktor haalbaar. Hoewel enkele konvensionele substelsel-ontwerptegnieke aangewend word, word daar verskeie wysigings aangebring om ‘n gegewe substelsel by die ontwerpvereistes vir hierdie tesis aan te pas. Die bydrae van die navorsing is hoofsaaklik die stroombaanmodifikasies wat gedoen is op substelselvlak om integrasie te vergemaklik. Vir veelvoudige-toegang kommunikasiestelsels waar ‘n aantal onafhanklike gebruikers dieselfde seinkanaal moet deel, kan die sender-ontvanger voorgestel in hierdie tesis meewerk om die datatempo en fouttempo te verbeter. Die ontwerp is voltooi vir vervaardiging in ‘n standaard 0.35-μm CMOS-proses met minimale eksterne komponente. Met ‘n aktiewe skyfie-oppervlakte van ongeveer 5 mm2, verbruik die gesimuleerde sender ongeveer 250 mW en die ontvanger verbruik ongeveer 200 mW. / Thesis (PHD)--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

This thesis discusses about using the worldwide satellite system GPS for time and frequency synchronization. This thesis presents study about basic principles of the GPS system, its segments and ways of using this system. Some GPS receivers suitable for receiving the time marks (pulses) used for time synchronization are described. Thesis contents designing of the circuit that will receive time marks and it will digitalize and record external signal and send it with precision time information to PC for displaying and post processing. Thesis also discusses about both hardware and software development of the synchronization module and software used in PC.