Les micro-dispositifs comportant des structures libérées et mobiles sont d’une part très sensibles aux variations de leur environnement de travail, et d’autre part très fragiles mécaniquement. L’étape de découpe du substrat en plusieurs puces est extrêmement agressive et peut entrainer la destruction totale des micro-dispositifs. L’encapsulation avant la découpe va alors prémunir les micro-composants lors de cette étape critique et continuer à garantir leur bon fonctionnement tout au long de leur utilisation en conservant la stabilité et la fiabilité de leur performance. Le conditionnement doit en outre interfacer les micro-dispositifs encapsulés avec le monde macroscopique en vue de leur utilisation. De nombreux procédés de fabrication ont déjà été développés pour l’élaboration d’un conditionnement. C’est le cas de l’encapsulation puce par puce, substrat - substrat, par couche sacrificielle par exemple. Ils sont toutefois très contraignants (encombrement, compatibilité, coût, …). Nous avons étudié, au cours de cette thèse, un procédé innovant de conditionnement hermétique par transfert de film utilisant une couche à adhésion contrôlée. Cette technologie consiste à élaborer des capots protecteurs sur le substrat moule puis à les reporter collectivement pour encapsuler les micro-dispositifs. Ce procédé est totalement compatible avec un interfaçage électrique de composant qui traverse les cordons de scellement ou le capot. Ce procédé nécessite la maîtrise de la croissance de divers films (C, CxFy, Ni, AlN, parylène, BCB, Au-In) et permet d’obtenir des boitiers étanches, hermétiques et robustes qui devraient très rapidement pouvoir être utilisés pour le conditionnement de MEMS. / Micro-devices which are composed of free standing or mobile structures are very sensitive to the working condition and mechanically very fragile. The saw dicing steps is very aggressive and it can destroy the micro-devices. Packaging will prevent the micro devices from any damage during this critical step and also take care of it all along its life by controlling its performance stability and reliability. Moreover, the suited devices use needs a connection to the macroscopic word through the packaging. Many packaging process flow has already developed such as pick and place, wafer to wafer, thin film packaging with a sacrificial layer. Nevertheless, they have got many drawbacks (footprint, process compatibility, cost …). We have developed an attractive wafer level hermetic packaging process by film transfer technology during this these. It relies on a transferred molded film cap from a carrier wafer to the donor wafer. Electrical path can be done through the cap or the bonding ring. Cap manufacturing need a high layer growth skill for example in C, CxFy, Ni, AlN, parylène, BCB, Au-In films to make robust, hermetic encapsulation which should be soon used for MEMS packaging.

L'objectif de ce travail de thèse a été d'évaluer, à partir d'outils de caractérisation électrique (spectroscopie d'impédance basse fréquence et courants thermo-stimulés), l'impact des étapes de polissage mécanochimique (CMP) et de recuits thermiques sur les propriétés diélectriques de matériaux utilisés pour les dernières générations de circuits intégrés. Une première partie est focalisée sur le matériau SiOCH poreux déposé par voie chimique " en phase vapeur " assisté par plasma (PECVD) suivant une approche porogène (p=26%, d=2nm et er=2,5). Son intégration dans les technologies 45nm nécessite l'utilisation d'un procédé de 'CMP directe' qui induit une dégradation des propriétés isolantes attribuée à l'adsorption de surfactants et de molécules d'eau. L'analyse diélectrique sur une large gamme de fréquence (10-1Hz- 105Hz) et de température (-120°C -200°C) a mis en évidence plusieurs mécanismes de relaxation diélectrique et de conduction liés à la présence de molécules nanoconfinées (eau et porogène) dans les pores du matériau. L'étude de ces mécanismes a permis d'illustrer le phénomène de reprise en eau du SiOCH poreux ainsi que d'évaluer la capacité de traitements thermiques à en restaurer les performances. Une seconde partie concerne l'étude d'une résine époxy chargée avec des nanoparticules de silice, utilisée en tant que 'wafer level underfill' dans les technologies d'intégration 3D. Les analyses en spectroscopie d'impédance ont montré que l'ajout de nanoparticules de silice s'accompagne d'une élévation de la température de transition vitreuse et de la permittivité diélectrique, ainsi que d'une diminution de la conductivité basse fréquence. L'autre contribution majeure des mesures diélectriques a été de montrer qu'un refroidissement trop rapide de la résine à l'issue de la réticulation était responsable d'une contrainte interne qui pourra occasionner des problèmes de fiabilité pour l'application.

This thesis devotes to develop a wafer-level packaging technique of the planar AgCl-based micro reference electrode and to investigate its various electrochemical characteristics (including the potential stability and offset voltage, AC impedance, cyclic-voltammetry analysis, electrochemical noise and reproducibility). The miniaturized all-solid-state reference electrode can integrated with many biomedical or biochemical sensors for substantially reduce the dimension of the whole sensing system and improve the commercial capability of portable detecting products. This study reports firstly a smallest module of the micro reference electrode with dimension only about 9 mm (L) ¡Ñ 6 mm (W) ¡Ñ 1 mm (H) in the worldwide using the silicon bulk-micromachining technology, thin film deposition and chloridation techniques. The packaged reference electrode module is constructed by two bonded wafers with different functions. One wafer of this module is defined as ¡§electrode chip¡¨ and it has a Ti/Pd/Ag/AgCl planar quasi-reference electrode deposited on its surface. Another wafer is called as ¡§packaging chip¡¨ and it has two bulk-micromachined silicon cavities for the filling/sealing of 1.33 ~ 6.40 £gL KCl-gel (as the salt-bridge of electrode) and electrical connection. Many electrochemical characteristics of the encapsulated solid-state micro reference electrode are tested and improved for the commercial applications. Including a very stable cell potential (<4 mV in 30000 sec.), an approximately zero offset-voltage, a low AC impedance (1~20 K£[), and high reproducibility (drift less than 3~8 mV in 30000 sec. and the range of offset voltage is -6 ~ 3 mV) of the packaged micro reference electrode are demonstrated. Furthermore, stable CV curve of the packaged Ti/Pd/Ag/AgCl/KCl-gel reference electrode were proved by cyclic-voltammetry analysis and its low electrochemical noise spectrum was investigated and discussed in this work. Compared with the commercial reference electrode, the planar miniaturized AgCl reference electrode module developed in this thesis has displayed its many excellent characteristics and with a dimension only 250 times smaller than the conventional reference electrode.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales soudées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la fiabilité du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée.

We have pioneered a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films [1,2]. The achievement of transfer-free bilayer graphene directly on silicon wafers, with high adhesion, at temperatures compatible with conventional semiconductor processing, and showing record- low sheet resistances, makes this approach an ideal route for metal replacement method for nanodevices with ultimate scalability fabricated at the wafer –level.

For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters. / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.

For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters.:Bibliographische Beschreibung 3 Vorwort 13 List of symbols and abbreviations 15 1 Introduction 23 2 Fundamentals on MEMS and TSV based 3D integration 25 2.1 Micro Electro-Mechanical systems 25 2.1.1 Basic Definition 25 2.1.2 Silicon technologies for MEMS 26 2.1.3 MEMS packaging 29 2.2 3D integration based on TSVs 33 2.2.1 Overview 33 2.2.2 Basic processes for TSVs 34 2.2.3 Stacking and Bonding 47 2.2.4 Wafer thinning 48 2.3 TSV based MEMS packaging 50 2.3.1 MEMS-TSVs 50 2.3.2 3D-WLP for MEMS 52 3 Technology development for a 3D-WLP based MEMS 57 3.1 Target integration approach for 3D-WLP based MEMS 57 3.1.1 MEMS modules using 3D-WLP based MEMS 57 3.1.2 Integration concepts 58 3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60 3.2.1 Boundary conditions 60 3.2.2 Technology concepts 63 3.3 Selected approaches for TSV implementation in MEMS 64 3.3.1 Via Last Technology 64 3.3.2 Via Middle technology 69 4 Development of process modules 75 4.1 Characterisation 75 4.2 TSV related etch processes 77 4.2.1 Equipment 77 4.2.2 Deep silicon etching 78 4.2.3 Etching of the buried dielectric layer 84 4.2.4 Patterning of TSV isolation liner – spacer etching 90 4.2.5 Summary 92 4.3 TSV isolation 93 4.3.1 Principle considerations 93 4.3.2 Experiment 95 4.3.3 Results 97 4.3.4 Summary 102 4.4 Metallisation of TSV and RDL 103 4.4.1 Plating base and experimental setup 103 4.4.2 Investigations related to the ECD process 106 4.4.3 Pattern plating 117 4.4.4 Summary 123 4.5 Wafer Level Bonding 124 4.5.1 Silicon direct bonding 124 4.5.2 Thermo-compression bonding by using ECD copper 128 4.5.3 Summary 134 4.6 Wafer thinning and TSV back side reveal 134 4.6.1 Thinning processes 134 4.6.2 TSV reveal processes 136 4.6.3 Summary 145 4.7 Under bump metallisation and solder bumps 146 5 Demonstrator design, fabrication and characterisation 149 5.1 Single wafer demonstrator for electrical test 149 5.1.1 Demonstrator design and test structure layout 149 5.1.2 Demonstrator fabrication 150 5.1.3 Electrical measurement 151 5.1.4 Summary 153 5.2 Via Last based TSV fabrication in the MEMS device wafer 153 5.2.1 Layout of the MEMS device with TSVs 153 5.2.2 Fabrication of TSVs and wafer thinning 154 5.2.3 Characterisation of the fabricated device 155 5.2.4 Summary 156 5.3 Via Last based cap-TSV for very thin MEMS devices 157 5.3.1 Design 157 5.3.2 Fabrication 158 5.3.3 Characterisation 161 5.3.4 Summary 162 5.4 Via Middle approach based on thinning after bonding 163 5.4.1 Design 163 5.4.2 Results and characterisation 164 5.4.3 Summary 166 6 Conclusion and outlook 167 Appendix A: Typical requirements on a MEMS package and its functions 171 Appendix B: Classification of packaging and system integration techniques 173 B.1 Packaging of electronic devices in general 173 B.2 Single Chip Packages 174 B.3 System integration 175 B.4 3D integration based on TSVs 180 Bibliography 183 List of figures 193 List of tables 199 Versicherung 201 Theses 203 Curriculum vitae 205 Own publications 207 / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.:Bibliographische Beschreibung 3 Vorwort 13 List of symbols and abbreviations 15 1 Introduction 23 2 Fundamentals on MEMS and TSV based 3D integration 25 2.1 Micro Electro-Mechanical systems 25 2.1.1 Basic Definition 25 2.1.2 Silicon technologies for MEMS 26 2.1.3 MEMS packaging 29 2.2 3D integration based on TSVs 33 2.2.1 Overview 33 2.2.2 Basic processes for TSVs 34 2.2.3 Stacking and Bonding 47 2.2.4 Wafer thinning 48 2.3 TSV based MEMS packaging 50 2.3.1 MEMS-TSVs 50 2.3.2 3D-WLP for MEMS 52 3 Technology development for a 3D-WLP based MEMS 57 3.1 Target integration approach for 3D-WLP based MEMS 57 3.1.1 MEMS modules using 3D-WLP based MEMS 57 3.1.2 Integration concepts 58 3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60 3.2.1 Boundary conditions 60 3.2.2 Technology concepts 63 3.3 Selected approaches for TSV implementation in MEMS 64 3.3.1 Via Last Technology 64 3.3.2 Via Middle technology 69 4 Development of process modules 75 4.1 Characterisation 75 4.2 TSV related etch processes 77 4.2.1 Equipment 77 4.2.2 Deep silicon etching 78 4.2.3 Etching of the buried dielectric layer 84 4.2.4 Patterning of TSV isolation liner – spacer etching 90 4.2.5 Summary 92 4.3 TSV isolation 93 4.3.1 Principle considerations 93 4.3.2 Experiment 95 4.3.3 Results 97 4.3.4 Summary 102 4.4 Metallisation of TSV and RDL 103 4.4.1 Plating base and experimental setup 103 4.4.2 Investigations related to the ECD process 106 4.4.3 Pattern plating 117 4.4.4 Summary 123 4.5 Wafer Level Bonding 124 4.5.1 Silicon direct bonding 124 4.5.2 Thermo-compression bonding by using ECD copper 128 4.5.3 Summary 134 4.6 Wafer thinning and TSV back side reveal 134 4.6.1 Thinning processes 134 4.6.2 TSV reveal processes 136 4.6.3 Summary 145 4.7 Under bump metallisation and solder bumps 146 5 Demonstrator design, fabrication and characterisation 149 5.1 Single wafer demonstrator for electrical test 149 5.1.1 Demonstrator design and test structure layout 149 5.1.2 Demonstrator fabrication 150 5.1.3 Electrical measurement 151 5.1.4 Summary 153 5.2 Via Last based TSV fabrication in the MEMS device wafer 153 5.2.1 Layout of the MEMS device with TSVs 153 5.2.2 Fabrication of TSVs and wafer thinning 154 5.2.3 Characterisation of the fabricated device 155 5.2.4 Summary 156 5.3 Via Last based cap-TSV for very thin MEMS devices 157 5.3.1 Design 157 5.3.2 Fabrication 158 5.3.3 Characterisation 161 5.3.4 Summary 162 5.4 Via Middle approach based on thinning after bonding 163 5.4.1 Design 163 5.4.2 Results and characterisation 164 5.4.3 Summary 166 6 Conclusion and outlook 167 Appendix A: Typical requirements on a MEMS package and its functions 171 Appendix B: Classification of packaging and system integration techniques 173 B.1 Packaging of electronic devices in general 173 B.2 Single Chip Packages 174 B.3 System integration 175 B.4 3D integration based on TSVs 180 Bibliography 183 List of figures 193 List of tables 199 Versicherung 201 Theses 203 Curriculum vitae 205 Own publications 207

This thesis treats the development of packaging and integration methods for the cost-efficient encapsulation and packaging of microelectromechanical (MEMS) devices. The packaging of MEMS devices is often more costly than the device itself, partly because the packaging can be crucial for the performance of the device. For devices which contain liquids or needs to be enclosed in a vacuum, the packaging can account for up to 80% of the total cost of the device. The first part of this thesis presents the integration scheme for an optical dye thin film NO2-gas sensor, designed using cost-efficient implementations of wafer-scale methods. This work includes design and fabrication of photonic subcomponents in addition to the main effort of integration and packaging of the dye-film. A specific proof of concept target was for NO2 monitoring in a car tunnel. The second part of this thesis deals with the wafer-scale packaging methods developed for the sensing device. The developed packaging method, based on low-temperature plastic deformation of gold sealing structures, is further demonstrated as a generic method for other hermetic liquid and vacuum packaging applications. In the developed packaging methods, the mechanically squeezed gold sealing material is both electroplated microstruc- tures and wire bonded stud bumps. The electroplated rings act like a more hermetic version of rubber sealing rings while compressed in conjunction with a cavity forming wafer bonding process. The stud bump sealing processes is on the other hand applied on completed cavities with narrow access ports, to seal either a vacuum or liquid inside the cavities at room temperature. Additionally, the resulting hermeticity of primarily the vacuum sealing methods is thoroughly investigated. Two of the sealing methods presented require permanent mechanical fixation in order to complete the packaging process. Two solutions to this problem are presented in this thesis. First, a more traditional wafer bonding method using tin-soldering is demonstrated. Second, a novel full-wafer epoxy underfill-process using a microfluidic distribution network is demonstrated using a room temperature process. / <p>QC 20130325</p>

This thesis presents the development of wafer level vacuum packaging processes using Au-Si eutectic and glass frit bonding contributing to the improvement of packaging concepts for a variety of MEMS devices. In the first phase of this research, micromachined resonators and pirani vacuum gauges are designed for the evaluation of the vacuum package performance. These designs are verified using MATLAB and Coventorware finite element modeling tool. Designed resonators and pirani vacuum gauges and previously developed gyroscopes with lateral feedthroughs are fabricated with a newly developed Silicon-On-Glass (SOG) process. In addition to these, a process for the fabrication of similar devices with vertical feedthroughs is initiated for achieving simplified packaging process and lower parasitic capacitances. Cap wafers for both types of devices with lateral and vertical feedthroughs are designed and fabricated. The optimization of Au-Si eutectic bonding is carried out on both planar and non-planar surfaces. The bonding quality is evaluated using the deflection test, which is based on the deflection of a thinned diaphragm due to the pressure difference between inside and outside the package. A 100% yield bonding on planar surfaces is achieved at 390&ordm / C with a v holding time and bond force of 60 min and 1500 N, respectively. On the other hand, bonding on surfaces where 0.15&mu / m feedthrough lines exist can be done at 420&ordm / C with a 100% yield using same holding time and bond force. Furthermore, glass frit bonding on glass wafers with lateral feedthroughs is performed at temperatures between 435-450&ordm / C using different holding periods and bond forces. The yield is varied from %33 to %99.4 depending on the process parameters. The fabricated devices are wafer level vacuum packaged using the optimized glass frit and Au-Si eutectic bonding recipes. The performances of wafer level packages are evaluated using the integrated gyroscopes, resonators, and pirani vacuum gauges. Pressures ranging from 10 mTorr to 60 mTorr and 0.1 Torr to 0.7 Torr are observed in the glass frit packages, satisfying the requirements of various MEMS devices in the literature. It is also optically verified that Au-Si eutectic packages result in vacuum cavities, and further study is needed to quantify the vacuum level with vacuum sensors based on the resonating structures and pirani vacuum gauges.

<p>Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer bonding techniqueshave been reported in literature. In adhesive wafer bondingorganic and inorganic adhesives are used as intermediatebonding material. The main advantages of adhesive wafer bondingare the relatively low bonding temperatures, the lack of needfor an electric voltage or current, the compatibility withstandard CMOS wafers and the ability to join practically anykind of wafer materials. Adhesive wafer bonding requires nospecial wafer surface treatmentssuch as planarisation.Structures and particles at the wafer surfaces can be toleratedand compensated for some extent by the adhesive material.Adhesive wafer bonding is a comparably simple, robust andlowcost bonding process. In this thesis, adhesive wafer bondingtechniques with different polymer adhesives have beendeveloped. The relevant bonding parameters needed to achievehigh quality and high yield wafer bonds have been investigated.A selective adhesive wafer bonding process has also beendeveloped that allows localised bonding on lithographicallydefined wafer areas.</p><p>Adhesive wafer bonding has been utilised in variousapplication areas. A novel CMOS compatible film, device andmembrane transfer bonding technique has been developed. Thistechnique allows the integration of standard CMOS circuits withthin film transducers that can consist of practically any typeof crystalline or noncrystalline high performance material(e.g. monocrystalline silicon, gallium arsenide,indium-phosphide, etc.). The transferred transducers or filmscan be thinner than 0.3 µm. The feature sizes of thetransferred transducers can be below 1.5 µm and theelectrical via contacts between the transducers and the newsubstrate wafer can be as small as 3x3 µm2. Teststructures for temperature coefficient of resistancemeasurements of semiconductor materials have been fabricatedusing device transfer bonding. Arrays of polycrystallinesilicon bolometers for use in uncooled infrared focal planearrays have been fabricated using membrane transfer bonding.The bolometers consist of free-hanging membrane structures thatare thermally isolated from the substrate wafer. Thepolycrystalline silicon bolometers are fabricated on asacrificial substrate wafer. Subsequently, they are transferredand integrated on a new substrate wafer using membrane transferbonding. With the same membrane transfer bonding technique,arrays of torsional monocrystalline silicon micromirrors havebeen fabricated. The mirrors have a size of 16x16 µm2 anda thickness of 0.34 µm. The advantages of micromirrorsmade of monocrystalline silicon are their flatness, uniformityand mechanical stability. Selective adhesive wafer bonding hasbeen used to fabricate very shallow cavities that can beutilised in packaging and component protection applications. Anew concept is proposed that allows hermetic sealing ofcavities fabricated using adhesive wafer bonding. Furthermore,microfluidic devices, channels and passive valves for use inmicro total analysis systems are presented.</p><p>Adhesive wafer bonding is a generic CMOS compatible bondingtechnique that can be used for fabrication and integration ofvarious microsystems such as infrared focal plane arrays,spatial light modulators, microoptical systems, laser systems,MEMS, RF-MEMS and stacking of active electronic films forthree-dimensional high-density integration of electroniccircuits. Adhesive wafer bonding can also be used forfabrication of microcavities in packaging applications, forwafer-level stacking of integrated circuit chips (e.g. memorychips) and for fabrication of microfluidic systems.</p>