Global ETD Search

11	Waveguide Finite Elements Applied on a Car Tyre Nilsson, Carl-Magnus January 2004 (has links) <p>Structures acting as waveguides are quite common withexamples being, construction beams, fluid filled pipes, railsand extruded aluminium profiles. Curved structures like cartyres and pipe-bends may also be considered as waveguides. Wavesolutions in such structures may be found by a method calledthe Waveguide Finite Element Method or WFEM. This method uses afinite element approach on the cross-section of a waveguide tomodel the vibro-acoustic response as a set of linear, coupled,one dimensional, wave-equations.</p><p>In this thesis six novel waveguide finite elements arederived and validated. These elements are, straight and curvedpre-stressed, orthotropic or anisotropic shell elements,straight and curved fluid elements, and straight and curvedfluid-shell coupling elements.</p><p>Forced response and input power calculations for infiniteand periodic waveguides are presented. The assembled waveguidemodels can also serve as input for the Super Spectral FiniteElement Method, which enables forced response calculations formore complex boundaries. Furthermore, several properties ofdamped and undamped wave solutions are investigated.</p><p>Finally, a car tyre model, encompassing for the highlyanisotropic material and the air cavity inside the tyre is setforth. A number of forced response calculations for this modelare presented and compared with measurements with goodagreement.</p><p><b>Keywords:</b>wave equation, wave solution, waveguide,finite element, spectral finite element, tyre noise, tyrevibration, input power, shells, pre-stress, fluid-shellcoupling axi-symmetric, two-and-half-dimensional</p> wave equation wave solution waveguide finite element spectral finite element tyre noise tyre vibration input power shells pre stress fluid shell coupling axi--symmetric
12	DATA TRANSFER PERFORMANCE ANALYSIS FROM PROGRAMMABLE LOGIC TO PROCESSING SYSTEM OF ZYNQ 7000 Tilottoma Barua (9188531) 30 July 2020 (has links) <div>Field Programmable Gate Arrays(FPGAs) were invented in the 1980s. Since then the use of FPGAs in many fields has been growing rapidly. Due to the inherent reconfiguration and relatively low development cost FPGA technology has become one of the important components in data processing and communication system.</div><div>The recent development of computing technology affects not only the software but also requires integrating and utilizing a custom logic design on a dedicated hardware platform.</div><div>In this context,this research work analyzes and compares on-chip interfaces of HW/SW communication in the Zynq-7000 all programmable SoC based platform. Several experiments were carried out to evaluate the performance of data communication between the processing system and programmable logic through general purpose(GP), high performance ports (HP) and accelerator coherency port (ACP). The results identified the most effective interfaces for transferring data from the PL to PS and store the data to DRAM memory.</div><div>One conclusion of this work is that, the selection of suitable ports depends on application requirements. For low-bandwidth application GP port is appropriate. For high-speed applications, the high performance port(HP) and Accelerator Coherency Port (ACP) are suitable and works better.The results of this thesis are useful in high performance embedded system design.<br></div><div><br></div><div><br></div> Zynq SoC technology Data transfer performance Programmable Logic(PL) Processing System(PS) AXI Interface FPGA
13	Etude expérimentale de la propagation de flammes dans un mélange stratifié / Experimental investigation of flame propagation through stratified mixture field Balusamy, Saravanan 22 October 2010 (has links) Pour mieux comprendre la combustion en mode stratifié, la propagation de flammes au sein de stratifications de richesse laminaire ou turbulente a été étudiée par des mesures simultanées de richesse et de vitesse effectuées par couplage de la PIV et de la PLIF. L’accent a été mis sur le développement de méthodes permettant d’améliorer la qualité des mesures locales. En particulier, un nouvel algorithme de PIV permettant la mesure locale de la vitesse des gaz frais véritablement à l’entrée de la zone de préchauffage a été développé. Pour améliorer la résolution,les mailles de calcul s’adaptent localement à la topologie de la flamme, pour tenir compte de la forme du front de flamme et de l’expansion des gaz. L’analyse statistique des mesures conditionnée sur la richesse locale a permis de caractériser les propriétés de la flamme soumise à une stratification de richesse dans un écoulement laminaire et turbulent, en particulier en mettant en évidence un effet mémoire. / In order to better understand the stratified combustion, the propagation of flame through stratified mixture field in laminar and turbulent flow conditions has been studied by using combined PIV/PLIF techniques. A great emphasis was placed on developing methods to improve the accuracy of local measurements of flame propagation. In particular, a new PIV approach has beendeveloped to measure the local fresh gas velocity near preheat zone of flame front. To improve the resolution of measurement, the shape of interrogation window has been continuously modified based on the local flame topology and gas expansion effect. Statistical analysis of conditioned local measurements by the local equivalence ratio of flames allows the characterization of theproperties of flame propagation subjected to the mixture stratification in laminar and turbulentflows, especially the highlight of the memory effect. Combustion stratifiée Flamme turbulente Flamme laminaire Piv Plif Stratified combustion Local laminar burning velocity Piv Plif Adaptive interrogation window scheme Local fresh gas velocity Axi-symmetrical injection Hot wire anemometry Flame front extraction
14	CAR T-cellsterapi med axikabtagen-ciloleucel (YESCARTA): En systematisk litteraturöversikt av den senaste landvinningen i behandling av högmaligna B-cellslymfom Pålsson Östman, Marcus January 2024 (has links) Bakgrund: Diffust storcelligt B-cellslymfom (DLBCL) är en högmalign cancersjukdom som drabbar B-lymfocyterna, en typ av vita blodkroppar. Incidensen i Sverige är omkring 600 fall per år. Utan effektiv behandling sker sjukdomsprogressionen med ett snabbt förlopp. Under de senaste två årtiondena har behandlingarna som använts i första och andra linjen kunnat bota 60–70% av patienterna med DLBCL. För patienterna som inte svarat på standardbehandlingarna är prognosen mycket allvarlig. YESCARTA är ett nytt genterapiläkemedel som består av patientens egna T-celler modifierade med en chimär antigen receptor (CAR). När CAR T-cellen binder till B-lymfocyter frisätts inflammatoriska mediatorer som orsakar celldöd av både normala och tumöromvandlade B-lymfocyter. Syfte: Hur påverkar behandling med YESCARTA den totala överlevnaden (OS), responsfrekvensen (ORR), progressionsfri överlevnad (PFS), händelsefri överlevnad (EFS), responsduration (DOR), samt komplett och partiell respons (CR & PR) hos patienter med diffust storcelligt B-cellslymfom (DLBCL)? Detta arbete syftar till att systematiskt sammanställa och utvärdera befintlig vetenskaplig litteratur om YESCARTA för att besvara denna frågeställning. Metod: Litteratursökningen utfördes i PubMed. Samtliga MeSH-termer för läkemedlet YESCARTA konsoliderades och filter för observation- och kliniska studier applicerades. Sökningen genererade 34 artiklar, varav 10 kunde inkluderas. Exklusion skedde huvudsakligen av studier som undersökt annat än den terapeutiska effekten av YESCARTA. Resultat: Majoriteten av studierna var av typen fas II. En fas III-studie med varianter i uppföljningstid och undergruppsanalys inkluderades. YESCARTA förefaller vara överlägsen standardbehandling i alla utfallsmått. Resultatet är mest robust för ORR, EFS och PFS. Cirka fyra av fem patienter kan förväntas uppnå remission efter behandling med YESCARTA. Effektfördelen av YESCARTA i OS och DOR är osäker med avseende på statistisk signifikans. Slutsats: För särskilt utvalda patienter med DLBCL är YESCARTA ett effektivt behandlingsalternativ. Review systematic review Axicabtagen-ciloleucel Diffuse large B-cell lymphoma DLBCL lymphoma Yescarta Axikabtagen-ciloleucel axi-cel lymfom diffust storcelligt B-cellslymfom CAR T CAR-T systematisk litteraturöversikt litteraturöversikt översikt Pharmaceutical Sciences Farmaceutiska vetenskaper
15	A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC) Yang, Xiaokun 25 March 2016 (has links) With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs. Advanced Encryption Standard (AES) High Performance Bus Architecture Design Automation High Security Internet-of-Things (IoT) Low Power Performance Evaluation Methodology System-on-Chips (SoC) Universal Verification Methodology (UVM) Valid Data Bandwidth Computer and Systems Architecture Digital Circuits Hardware Systems
16	Modeling, Simulation, and Injection of Camera Images/Video to Automotive Embedded ECU : Image Injection Solution for Hardware-in-the-Loop Testing Lind, Anton January 2023 (has links) Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). The purpose of this degree project is to research and develop a proof of concept for in-house development of an image injection solution (IIS) on the IU in the HIL testing environment. A proof of concept could confirm that editing, customizing, and having full control of the IU is a possibility. This project was initiated by Volvo Cars to optimize the use of the HIL testing environment currently available, making the environment more changeable and controllable while the IIS remains a static system. The IU is an MPSoC/FPGA based design that uses primarily Xilinx hardware and software (Vivado/Vitis) to achieve the necessary requirements for image injection in the HIL testing environment. It consists of three stages in series: input, image processing, and output. The whole project was divided in three parts based on the three stages and carried out at Volvo Cars in cooperation by three students, respectively. The author of this thesis was responsible for the output stage, where the main goal was to find a solution for converting, preferably, AXI4 RAW12 image data into data on CSI2 format. This CSI2 data can then be used as input to serializers, which in turn transmit the data via fiber-optic cable on GMSL2 format to the VCU. Associated with the output stage, extensive simulations and hardware tests have been done on a preliminary solution that partially worked on the hardware, producing signals in parts of the design that could be read and analyzed. However, a final definite solution that fully functions on the hardware has not been found, because the work is at the initial phase of an advanced and very complex project. Presented in this thesis is: important theory regarding, for example, protocols CSI2, AXI4, GMSL2, etc., appropriate hardware selection for an IIS in HIL (FPGA, MPSoC, FMC, etc.), simulations of AXI4 and CSI2 signals, comparisons of those simulations with the hardware signals of an implemented design, and more. The outcome was heavily dependent on getting a certain hardware (TEF0010) to transmit the GMSL2 data. Since the wrong card was provided, this was the main problem that hindered the thesis from reaching a fully functioning implementation. However, these results provide a solid foundation for future work related to image injection in a HIL environment. ADAS AD ADS HIL Hardware in the loop Hardware-in-the-loop ECU VCU Automotive Embedded System Systems Camera Image Video Injection FPGA MPSoC Vivado Vitis VHDL Volvo Cars FMC HPC LPC MIPI CSI2 GMSL2 AMBA AXI4 Xilinx RTL Implementation Synthesis Intelectual Property IP Vehicle computing unit Electronic control unit TEB0911 TEF0007 TEF0010 CSI2 Tx CSI2 Tx Subsystem Zynq SerDes AXI4 AXI4-Lite Programmable Logic PL Processor System PS C C++ Video test pattern generator VTPG Axi traffic generator ATG Ultrascale+ Virtual input/output VIO Integrated logic analyzer ILA Interface Unit Embedded Systems Inbäddad systemteknik

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