The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a systematic approach of design, analysis and simulation. The metallic SET transistors considered in this work are fabricated within the chip interconnect layers using CMOS back-end-of-line (BEOL)-compatible processing. The CMOS process integration can be divided into front-end-of-line (FEOL) and BEOL processes. The FEOL includes processes required to form isolated CMOS transistors whereas BEOL is the second portion of the IC fabrication where the devices get interconnected through the wiring using multiple layers of dielectrics and metals. Therefore, metallic SET circuits can be easily stacked above the CMOS platform presenting a low cost, low thermal budget, improving the overall yield at high-volume production of highly integrated systems. This considerably decreases the interconnect parasitics and increases the density of functions while maintaining the overall acceptable performance. Many problems such as low current drivability, delay and small voltage gain that hinder SET technology for its implementation in integrated circuits can be alleviated by intelligent circuit design. Although a complete replacement of CMOS by SETs is unlikely in the near future, an augmentation of CMOS with SETs is desirable if interfacing from and to CMOS works well. Interfacing from CMOS to SET circuitry is simple as the current and voltage levels are small and in accessible range. But interfacing CMOS from SET circuits is delicate due to SET logic's low current driving capability for CMOS and its interconnect. There is no concrete research on the interface issue wherein a SET-only circuitry drives a CMOS and its interconnects. For such hybridization to become possible, it is necessary to demonstrate the SET logic driving capability for CMOS with sufficient current drive and output voltage. The core SET logic can be designed to operate at low voltage, but at the interface the output of the SET logic must be in a voltage range that can be fed to a CMOS input for proper logic functionality. It is hence necessary to develop and adopt a systematic design methodology for such hybrid circuits at a specific technology node for room temperature operation. In this thesis we will look at a generalized design methodology that can be applied to (a) develop a fabrication model with parasitic effect of a hybrid SET-CMOS and SET-only circuits, (b) design and analyze the SET based fundamental building block in hybrid SET-CMOS or SET-only circuit and (c) simulate such a circuitry to assess its merits. More specifically, we will address the interfacing issue of such hybrid circuits in which we exploit the maximum capability of a SET logic in terms of driving capability, voltage response and power for a room temperature operation. The result of this research motivates the application of SET logic in 2 stages realizing some properties beyond those of CMOS devices. The first stage is the heterogeneous integration at chip level around a CMOS core. In such a circuitry, the SET introduces new functionalities such as reconfigurable logic, random number-based circuits, and multiband filtering circuits that can be combined with CMOS based general purpose processors or I/O signal restoration. The second stage of application is to use a new information processing technology focussed on a "new switch" exploiting a new state variable to provide functional scaling substantially beyond that attainable solely with ultimately scaled CMOS.

This thesis follows the design process of a back end. The purpose of this back end is to interface a radar front end, developed by Acreo Swedish ICT, and stream it’s digitalized output to a PC using Universal Serial Bus (USB) 3.0. The front end, which acts as a basis for this project, is a Frequency Modulated Continuous Wave (FMCW) radar which is connected to the back end by a header. The header connects the digitalized radar signals, together with two SPI-buses and a few GPIO pins. Thus, enabling configuration and set up of the front end board via a PC. The result of the thesis is a data acquisition board that can be used to interface with the front end. The implemented back end features an FPGA to handle the ADC data from the front end, so the board has DSP capabilities, but can also stream the raw radar data. The FPGA is connected to a USB 3.0 controller through a 32-bit parallel interface. The configuration of the front end, via the produced board, is verified in it’s functionality and can be controlled by a PC using a simple GUI. Commands are sent through the USB 3.0 controller to a front end controller which handles the communication. Since getting the hardware functional has been the main objective of the thesis, the project has been deemed to be successful. The final result is a back end radar prototype, which has the requested core hardware functionalities. In addition to this, the prototype has the capacity to act as a platform for further expanding its functionality after a hand over of the project to Acreo Swedish ICT.

Accessibility in back-end development is often overlooked, with the majority of discussions and efforts centered on front-end design. To make applications usable for a wider audience, developers must also prioritize incorporating accessibility from the back-end. Back-end web accessibility encompasses the design and development of web-based systems and applications that are accessible to all users, including those with disabilities. This involves optimizing the underlying code and infrastructure for accessibility and implementing features that enable users with disabilities to navigate and interact with the site or application. Ensuring back-end web accessibility is crucial for creating an inclusive online environment accessible to everyone, regardless of their abilities. Presently, there is a significant gap in research regarding back-end accessibility specifics. This study investigates the challenges in implementing back-end accessibility, explores best practices, and aims to facilitate future research on its impact on user experience and system performance.

Ces dernières années la miniaturisation des microsystèmes atteint la limite physique de leur développement. Ainsi une de voie d’innovation dans l’industrie des semiconducteurs est l’intégration des fonctionnalités supplémentaires au sein des composants déjà existants.Le projet consiste à intégrer, dans une même couche métallique d’interconnexion CMOS, un MEMS capable, par sa rotation, d’établir un contact électrique.Les verrous se situent dans la libération des parties mobiles par dissolution de l’oxyde environnant (déformation hors plan sous l’effet des contraintes résiduelles, stiction, présence de résidus qui empêchent le contact), dans l’actionnement (densité de courant, répétabilité, durabilité, fiabilité) ainsi que, la capacité d’établir un vrai contact électrique à faible résistance (aire réelle / apparente du contact des surfaces rugueuses, pollution du contact).Le travail réalisé a porté sur la conception, le design et la simulation des microsystèmes afin de surmonter ces difficultés et / ou d’étudier le comportement et mesurer les effets. / In recent years the miniaturization of microsystems is reaching the physical limit of its development. Thus, a path of innovation in the semiconductor industry is additional functionalities in existing components.The project consists to integrate a MEMS, within the same metal interconnect of CMOS layer which, by rotating, can establish an electrical contact.The obstacles are in the release of the moving parts by dissolution of the surrounding oxide (out of plane deformation under the effect of residual stress, stiction, residues which prevent contact), in the actuation (current density repeatability, durability, reliability) and, for ohmic switches, the ability to establish a real electrical contact with low resistance (real / apparent area of contact with rough surfaces, contact pollution).The work carried out has focused on conception (design) and simulation of microsystems to overcome these difficulties and / or to study the behavior and measure the effects.

Syftet med det här examensarbetet är att presentera process och erfarenheter från mitt konstnärliga musikproduktionsprojekt som genomförts under mitt sista år av min masterutbildning. Genomförandet har bestått av att skapa ett svenskt popmusikalbum där låtar har skapats enskilt, genom samarbeten och tre verk har blivit slutförda och distribuerats på streamingtjänster så som Spotify och YouTube. Vidare är syfte att presentera en modell med hjälp av mitt konstnärliga arbete där det prövas potentiella omformuleringar för yrkesroller inom låtskapande. Dessa termer ska i sin tur underlätta rolldefinition inom låtskapande och även ge utrymme för att förtydliga den ideella rätten som medverkande i ett konstnärligt verk har. Med utgångspunkt till att musikproducenten ofta hamnar i en multikompetent position så har jag valt att låna begrepp från systemutvecklarens yrkesvärld för att skapa modellen. Begreppen jag valt att låna består av back-end, front-end och full-stack och avsikten är att bryta upp paraplybegrepp såsom ”låtskrivare, producent och performer” och även kunna bidra till tydligare rekryteringsprocesser för samarbeten inom låtskapande. / The purpose of this master’s thesis is to present the process and experiences of my music production project that was carried out during the last year of my masters’ studies. The project’s creative content is a Swedish pop album which created through collaborative and independent work. Three single releases and one music video have been released and distributed through the course of the project on streaming platforms such as Spotify and YouTube. In addition to the making of the album I have chosen to create a model to use as a frame for potential recruitment instances of creative collaborations, improve role definition and develop a more accurate method to credit rights holder’s moral credentials as a contributor to an artistic work. The root cause of this model is that a music producer often finds themselves as a multicompetent keyperson in creative collaborations where the lines between different professions overlap. The model is inspired of the software developers job terminology and aims to break up umbrella concept roles such as “songwriter, producer and performer” to facilitate the recruiting process of creative collaborations within the crafting of songs. The terminologies inspired out of the software developer’s professions are back-end, front-end and full-stack.

At Halmstad University, the CatFish Project aims to measure and report on water quality. The System includes three components, one to measure, one to present, and one to handle data. This thesis explains the development of a cloud-based back-end solution created for the CatFish project. The solution connects IoT devices via the MQTT protocol. The devices are connected to collect and transfer data, later stored in a database, to be presented to a web application via a REST or WebSocket API. The solution is implemented with Amazon Web Services as a cloud service provider and is hosted on their platform. / Vid Högskolan i Halmstad ämnar CatFish projektet att mäta och rapportera om vattenkvalitet. Systemet innehåller tre komponenter, en för att mäta, en för att presentera och en för att hantera data. Denna rapport kommer detaljera utvecklingen av den molnbaserade lösning som skapats för projektet, i syfte att hantera data. Lösningen kopplar samman IoT enheter via MQTT protokollet, dessa enheter samlar och skickar sedan data till molnet, där denna data samlas i en databas, för att senare presenteras via en webbapplikation. Datan skickas till denna via REST eller WebSocket APIer. Lösningen implementeras med Amazon Web Services som plattform och det även på denna plattform som lösningen körs.

With the continued progression of Moore’s law into the sub-14nm technology nodes, interconnect RC and power dissipation scaling play an increasingly important role in overall product performance. As critical dimensions in the mainstream Cu/ULK interconnect system shrink below 30nm, corresponding increases in relative process variation and decreases in overall process window mandate increasingly complex integrated solutions. Traditional metallization processes, e.g. PVD barrier and seed layers, no longer scale for all layout configurations as they reach physical and geometric limitations. Interactions between design, OPC, and patterning also play more and more critical roles with respect to reliability and yield in volume manufacturing; stated simply, scaling is no longer “business as usual”. Restricted design layouts, prescriptive design rules, novel materials, and holistic integration solutions each therefore become necessary to maximize available process windows, thus enabling new generations of cost-competitive products in the marketplace.

<p>With increasing demands in terms of timing, area and power, today’s ASIC (Application Specific Integrated Circuit) designers are faced with new problems as technology emerges. Ericsson has started to work in 65 nm and realized that the methods used in previous, larger technologies, does not offer good enough correlation between synthesis and the results after physical placement. This leads to several expensive and time consuming iterations back and forth between Ericsson and the ASIC vendor.</p><p>In order to narrow the gap between Ericsson and the ASIC vendor, and hence increase correlation, physical planning has been identified as a possible solution. Cadence First Encounter, part of the Cadence Encounter digital IC design platform, is an advanced tool for silicon virtual prototyping. The tool basically brings back-end placement knowledge to front-end ASIC designers.</p><p>This master’s thesis main goal is to evaluate Cadence First Encounter and investigate how it could be integrated with Ericsson’s design flow. The tool has been tested on previous designs with known issues and the results are positive. By using the prototype work flow in First Encounter that is described in this report, it is possible to identify and correct issues with the netlists in time, which will help shortening the lead time in projects and hence also the time to market.</p>

With increasing demands in terms of timing, area and power, today’s ASIC (Application Specific Integrated Circuit) designers are faced with new problems as technology emerges. Ericsson has started to work in 65 nm and realized that the methods used in previous, larger technologies, does not offer good enough correlation between synthesis and the results after physical placement. This leads to several expensive and time consuming iterations back and forth between Ericsson and the ASIC vendor. In order to narrow the gap between Ericsson and the ASIC vendor, and hence increase correlation, physical planning has been identified as a possible solution. Cadence First Encounter, part of the Cadence Encounter digital IC design platform, is an advanced tool for silicon virtual prototyping. The tool basically brings back-end placement knowledge to front-end ASIC designers. This master’s thesis main goal is to evaluate Cadence First Encounter and investigate how it could be integrated with Ericsson’s design flow. The tool has been tested on previous designs with known issues and the results are positive. By using the prototype work flow in First Encounter that is described in this report, it is possible to identify and correct issues with the netlists in time, which will help shortening the lead time in projects and hence also the time to market.

Fluoride based chemical systems are widely used at various stages in microelectronic processing, particularly for wet cleaning and etching applications. Some examples include the use of semi aqueous fluoride (SAF) solutions in back end of line cleaning, the use of dilute HF solutions as etchants for SiO2 and HF-HNO3 or HF-H2O2 solutions as isotropic etchants for silicon. In this work, the use of fluoride based solutions for two applications relevant to semiconductor processing are considered.In the first part of the study, cleaning of post plasma etch residues generated during fabrication of copper damascene structures was investigated in semi aqueous fluoride (SAF) formulations based on dimethyl sulfoxide and ammonium fluoride. Formulations designed for residue removal should be able to remove the residue effectively, without causing critical dimension loss during the process cycle. A systematic evaluation of solution variables (solvent content and pH) was conducted and the extent of removal of model copper oxide films and selectivity over copper and carbon doped oxide (CDO) films were used as metrics to evaluate the formulations. Results of the study indicate that the presence of solvent is necessary to achieve reasonable etch selectivity over dielectric films. Additionally, a removal end point detection technique based on electrochemical impedance spectroscopy was developed, which could potentially help in the optimization of cleaning time with minimal dielectric loss. This method was applied to monitor the removal of copper oxide films as well as residue from patterned test structures.In the second part of the study, electrochemical formation of porous silicon films in hydrofluoric acid (HF) solutions was investigated, for potential applications in advanced packaging. Specifically, porous silicon formation in solution mixtures containing HF, acetic acid and peroxide, was studied. The effect of variables including current density, substrate resistivity, HF, acetic acid and peroxide concentration, on key porous film characteristics such as growth rate, porosity and microstructure, was explored. Addition of peroxide was found to significantly increase the porosity and growth rate of the film, as a result of enhanced chemical dissolution and films with porosities as high as 95% were obtained. Additionally, in solutions containing peroxide, a variety of microstructural features, such as nanopores, micron sized pores, truncated pyramidal structures and silicon needles were observed, under various fabrication conditions.