Battery energy storage system (BESS) is promising to be implemented in residential applications for supporting PV integration, load shifting, and backup power purposes. For this application, 48V second-life battery draws more and more attentions for their cost-effectiveness, safe voltage level, reliability, and potential large market. This thesis proposes the comprehensive control and design of an isolated battery-driven grid interface (IBDGI) with the dual-active-bridge (DAB) converter for residential applications with 48V battery pack. The three-phase DAB converter is a promising candidate as the front-end DC/DC converter in the two-stage IBDGI due to its high efficiency, high power density, and low capacitance requirement. An effective design strategy for the three-phase DAB converter is proposed based on the zero-voltage-switching (ZVS) zone and back-ow power to achieve high efficiency for a wide operating voltage range and different load conditions. Based on the power loss model, an easily-implemented variable switching frequency operating method is proposed to further increase the efficiency at light load conditions. The dead-time effect is observed in the three-phase DAB converter. To avoid the dead-time effect and better understand the phenomena, a comprehensive analysis is proposed. All the cases of the dead-time effect in the three-phase DAB converter are analyzed in terms of the buck, boost, and matching states. The expressions of the transmission power, constraint conditions, and key time of the dead-time effect are derived for each state. The operation waveforms of the dead-time effect are also presented. The hybrid capacitor bank composed by the LC resonant lter with electrolytic capacitor and lm capacitor is utilized for the DC bus of the IBGDI. The electrolytic capacitors work as passive decoupling purpose while the lm capacitor is responsible for high switching harmonic ltering. Moreover, a current sharing method between the hybrid capacitor bank is proposed to extend the electrolytic capacitor's life. The LCL single-phase inverter is applied for the downstream of the IBDGI. A step-by-step design procedure of the LCL lter with passive damping is proposed for the 120V/240V dual grid-tied and standalone modes. The PR controllers are also designed for the LCL inverter for standalone and grid-tied modes. At the system level, a novel second harmonic current (SHC) reduction strategy is proposed for the IBDGI with the three-phase DAB converter by adding a load current feedforward (LCFF) path to the DAB voltage closed-loop controller. This method will suppress the SHC without modi cations of the original controller's bandwidth, which make it easy to be implemented. The small-signal model of the three-phase DAB converter is provided and veri ed by the step response. The parameter sensitivity analysis for the LCFF method is proposed to show that the SHC is well suppressed within ±20% parameter error. The proposed converter and control methods are veri ed by simulation and experimental results. / Thesis / Doctor of Philosophy (PhD)

Due to modularity and easy scalability, modular multilevel converters (MMCs) are deemed the most suitable for high-voltage and medium-voltage power conversion applications. However, large module capacitors are usually required in MMCs to store large circulating power of line-frequency and its harmonics that flow through the capacitors. Even though several methods for minimizing the circulating power have been proposed in the literature, there is still the need for a systematic and simplified approach of addressing these control strategies and evaluating their efficacy. Moreover, the generally accepted feedback control architecture for the MMC is complicated, derived through a rigorous mathematical analysis, and therefore, not easy to intuitively comprehend. Recently, a method of modeling of the MMC based on state-plane analysis and coordinate transformation, is proposed in the literature. Based on the state-plane analysis, two kinds of circulating power in the MMC are identified that are orthogonal to each other. This means these two circulating power can be controlled individually without affecting each other. To control these circulating power, in the literature, a decoupled equivalent circuit model is developed through the coordinate transformation which clearly suggests a means for minimizing these circulating power. Further extending this work, in this thesis, the existing control concepts for reducing the circulating power are unveiled in a systematic and simplified manner utilizing the decoupled equivalent circuit model. A graphical visualization of circulating power using the state-planes is provided for each control strategy to readily compare its efficacy. Moreover, the generally accepted control architecture of the MMC is presented in an intuitive and simplified way using the decoupled circuit model. The important physics related to control implementation, originally hidden behind the complicated mathematics, is explained in detail. / Master of Science / A power converter is an electrical device that converts electrical energy from one form to another in order to be compatible with the load demand. A typical power converter consists of semiconductor switches, inductor, capacitor etc. These power converters are required in a wide range of applications: automotive and traction, motor drives, renewable energy conversion, energy storage, aircraft, power generation, transmission, and distribution, to name a few. Many of these applications are continuously increasing their power capacity to handle the escalating demands of energy that exist due to rising population numbers, industrialization, urbanization etc. Consequently, it has been a responsibility of power electronics engineers and researchers to develop power converters that can handle high voltages and high currents. Multilevel power converters have been the key-enabling developments that can withstand high-voltages while using traditional low-voltage semiconductor switches. Several multilevel converters such as the neutral point clamped converter, flying capacitor converter, cascaded H-bridge converter, modular multilevel converter (MMC) etc. have been developed and commercialized in the last two decades. Among them, the MMC is a widely accepted topology for medium- and high-voltage power conversion applications. In an MMC, several modules are stacked together in series, and each module consists of semiconductor switches and a capacitor. The series connection of the modules enables the MMC to handle high-voltage power conversion using low-voltage traditional semiconductor switches. The voltage rating of an MMC can be easily scaled-up by simply increasing the number of modules in each arm. Moreover, since several identical modules are connected in each arm, the structure of the MMC is highly modular which helps greatly in manufacturing and design. Nonetheless, in MMCs, generally large circulating power flow to the capacitor in each module, which leads to significant voltage ripples. To suppress these voltage ripples, a large capacitor is required in each module, leading to large size and weight of the converter. In the literature, several control strategies have been proposed to minimize the circulating power. However, there is still the need for a systematic and simplified approach of addressing these control strategies and evaluating their efficacy. Moreover, the generally accepted feedback control architecture for the MMC is complicated, derived through a rigorous mathematical analysis, and therefore, not easy to intuitively comprehend. Recently, a decoupled equivalent circuit model has been developed in the literature. This model clearly explains the process of power flow in the MMC between input and output and the nature of the circulating power. The equivalent circuit model provides the circulating power, that are orthogonal to each other, meaning they can be controlled individually without affecting each other. Moreover, the equivalent circuit model clearly suggests a means for minimize the circulating power by providing two "ideal" control laws. Further extending this work, in this thesis, the existing control concepts for reducing the circulating power are unveiled in a systematic and simplified manner utilizing the decoupled equivalent circuit model. Moreover, the generally accepted control architecture of the MMC is presented in an intuitive and simplified way via the decoupled circuit model. The important physics related to control implementation, originally hidden behind the complicated mathematics, is explained in detail.

The demand for high-power converters are surging due to applications like renewable energy, motor drives and grid-interface applications. Typically, these converters’ power ranges from tens of kilowatts (kW) to several megawatts (MW). To reach such high power levels the converter voltage ratings must increase, as the current ratings cannot be reached by the available devices or because the system losses become excessive. To address this, two strategies can be utilized: multilevel topologies (e.g. Multilevel Modular Converter or Flying Capacitor Multilevel Converter) and high voltage switches. For medium voltage applications, the most commonly employed switches are the IGBT and the IGCT. Both are silicon-based technology and are limited to a rated voltage of 6.5 kV and 4.5 kV, respectively. Often, these devices switching frequency are limited to less than 1 kHz. To expand the frontiers of medium voltage converters and to demonstrate the capabilities of wide band gap devices in medium voltage, a 7-level 13.8 kV AC 22 kV DC 1.1 MW flying capacitor multilevel converter based on 10 kV SiC MOSFET with 2.5 kHz switching frequency was designed and constructed. Given the complexity of a multilevel topology, the high voltage levels, and the critical nature of the loads, a failure in a high-power converter can incur significant costs, long service downtime, and safety risks to personnel. Hence, understanding the failure modes of these converters is essential for designing protections and mitigation strategies to prevent or reduce the risks of failures. Furthermore, the adoption of 10 kV SiC MOSFET introduces additional challenges in terms of protection. Despite their well-known benefits, these devices exhibit shorter energy withstanding time compared with their silicon counterpart, and increased insulation stress resulting from the high dv/dt imposed by the fast-switching transient at higher voltages. In this context, a failure mode analysis was conducted for the converter aforementioned. The analysis examined the fault dynamics and evaluated the protections schemes at the converter level. The study identified a failure mechanism between cells, so called Cell Short- Circuit Fault (CSCF), capable of damaging the entire phase-leg. In response, a protection scheme based on TVS (Transient Voltage Suppression) diodes was designed to prevent extremely imbalanced cell voltages and failure propagation. Because of the high electric field intensity environment of the converter, an FEA (Finite Element Analyses) simulation is performed to verify and control the electric field (E-field) intensity within the protection module itself and in the converter assembly. Next, the protection module insulation design was successfully verified in a Partial Discharge (PD) experiment. In sequence, an experimental verification utilizing an equivalent circuit based on the fault model demonstrated the efficacy of the protection module. Waveforms extracted while the converter was operating showing the protection module acting during a fault are presented and analyzed. Finally, the influence of the protection module in the switching of the 10 kV SiC MOSFET was evaluated via a double pulse test (DPT), revealing negligible effects on the converter performance. / Center of Power Electronics Systems (CPES) Department of Energy (DoE) / Master of Science / Due to governmental policies and market opportunities renewable energy (e.g. solar and wind energy) is increase its share in the electricity generation in the US and around the world. This scenario poses challenges regarding the stability of the grid and variation in the generation along the day. One of the alternatives to alleviate the problem is to use highpower converters that provides a interface between grid and manufacturing plants. This type of converter have bidirectional capabilities and can store the energy generated by solar farms during the day and return it to the grid at night for example. Moreover, it can provide grid support capabilities in terms of variation of frequency and voltage. To expand on the grid interface converters application concept, a medium voltage power converter in 22 kV DC and 13.8 kV AC is designed utilizing novel techniques and the latest technologies in semiconductors, 10 kV SiC MOSFETs. The benefits of this design are a small form factor, high efficiency, immunity to electromagnetic interference and power quality. This work presents a failure mode analysis of the power converter aforementioned, the analysis examined the fault dynamics and an evaluation of the protections schemes at the converter level. The failure analysis revealed the need of a protection scheme extremely imbalanced cell voltages and failure propagation. Hence, a protection module based on TVS (Transient Voltage Suppression) diodes was successfully designed and tested. Due to the high voltages present in this equipment, an FEA (Finite Element Analyses) simulation is performed to verify and control the electric field (E-field) intensity within the protection module itself and in the converter assembly. Experimental results are provided for insulation design integrity (partial discharge test), for the efficacy of the protection module against the fault, and for the impact of the protection module on the operation performance.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

Indiana University-Purdue University Indianapolis (IUPUI) / This research proposes state-of-the-art multilevel converter topologies and their modulation strategies, the implementation of a conventional flying-capacitor converter topology up to four-level, and a new four-level flying-capacitor H-Bridge converter confi guration. The three phase version of this proposed four-level flying-capacitor H-Bridge converter is given as well in this study. The highlighted advantages of the proposed converter are as following: (1) the same blocking voltage for all switches employed in the con figuration, (2) no capacitor midpoint connection is needed, (3) reduced number of passive elements as compared to the conventional solution, (4) reduced total dc source value by comparison with the conventional topology. The proposed four-level capacitor-clamped H-Bridge converter can be utilized as a multilevel inverter application in an electri fied railway system, or in hybrid electric vehicles. In addition to the implementation of the proposed topology in this research, its experimental setup has been designed to validate the simulation results of the given converter topologies.

Le « Lithium-Ion Capacitor » (LiC) est un supercondensateur hybride dont les caractéristiques peuvent être placées entre un condensateur à double couche électrique (supercondensateur) et une batterie lithium-ion. Il possède des densités d’énergie et de puissance intermédiaires grâce à sa composition hybride à base d'une électrode positive en charbon actif identique à celle d’un supercondensateur et d'une électrode négative en carbone pré-lithié identique à celle d’une batterie lithium-ion. L'objectif de cette thèse est d'étudier le vieillissement des LiC industrialisés aussi bien dans le cadre d’un vieillissement en stockage (calendaire) qu’en utilisation (cyclage). Un de leur spécificité principale concerne l’évolution particulière de leur capacité en fonction de la tension à leurs bornes (C(V)). Le premier type de vieillissement qu’est le vieillissement calendaire permet de représenter le comportement des LiC lorsqu’ils sont stocker avant utilisation ou lorsqu’ils sont en veille. La dégradation de leurs paramètres liée au vieillissement, est alors essentiellement influencée par leur tension et la température. Des essais de vieillissement à trois tensions caractéristiques et deux températures différentes sont étudiés. L’évolution des impédances des cellules a été suivie tout au long du vieillissement afin d’identifier un modèle électrique de suivi du vieillissement dont les paramètres sont liés aux phénomènes électrochimiques. Par ces essais, la meilleure tension de stockage des LiC, permettant la prolongation de leur durée de vie a été mise en évidence. Par ailleurs, des mécanismes de vieillissement différents d’une tension caractéristique à l’autre sont révélés et soulignent la spécificité de fonctionnement des LiC. Ces résultats ont été confirmés par des analyses post-mortem. Le second type de vieillissement étudié est le vieillissement par cyclage qui prend en compte l'impact du courant sur la durée de vie des LiC. Le choix des profils de courant de cyclage a été effectué en considérant le principe de fonctionnement électrochimique des LiC. Les évolutions des impédances et des courbes C(V) des cellules sont comparées et interprétées. Les mécanismes de vieillissement prenant naissance lors du cyclage continu sont abordés. Ils dépendent de la fenêtre de potentiel sur laquelle les LiC fonctionnent pendant leur utilisation. La fenêtre de tension optimale qui assure une longue durée de vie des LiC est aussi mise en évidence / Lithium-Ion Capacitors (LiCs) are the new emerging technology of hybrid supercapacitors that combines the advantages of conventional supercapacitors and lithium-ion batteries. They provide intermediate energy and power densities due to their hybrid composition based on a positive electrode made of activated carbon similar to that of supercapacitors and a negative electrode made of pre-lithiated carbon similar to that of lithium-ion batteries. The aim of this thesis is to study the aging of commercial LiCs using two accelerated aging procedures: calendar aging and cycle aging. One of their main particularities concerns the nonlinear capacitance evolution with respect to their voltage (C(V) curve). The first accelerated aging test is related to the calendar life of LiCs that represents their behavior independently of their usage. The degradation of their parameters due to aging is mainly affected by the voltage and the temperature only. These tests were applied to several cells at three different voltage values and two temperatures. The evolution of their impedances were followed during the whole aging period in order to identify an electrical model that can accurately describe the progress of aging and that possesses electrochemically meaningful parameters. The best voltage value that ensures the extension of the lifetime of LiCs was identified using the results of these tests. In addition, aging mechanisms that extremely depend on the applied voltage value were identified. They highlight the particularity of the functioning of LiCs. These results were confirmed using post-mortem analyses. The second accelerated aging test is the cycle aging that assesses the impact of the current on the life cycle of LiCs. The choice of current profiles was based on the electrochemical operating principle of LiCs. The evolution of the impedances and the C(V) curves of LiCs were compared and analyzed. Aging mechanisms produced during cycle aging were also evaluated. They depend on the voltage range in which the LiC operates. The optimal voltage window that guarantees a long lifetime of LiCs was highlighted

Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues are extremely helpful for curing many neural injuries and cognitive diseases. One method to discover this field is by designing a chip embedded in brains with probes to actual neurons. It is obvious that batteries are not practical for these applications and thereby RF radiation is used as power sources, revealing that chips should operate under a very low power supply. Since neural signals are analog waveforms, analog-to-digital converter (A/D converter, ADC) is the key component in a neural recorder chip. This thesis proposes the complete design of a low power 8-bit successive approximation register (SAR) A/D converter for use in a wireless neural recorder chip, realizing the function of digitizing a sampled neural signal with a frequency distribution of 10Hz to 10kHz. A modified energy-saving capacitor array in the SAR structure is provided to help save power dissipation. Therefore, the ADC shall operate within a power budget of 20­μW maximum from a 1­V power source, at a clock frequency of 500kHz corresponding to a conversion rate of 55.5-kS/s. All the circuits are designed and implemented based on the IBM/Global Foundries 8HP 130nm BiCMOS technology. Simulations of schematic and layout versions are done respectively to verify the functionality, linearity and power consumption of the ADC. Key words: Successive approximation register analog-to-digital converter (SAR-ADC), low power design, energy-saving capacitor array, neural recorder applications

Orientador: Ruben Augusto Romero Lazaro / Resumo: Este trabalho apresenta uma proposta baseada na meta-heurística Busca Tabu, chamada de Busca Tabu Reformulada para resolver o problema de operação ótima dos sistemas de distribuição, utilizando uma estratégia integrada de reconfiguração e alocação de bancos de capacitores fixos e chaveados para obter a topologia radial que apresente o menor custo de operação. Para encontrar a topologia radial inicial foi aplicado o algoritmo de Prim, em que foi obtida uma solução reconfigurada, e essa solução encontrada foi submetida à uma heurística para alocação de capacitores fixos e chaveados. A proposta de solução inicial é submetida ao algoritmo de Busca Tabu Reformulada que utiliza uma vizinhança que considera como solução vizinha uma topologia vizinha da topologia radial corrente e com a proposta de alocação de bancos de capacitores modificada. Como proposta da metodologia Busca Tabu Reformulada o procedimento é repetido até um critério de parada definido. Todos os programas foram escritos em linguagem FORTRAN 77. Os algoritmos propostos foram testados com os sistemas de 33, 70, 84 e 136 barras. / Abstract: This paper presents a proposal based on the Tabu Search metaheuristic called Tabu Search Reformulated to solve the problem of optimal operation of the distribution systems, using an integrated strategy of reconfiguration and allocation of fixed and switched capacitor banks to obtain the radial topology which presents the lowest operating cost. To find the initial radial topology the Prim algorithm was applied, in which a reconfigured solution was obtained, and this solution was submitted to a heuristic for the allocation of fixed and switched capacitors. The initial solution proposal is submitted to the Reformulated Tabu Search algorithm that uses a neighborhood that considers as neighbor solution a neighboring topology of the current radial topology and with the proposed allocation of modified capacitor banks. As a proposal of the Tabu Search Reformulated methodology, the procedure is repeated up to a defined stop criterion. All the programs were written in FORTRAN 77 language. The proposed algorithms were tested with the 33, 70, 84 and 136-node systems. / Mestre

Este trabalho tem o objetivo de utilizar métodos de otimização não linear a fim de desenvolver uma metodologia eficiente para alocação de bancos de capacitores visando a eliminar violações de tensão em redes de distribuição. A aplicação de capacitores em paralelo a sistemas elétricos de potência é comumente empregada com o intuito de se obter melhor controle do fluxo de potência, gerenciamento do perfil de tensão, correção do fator de potência e minimização de perdas. Tendo em vista estes benefícios, a metodologia deste trabalho se dará por meio da resolução de um problema de programação não linear associada com a aproximação linear da relação potência reativa versus tensão para determinar o número, a localização e o dimensionamento dos bancos capacitores ao longo das linhas de distribuição. Desta forma, pretende-se minimizar a injeção de reativos e reduzir as perdas ativas totais de modo que todas as restrições de operação e de carga sejam atendidas. Os resultados são avaliados pelo programa GAMS (General Algebraic Modeling System), pelo MATLAB TM (Matrix Laboratory) e por um programa elaborado em Fortran, sendo possível analisar e descrever as contribuições alcançadas pelo presente trabalho, considerando que este é um tema de grande relevância para a operação e planejamento da expansão dos sistemas elétricos de potência. / This work aims to use nonlinear optimization methods to develop an efficient methodology for capacitor banks allocation to eliminate voltage violations in distribution networks. The application of capacitors in parallel to the electric power systems are commonly employed in order to have better control of power flow, voltage profile management, power factor correction and loss minimization. To achieve these benefits, the methodology of this work will be done through the resolution of a nonlinear programming problem associated with the linear approach of Voltage Variations versus Reactive Power Variation, calculating the number, location and optimal design of capacitor banks along distribution lines. Thus, it looks forward to minimize reactive power injection and reduce losses subject to meeting the operating and the loading constraints. The results are evaluated by the program GAMS TM (General Algebraic Modeling System), by Matlab TM (Matrix Laboratory) and by a program written in FORTRAN TM, being able to analyze and describe the contributions achieved by this work, considering it is a topic of great relevance to the operation and expansion planning of electric power systems.

Esta dissertação tem por objetivo o desenvolvimento, e implantação em computador, de uma metodologia para tratamento do problema de restabelecimento de energia em sistemas de distribuição de grande porte (com milhares de linhas, barras de carga e chaves seccionadoras), que permita a obtenção de Planos de Restabelecimento de Energia (PREs) adequados considerando a existência de reguladores de tensão, bancos de capacitores e de diferentes tipos de chaves seccionadoras. A metodologia proposta deverá considerar as características de operação de diferentes tipos de chaves seccionadoras (existência de telecomando, possibilidade de abertura com carga e/ou em curto circuito, etc.) para obtenção de PREs. Vale lembrar que usualmente as metodologias desenvolvidas para obtenção de PREs consideram a existência apenas de chaves automáticas e não automáticas, não considerando outras características de funcionamento das chaves seccionadoras. Tendo em vista que o problema a ser tratado é combinatório, com múltiplos objetivos e restrições, a metodologia proposta será baseada em Algoritmos Evolutivos, em técnicas de otimização multi-objetivo e na estrutura de dados denominada Representação Nó-Profundidade (RNP). A RNP será utilizada para representar computacionalmente, de forma eficiente, a topologia elétrica dos sistemas de distribuição. Para validar a metodologia proposta serão realizadas simulações computacionais com sistemas de distribuição reais de grande porte. / This dissertation aims to develop a methodology to provide adequate Energy Restoration Plans (ERPs) in contingency situations to large-scale distribution systems (with thousands of lines, load buses and sectionalizing switches), considering the existence of voltage regulators, capacitors banks and different types of sectionalizing switches. The proposed methodology considers the operational characteristics of different types of sectionalizing switches (existence of remote control, possibility of open-load and/or short-circuit, etc.) for the purpose of obtaining ERPs. Usually the developed methodologies consider only the existence of remotely controlled and manually controlled switches, excluding other operational characteristics of the sectionalizing switches. As the service restoration problem is combinatory with multiple objectives and constraints, the proposed methodology is based on Evolutionary Algorithms, multiobjective optimization techniques and on the data structure named Node-Depth Encoding. The Node-Depth Encoding is used to computationally represent, in an efficient way, the topology of the distribution systems. The proposed methodology is validated through computational simulations performed in real large-scale distribution systems.