While 3D stacked multi-processor technology offers the potential for significant computing advantages, these architectures also face the significant challenge of small, localized hotspots with very large heat fluxes due to the placement of asymmetric cores, heterogeneous devices and performance driven layouts. In this thesis, a new thermal management solution is introduced that seeks to maximize the performance of microprocessors with dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profiles resulting from the dynamic power maps, solid-liquid phase change materials (PCMs) with an embedded heat spreader network are strategically positioned near localized hotspots, resulting in a large increase in the local thermal capacitance in these problematic areas. Theoretical analysis shows that the increase in local thermal capacitance results in an almost twenty-fold increase in the time that a thermally constrained core can operate before a power gating or core migration event is required. Coupled to the PCMs are solid state coolers (SSCs) that serve as a means for fast regeneration of the PCMs during the cool down periods associated with throttling events. Using this combined PCM/SSC approach allows for devices that operate with the desirable combination of low throttling frequency and large overall core duty cycles, thus maximizing computational throughput. The impact of the thermophysical properties of the PCM on the device operating characteristics has been investigated from first principles in order to better inform the PCM selection or design process. Complementary to the theoretical characterization of the proposed thermal solution, a prototype device called a "Composite Thermal Capacitor (CTC)" that monolithically integrates micro heaters, PCMs and a spreader matrix into a Si test chip was fabricated and tested to validate the efficacy of the concept. A prototype CTC was shown to increase allowable device operating times by over 7X and address heat fluxes of up to ~395 W/cm2. Various methods for regenerating the CTC have been investigated, including air, liquid, and solid state cooling, and operational duty cycles of over 60% have been demonstrated.

The primary objective of this research was to investigate and develop an electrostatic energy-harvesting voltage-constrained CMOS/BiCMOS integrated circuit (IC) that harnesses ambient kinetic energy from vibrations with a vibration-sensitive variable capacitor and channels the extracted energy to charge an energy-storage device (e.g., battery). The proposed harvester charges and holds the voltage across the vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). To that end, the research developed an energy-harvesting system that synchronizes to variable capacitor's state as it cycles between maximum and minimum capacitance by controlling each functional phase of the harvester and adjusting to different voltages of the on-board battery. One of the major challenges of the system was performing all of these duties without dissipating the energy harnessed and gained from the environment. Consequently, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during each vibration cycle.

Piezoelectric materials are widely used for sensors, actuators and trasducers. Traditionally, piezoelectric applications are dominated by multicomponent oxide ferroelectrics such as lead zirconate titanate (PZT), which have the advantage of high piezoelectric coefficients. Recently, one-dimensional piezoelectric nanostructures such as nanowires of zinc oxide (ZnO) and gallium nitride (GaN) has gained a lot of attention due to their combined piezoelectric and semiconducting properties. The focus of this thesis is to study the processing and electric properties of such piezoelectric thin films and nanostructures for various applications. There is an increasing interest to form thin films of multicomponent ferroelectric oxides such as PZT on three-dimensional structures for charge storage and MEMS applications. Traditional vapor phase deposition techniques of PZT offer poor conformality over threedimensional surfaces due to their reactant transport mechanisms. As an alternative, solgel synthesis may provide new process possibilities to overcome this hurdle but the film quality is usually inferior, and the yield data was usually reported for small device areas. The first part of this study is dedicated to the characterization of the electric properties and yield of PZT thin film derived from the sol-gel process. PZT thin films with good electric property and high yield over a large area have been fabricated. La doping was found to double the breakdown field due to donor doping effect. LaNiO3 thin films that can be coated on a three-dimensional surface have been synthesized by an all-nitrate based sol-gel route, and the feasibility to form a conformal coating over a three-dimensional surface by solution coating techniques has been demonstrated. ZnO and GaN micro/nanowires are promising piezoelectric materials for energy harvesting and piezotronic device applications. The second part of this study is focused on the growth of ZnO and GaN micro/nanowires by physical vapor deposition techniques. The morphology and chemical compositions are revealed by electron microscopy. Utilizing the as-grown ZnO nanowires, single nanowire based photocell has been fabricated, and its performance was studied in terms of its response time, repeatability, excitation position and polarization dependence upon He-Cd UV-laser illumination. The excitation position dependence was attributed to the competition of two opposite photo- and thermoelectric currents originated from the two junctions. The excitation polarization dependence was attributed to the difference in optical properties due to crystallographic anisotropy. Employing the as-grown GaN nanowires, single nanowire based strain sensor is demonstrated, and its behavior is discussed in terms of the effect of strain-induced piezopotential on the Schottky barrier height.

Since metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations. / text

Hierarchical Kroll-carbons (KCs) with combined micro- and mesopore systems are prepared from silica and alumina templates by a reductive carbochlorination reaction of fumed silica and alumina nanoparticles inside a dense carbon matrix. The resulting KCs offer specific surface areas close to 2000 m2 g−1 and total pore volumes exceeding 3 cm3 g−1, resulting from their hierarchical pore structure. High micropore volumes of 0.39 cm3 g−1 are achieved in alumina-based KCs due to the enhanced carbon etching reaction being mainly responsible for the evolution of porosity. Mesopore sizes are uniform and precisely controllable over a wide range by the template particle dimensions. The possibility of directly recycling the process exhaust gases for the template synthesis and the use of renewable carbohydrates as the carbon source lead to a scalable and efficient alternative to classical hard- and soft templating approaches for the production of mesoporous and hierarchical carbon materials. Silica- and alumina-based Kroll-carbons are versatile electrode materials in electrochemical double-layer capacitors (EDLCs). Specific capacitances of up to 135 F g−1 in an aqueous electrolyte (1 M sulfuric acid) and 174 F g−1 in ionic liquid (1-ethyl-3-methylimidazolium tetrafluoroborate) are achieved when measured in a symmetric cell configuration up to voltages of 0.6 and 2.5 V, respectively. 90% of the capacitance can be utilized at high current densities (20 A g−1) and room temperature rendering Kroll-carbons as attractive materials for EDLC electrodes resulting in high capacities and high rate performance due to the combined presence of micro- and mesopores.

With the digital systems moving towards higher frequencies, lower operating voltages and higher power, supplying the required current at the right voltage and at the right time to facilitate timely switching of the CMOS circuits becomes increasingly challenging. The board level power supply cannot meet these requirements directly due to the high inductance of the package interconnections. To overcome this problem, several thin film decoupling capacitors have to be placed on the IC or close to the IC in the package. Two approaches were pursued for high-k thin film decoupling capacitors. 1) Low cost sol-gel based thin film capacitors on organic board compatible Cu-foils 2) RF-sputtered thin film capacitors on silicon substrate for silicon compatible processes While sol-gel provides cost effective technology, sputtered ferroelectric devices are more compatible from manufacturing stand point with the existing technology. Nano-crystalline barium titanate and barium strontium titanate film capacitor devices were fabricated and characterized for organic and silicon substrates respectively. Sol-gel barium titanate films were fabricated first on a bare Cu-foil and then transferred to organic board through a standard lamination process. With process optimization and film doping, a capacitance density of 3 µF/cm2 was demonstrated with breakdown voltage greater than 12V. Leakage current characteristics, breakdown voltages, and electrical reliability of the devices were significantly improved through doping of the barium titanate films and modified film chemistry. Films and interfaces were characterized with high resolution electron microscopy, SEM, XRD, and DC leakage measurements. RF sputtering was selected for ferroelectric thin film integration on silicon substrate. Barium strontium titanate (BST) films were deposited on various electrodes sputtered on silicon substrates. The main focus was to improve interface stabilities for high-k thin films on Si to yield large-area defect-free devices. Effect of bottom electrode selection and barrier layers on device yield and performance were investigated carefully. High yield and high device performance was observed for certain electrode and barrier layer combination. A capacitance density up to 1 µF/cm2 was demonstrated with a breakdown voltage above 15 V on large area, 7 mm2, devices. These two techniques can potentially meet mid-high frequency future decoupling requirements.

Power distribution network (PDN) design was a non-existent entity during the early days of microprocessors due to the low frequency of operation. Once the switching frequencies of the microprocessors started moving towards and beyond MHz regions, the parasitic inductance of the PCB tracks and planes started playing an important role in determining the maximum voltage on a PDN. Voltage regulator module (VRM) sup-plies only the DC power for microprocessors. When the MOSFETs inside a processor switches, it consumes currents during transition time. If this current is not provided, the voltage on the supply rails can go below the specifications of the processor. For lower MHz processors few ceramic-capacitors known as ‘decoupling capacitors’ were connected between power and ground to provide this transient current demand. When the processor frequency increased beyond MHz, the number of capacitors also increased from few numbers to hundreds of them. Nowadays, the PDN is said to be comprising all components from VRM till the die location. It includes VRM, bulk capacitors, PCB power planes, capacitor mounting pads and vias, mount for the electronic package, package capacitors, die mount and internal die capacitance. So, the PDN has evolved into a very complex system over the years. A PDN should provide three distinct roles; 1) provide transient current required by the processor 2) act as a stable reference voltage for processor 3) filter out the noise currents injected by the processor. The first two are required for the correct operation of the processor. Third one is a requirement from analog or other sensitive circuits connected to the same PDN. If the noise exits the printed circuit board (PCB), it can result in conducted and radiated EMI, which can in turn result in failure of a product in EMC testing. Every PDN design starts with the calculation of a target impedance which is given as the ratio of maximum allowed ripple voltage to the maximum transient current required by the processor. The transient current is usually taken as half the average input current. The definition of target impedance assumes that the PDN is flat over the entire frequency of operation, which is true only for a resistive network. This is seldom true for a practical PDN, since it contains inductances and capacitances. Because of this, a practical PDN has an uneven impedance versus frequency envelope. Whenever two capacitors with different self resonant frequencies are connected in parallel, their equivalent impedance produces a pole between the self resonant frequencies known as antiresonance peaks. Because of this, a PDN will have phase angles associated with them. Also, these antiresonance peaks are energy reservoirs which will be excited during the normal operation of a processor by the varying currents. The transient current of a microprocessor is modeled as a gamma function, but for practical cases it can be approximated as triangular waveforms during the transition time which is normally 10% of the time period. Depending upon the micro-operations running inside the processor, the peak value of this waveform varies. This is filtered by the on-chip capacitors, package inductance and package capacitors. Due to power gating, clock gating, IO operations, matrix multiplications and magnetic memory readings the waveforms at the board will be like pulse type, and their widths are determined by these operations. In literatures, these two types of waveforms are used for PDN analysis, depending upon at which point the study is conducted. Chapter 1 introduces the need for PDN design and the main roles of a PDN. The issue of antiresonance is introduced from a PDN perspective. Different types of capacitors used on a PDN are discussed with their strengths and limitations. The general nature of the switching noise injected by a microprocessor is also discussed. This chapter discusses the thesis contributions, and the existing work related to the field. Chapter 2 introduces a new method to calculate the target impedance (Zt ) by including the phase angles of a PDN which is based on a maximum voltage calculation. This new Zt equals to conventional Zt for symmetrical triangular switching current waveforms. The value of new Zt is less than the conventional Zt for trapezoidal excitation patterns. By adding the resonance effects into this, a maximum voltage value is obtained in this chapter. The new method includes the maximum voltage produced on a PDN when multiple antiresonance peaks are present. Example simulations are provided for triangular and pulse type excitations. A measured input current wave-form for PIC16F677 microcontroller driving eight IO ports is provided to prove the assumption of pulse type waveforms. For triangular excitation waveform, the maximum voltage predicted based on the expression was ¡0.6153 V, and the simulated maximum voltage was found to be at ¡0.5412 V which is less than the predicted value. But the predicted value based on Zt method was 1.9845 V. This shows that the conventional as well as the new target impedance method leads to over estimating the maximum voltage in certain cases. This is because most of the harmonics are falling on the minimum impedance values on a PDN. If the PDN envelope is changed by temperature and component tolerances, the maximum voltage can vary. So the best option is to design with the target impedance method. When pulse current excitation was studied for a particular PDN, the maximum voltage produced was -139.39 mV. The target impedance method produced a value of -100.24 mV. The maximum voltage predicted by the equation was -237 mV. So this shows that some times the conventional target impedance method leads to under estimating the PDN voltage. From the studies, it is shown that the time domain analysis is as important as frequency domain analysis. Another important observation is that the antiresonance peaks on a PDN should be damped both in number and peak value. Chapter 3 studies the antiresonance peak suppression methods for general cases. As discussed earlier, the antiresonance peaks are produced when two capacitors with different self resonant frequencies are connected in parallel. This chapter studies the effect of magnetic coupling between the mounting loops of two capacitors in parallel. The mounting loop area contribute to the parasitic inductance of a capacitor, and it is the major contributing factor to it. Other contributing factors are equivalent series inductance (ESL) and plane spreading inductance. The ESL depends on the size and on how the internal plates of the capacitors are formed. The spreading inductance is the inductance contributed by the parts of the planes connecting the capacitor connector vias to the die connections or to other capacitor vias. If the power and ground planes are closer, the spreading inductance is lower. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The inductance contributed by the mounted area of the capacitor is known as mounting inductance. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The dependencies of various circuit parameters on antiresonance peak are studied using circuit theory. A general condition for damping the antiresonance is formulated. The antiresonance peak reduces with Q factor. The conventional critical condition for antiresonance peak damping needs modification when magnetic coupling is present between the mounting loops of two parallel unequal value capacitors. By varying the connection geometry it is possible to obtain negative and positive coupling coefficients. The connection geometries to obtain these two are shown. An example is shown for positive and negative coupling coefficient cases with simulation and experimental results. For the example discussed, RC Æ 32 - for k Æ Å0.6 and RC Æ 64 - for k Æ ¡0.6, where RC is the critical damping value and k is the magnetic coupling coefficient between the two mounting loops. The reason for this is that, the antiresonance peak impedance value is higher for negative coupling coefficient case than that for positive coupling coefficient case. Above the self resonant frequencies of both the capacitors, the equivalent impedance of the parallel capacitors become inductive. This case is studied with two equal value capacitors in parallel. It is shown that the equivalent inductance is lower for negative coupling coefficient case as compared to positive coupling coefficient case. An example is provided with simulation and experimental results. In the experimental results, parasitic inductance is observed to be 2.6 times lower for negative coupling coefficient case than that for positive coupling coefficient case. When equal value capacitors are connected in parallel, it is advantageous to use a negative coupling geometry due to this. Chapter 4 introduces a new method to damp the antiresonance peak using a magnet-ically coupled resistive loop. Reducing the Q factor is an option to suppress the peak. In this new method, the Q factor reduction is achieved by introducing losses by mag-netically coupling a resistive loop. The proposed circuit is analyzed with circuit-theory, and governing equations are obtained. The optimum value of resistance for achieving maximum damping is obtained through analysis. Simulation and experimental results are shown to validate the theory. From the experimental results approximately 247 times reduction in antiresonance peak is observed with the proposed method. Effectiveness of the new method is limited by the magnetic coupling coefficient between the two mounting loops of capacitors. The method can be further improved if the coupling coefficient can be increased at the antiresonance frequency. Chapter 5 focuses on the third objective of a PDN, that is to reduce the noise injected by the microprocessor. A new method is proposed to reduce the conducted noise from a microprocessor with switched super capacitors. The conventional switched capacitor filters are based on the concept that the flying capacitor switching at high frequency looks like a resistor at low frequency. So for using at audio frequencies the flying capacitors were switching at MHz frequencies. In this chapter the opposite of this scenario is studied; the flying capacitors are the energy storage elements of a switched capacitor converter and they switch at lower frequencies as compared to the noise frequencies. Two basic circuits (1:1 voltage conversion ratio) providing noise isolation were discussed. They have distinct steady state input current waveforms and are explained with PSPICE simulations. The inrush current through switches are capable of destroying them in a practical implementation. A practical solution was proposed using PMOS-PNP pair. The self introduced switching noise of the converter is lower when switching frequency is low and turn ON-OFF time is higher. If power metal oxide semiconductor field effect transistor (MOSFET)s are used, the turn ON and turn OFF are slow. The switching frequency can be lowered based on the voltage drop power loss. The governing equations were formulated and simulated. It is found that the switching frequency can be lowered by increasing the capacitance value without affecting the voltage drop and power loss. From the equations, it is found that the design parameters have a cyclic dependency. Noise can short through the parasitic capacitance of the switches. Two circuits were proposed to improve the noise isolation: 1) T switch 2) ¦ switch. Of these, the ¦ switch has the higher measured transfer impedance. Experimental results showed a noise reduction of (40-20) dB for the conducted frequency range of 150 kHz - 30 MHz with the proposed 1:1 switched capacitor converter. One possible improvement of this method is to combine the noise isolation with an existing switched capacitor converter (SCC) topology. The discussed example had a switching frequency of 700 Hz, and it is shown that this can isolate the switching noise in kHz and MHz regions. In a PDN there are antiresonance peaks in kHz regions. If the proposed circuit is kept close to a microprocessor, it can reduce the excitation currents of these low frequency antiresonance peaks. Chapter 6 concludes the thesis by stating the major contributions and applications of the concepts introduced in the thesis. This chapter also discusses the future scope of these concepts.

Orientador: José Roberto Sanches Mantovani / Resumo: O problema de alocação ótima de banco de capacitores em sistema de distribuição radiais consiste em definir as barras onde devem ser alocados os bancos de capacitores, além de determinar os tipos, potência nominal e em quais fases eles devem ser alocados, atendendo a restrições físicas e operacionais das redes elétricas, juntamente com os padrões da qualidade de fornecimento normatizados pelas agências reguladoras do setor. Também deve-se definir o esquema de controle, ou seja, quando os bancos capacitivos variáveis devem operar em diferentes níveis de carregamentos. A alocação de bancos de capacitores em sistemas de distribuição é um problema de programação não-linear inteiro misto, não convexo, de difícil solução através de técnicas clássicas de otimização, pela sua natureza combinatória, devido o aumento no número de variáveis inteiras envolvidas na solução de problemas de médio e grande porte. Neste trabalho, propõe-se para a sua solução a meta-heurística de Evolução Diferencial (ED), que deve fornecer a localização e dimensionamento dos bancos de capacitores fixos e chaveados ao longo dos alimentadores primários, em sistemas de distribuição radiais trifásicos e desbalanceados. A alocação deve atender aos critérios de mínimo custo de investimento e operação do sistema, dados pela soma do custo de aquisição, instalação e manutenção dos bancos de capacitores, mais o custo de perdas ativas no sistema além de melhorar o fator de potência. São apresentados neste trabalho, resu... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: The optimal allocation problem of capacitor bank in radial distribution systems is to define the bus where the capacitor banks must be allocated, furthermore determine the types, nominal power and which phase they must be allocated as they attended the physical and the operational constraints of power systems in conjunction with the supplier quality standards normalized by the sector regulatory agencies. Moreover, you must define the check schema, in the words, when the variable capacitor banks must operate at different load levels. The allocation of capacitor banks in distribution systems it's a not convex mixed integer nonlinear programming problem with a difficult solution through classical optimization techniques due to the increase of integer variables involved in the solution of large and medium-size problems. This works proposes for the solution, a metaheuristic based on Differential Evolution (DE) which provide the location and the sizing of fixed capacitor banks, switched over the primary feeders in unbalanced three-phase radial distribution systems, with the aim of minimizing the total investment and the system operation cost, given by sum of acquisition cost, installation and maintenance of capacitor banks, plus the cost of active losses in the system and to im-prove the power factor. Results for a 135-bus unbalanced three-phase system are presented. / Mestre

Made available in DSpace on 2014-06-11T19:22:33Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-11-17Bitstream added on 2014-06-13T18:49:33Z : No. of bitstreams: 1 mertensjunior_ea_me_ilha.pdf: 1934720 bytes, checksum: fe7d7a9f65b7d36be8112ffea7f317ae (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / O presente trabalho avalia a viabilidade técnica da aplicação de compensação reativa em circuitos secundários aéreos de baixa tensão, através da aplicação de capacitores e / ou filtros para aplicação em Baixa Tensão, buscando assim uma otimização dos reativos presentes nas redes secundárias. Considerando-se as constantes mudanças que vêm ocorrendo no cenário de distribuição de energia elétrica, devido ao grande avanço da eletrônica de potência e de cargas não lineares cada vez mais presentes no sistema elétrico, fazem-se necessários estudos para diagnosticar como e em que níveis tais mudanças podem estar afetando as características das redes de distribuição. Verifica-se que tais cargas, possuem um baixo fator de potência, e podem aumentar significativamente o nível de correntes harmônicas devido às técnicas de chaveamento utilizadas nestes dispositivos. Com isto, acentuam-se os problemas da propagação das distorções de forma de onda das correntes às tensões da rede, além de aumentar consideravelmente as perdas de energia elétrica ao longo de seus condutores e transformadores. Há necessidade de se conhecer as características dessas cargas de forma a permitir a correta modelagem das mesmas. O objetivo deste trabalho é identificar o perfil da rede secundária frente aos níveis de harmônicos e fator de potência, permitindo a adequada aplicação de filtros e capacitores para instalação no secundário dos transformadores de distribuição, visando a correção do fator de potência nos circuitos, redução do reativo circulante, das perdas elétricas e eventualmente dos níveis de distorção harmônica. Avaliando-se as interferências no carregamento dos transformadores de distribuição e melhoria do perfil da tensão de alimentação. Neste sentido, foi feita uma campanha de monitoramento em alguns circuitos selecionados... / This paper seeks to evaluate the technical feasibility of applying for compensation reactive side air circuits in low-voltage, by the application of capacitors and / or filters for use in the Low Voltage, thereby seeking an optimization of reactive present in the secondary networks. Analysis with a focus on secondary distribution network should consider a new factor, which is the proliferation of non-linear loads. Considering the constant changes that are occurring in the scenario of distribution of electric energy, due to the general advancement of power electronics and nonlinear loads increasingly present in the electrical system, are made necessary studies to diagnose how and to what levels such changes may be affecting the characteristics of distribution networks. It appears that such loads, have a low power factor, and can significantly increase the level of harmonic currents because of the techniques used in these switching devices. With this, stressing the problems of the spread of distortions of waveform of the current tensions to the network, in addition to considerably increase the loss of power over their drivers and processors. Thus, the objective of this study is to identify the profile of the network front secondary levels of harmonics and power factor, allowing the proper implementation of filters and capacitors for installation of transformers in the secondary distribution, aiming to correct the power factor in circuits, Reducing the reactive stock, loss of electrical and possibly the levels of harmonic distortion. Judging is interference in the shipment of processors for distribution and improving the profile of the supply voltage. In this sense, there was a campaign tracking in some selected circuits, computer simulations were also conducted, equipment developed and deployed pilot projects.

Submitted by Luíz Gustavo Simão Albano (luizgustavoalbano@gmail.com) on 2018-04-20T20:51:26Z No. of bitstreams: 1 TESE_ALBANO_LGS-23-02-2018.pdf: 13982901 bytes, checksum: 09610d28485aca4fecdd9833a5f43b00 (MD5) / Approved for entry into archive by Maria Marlene Zaniboni null (zaniboni@bauru.unesp.br) on 2018-04-23T19:56:14Z (GMT) No. of bitstreams: 1 albano_lgs_dr_bauru.pdf: 13982901 bytes, checksum: 09610d28485aca4fecdd9833a5f43b00 (MD5) / Made available in DSpace on 2018-04-23T19:56:14Z (GMT). No. of bitstreams: 1 albano_lgs_dr_bauru.pdf: 13982901 bytes, checksum: 09610d28485aca4fecdd9833a5f43b00 (MD5) Previous issue date: 2018-02-23 / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / Atualmente, a eletrônica baseada em materiais orgânicos vem ganhando visibilidade no cenário científico e tecnológico devido à alta flexibilidade mecânica e baixo custo desses materiais. A fabricação de dispositivos eletrônicos baseados em materiais orgânicos e técnicas de baixo custo é um desafio pertinente e atual. Os transistores merecem destaque por serem a base da tecnologia atual. Em especial, uma arquitetura vertical comumente conhecida como VOFET (Transistor Orgânico de Efeito de Campo em Arquitetura Vertical) vem sendo explorada nos últimos anos. Entretanto, um problema comum em VOFETs é o eletrodo intermediário, o qual deve ser permeável a campos elétricos e apresentar baixa resistência de folha utilizando técnicas com baixo custo de produção. Desta forma, na primeira parte deste trabalho é apresentado o desenvolvimento de um eletrodo intermediário baseado em nanofios de prata utilizando a técnica de baixo custo conhecida como Mayer rod-coating. Os eletrodos otimizados foram aplicados em dispositivos VOFETs, resultando em transistores com densidades de corrente de 2,5 mA/cm2 e razão on/off de 5x103, utilizando tensões de operação de até 2 V. Além dos semicondutores orgânicos comumente sintetizados, corantes naturais também vêm sendo explorados para aplicações em dispositivos eletrônicos. Dentre eles, a melanina desperta atenção por ser um pigmento natural encontrado em vários sistemas biológicos. No corpo humano a melanina é responsável por funções como pigmentação, fotoproteção e termoregulação. Suas características de transporte em função da umidade associada à sua alta biocompatibilidade, tem originado considerável interesse para aplicações em dispositivos eletrônicos. Apesar de suas vantagens, quando extraída in vivo a melanina apresenta considerável irregularidade estrutural e pouca solubilidade, sendo necessário o desenvolvimento de rotas sintéticas para a obtenção de filmes finos de qualidade. Assim, na segunda parte deste trabalho, foi explorada a obtenção de filmes finos de melanina para aplicações na eletrônica orgânica. Os resultados obtidos permitiram à aplicação desse material em transistores eletroquímicos. Além disso, um estudo considerando diferentes condições de umidade relativa e pHs permitiu mostrar que sua condutividade é governada pela reação de comproporcionamento. Na terceira parte deste trabalho, foi estudada a fabricação de filmes finos utilizando diferentes porcentagens de melanina em matrizes de álcool polivinílico, para simultâneas aplicações como filtros protetores de radiação ultravioleta e capacitores orgânicos transparentes. Os filmes finos fabricados apresentaram excelente desempenho contra os raios UVA, bloqueando 100 % dos raios incidentes, além de funcionar de forma simultânea como capacitores orgânicos transparentes utilizando nanofios de prata como eletrodos. A integração dos filtros com a eletrônica orgânica permite futuras aplicações desse sistema em janelas ópticas inteligentes. Na última parte deste trabalho, foi estudada a reticulação de cadeias poliméricas do álcool polivinílico através inserção da melanina com intuito de substituir o dicromato de amônio, tradicionalmente utilizado na de reticulação do polímero. Os resultados obtidos mostraram que os filmes finos com 0,5 % de melanina apresentaram uma redução na densidade de corrente de quase duas ordens de magnitude em comparação com os filmes finos de álcool polivinílico, comportamento similar quando a reticulação é realizada com dicromato de amônio. Os resultados obtidos neste trabalho mostram a possibilidade de fabricar dispositivos eletrônicos baseados em materiais orgânicos e técnicas de baixo custo. O uso da melanina mostra ser uma alternativa interessante, pois além de sua alta biocompatibilidade, este material pode desempenhar diferentes funções em dispositivos eletrônicos. / Currently, electronics based on organic materials has been acquiring visibility in the scientific and technological scenario due to the high mechanical flexibility and low-cost of these materials. The fabrication of electronic devices based on organic materials and low-cost techniques is a relevant and current challenge. Transistors deserve attention because they are the base of our current technology. In particular, a vertical architecture commonly known as VOFET (Vertical Organic Field Effect Transistor) has been explored in recent years. However, a common issue in VOFET structure is the intermediate electrode, which must be permeable to electric fields with low sheet resistance using low-cost production techniques. Thus, in the first part of this work, the development of an intermediate electrode based on silver nanowires using the low-cost technique known as Mayer rod-coating is presented. The optimized electrodes were applied in VOFETs, resulting in devices with current densities of 2.5 mA/cm2 and on/off ratio of 5x103, using operating voltages up to 2 V. Apart from to the organic semiconductors commonly synthesized, natural dyes are also being explored in organic electronics. Among them, melanin deserves attention because it is a natural pigment found in several biological systems. In the human body melanin is responsible for functions such as pigmentation, photoprotection and thermoregulation. The humidity-dependent electrical response associated with the high biocompatibility has provided considerable interest for applications in electronic devices. However, melanin when extracted in vivo presents considerable structural irregularity and low solubility. In this way, the development of synthetic routes to obtain thin films with quality has been considered. Thus, in the second part of this work, the fabrication of melanin thin films was explored for applications in organic electronics. The results obtained allowed the application of melanin thin films in electrochemical transistors. In addition, a study considering different conditions of relative humidity allowed observe that its electronic conductivity is governed by the comproportionation reaction. In the third part of this work, the fabrication of poly(vinyl alcohol) thin films with different percentages of melanin were studied for simultaneously applications as ultraviolet filters and transparent organic capacitors. The thin films fabricated presented good performance against UVA radiation, blocking 100 % of the incident rays and working as transparent organic capacitors using silver nanowires as electrode. The integration of the filters with organic electronics allows future applications of this system in smart windows. In the last part of this work, the crosslinking of poly(vinyl alcohol) polymer chains through melanin incorporation was studied in order to replace ammonium dichromate. Ammonium dichromate is traditionally used in the poly(vinyl alcohol) crosslinking process. The results showed that the thin films with 0.5 % of melanin presented a reduction factor of almost 100 in current density when compared to the neat thin films, similar behavior when the crosslinking is performed with inorganic materials. The results obtained in this work showed the possibility to fabricate electronic devices based on organic materials and low-cost techniques. In addition, the use of melanin is an interesting alternative due to the fact that this material has high biocompatibility and can perform different functions in electronic devices. / FAPESP: 13/09963-6 / FAPESP: 13/07296-2 / FAPESP: 14/25332-9