Wireless micro-sensors can enjoy popularity in biomedical drug-delivery treatments and tire-pressure monitoring systems because they offer in-situ, real-time, non-intrusive processing capabilities. However, miniaturized platforms severely limit the energy of onboard batteries and shorten the lifespan of electronic systems. Ambient energy is an attractive alternative because the energy from light, heat, radio-frequency (RF) radiation, and motion can potentially be used to continuously replenish an exhaustible reservoir. Of these sources, solar light produces the highest power density, except when supplied from indoor lighting, under which conditions the available power decreases drastically. Harnessing thermal energy is viable, but micro-scale dimensions severely limit temperature gradients, the fundamental mechanism from which thermo piles draw power. Mobile electronic devices today radiate plenty of RF energy, but still, the available power rapidly drops with distance. Harvesting kinetic energy may not compete with solar power, but in contrast to indoor lighting, thermal, and RF sources, moderate and consistent vibration power across a vast range of applications is typical. Although operating conditions ultimately determine which kinetic energy-harvesting method is optimal, piezoelectric transducers are relatively mature and produce comparatively more power than their counterparts such as electrostatic and electromagnetic kinetic energy transducers. The presented research objective is to develop, design, simulate, fabricate, prototype, test, and evaluate CMOS ICs that harvest ambient kinetic energy in periodic and non-periodic vibrations using a small piezoelectric transducer to continually replenish an energy-storage device like a capacitor or a rechargeable battery. Although vibrations in surrounding environment produce abundant energy over time, tiny transducers can harness only limited power from the energy sources, especially when mechanical stimulation is weak. To overcome this challenge, the presented piezoelectric harvesters eliminate the need for a rectifier which necessarily imposes threshold limits and additional losses in the system. More fundamentally, the presented harvesting circuits condition the transducer to convert more electrical energy for a given mechanical input by increasing the electromechanical damping force of the piezoelectric transducer. The overall aim is to acquire more power by widening the input range and improving the efficiency of the IC as well as the transducer. The presented technique in essence augments the energy density of micro-scale electronic systems by scavenging the ambient kinetic energy and extends their operational lifetime. This dissertation reports the findings acquired throughout the investigation. The first chapter introduces the applications and challenges of micro-scale energy harvesting and also reviews the fundamental mechanisms and recent developments of various energy-converting transducers that can harness ambient energy in light, heat, RF radiation, and vibrations. Chapter 2 examines various existing piezoelectric harvesting circuits, which mostly adopt bridge rectifiers as their core. Chapter 3 then introduces a bridge-free piezoelectric harvester circuit that employs a switched-inductor power stage to eliminate the need for a bridge rectifier and its drawbacks. More importantly, the harvester strengthens the electrical damping force of the piezoelectric device and increases the output power of the harvester. The chapter also presents the details of the integrated-circuit (IC) implementation and the experimental results of the prototyped harvester to corroborate and clarify the bridge-free harvester operation. One of the major discoveries from the first harvester prototype is the fact that the harvester circuit can condition the piezoelectric transducer to strengthen its electrical damping force and increase the output power of the harvester. As such, Chapter 4 discusses various energy-investment strategies that increase the electrical damping force of the transducer. The chapter presents, evaluates, and compares several switched-inductor harvester circuits against each other. Based on the investigation in Chapter 4, an energy-investing piezoelectric harvester was designed and experimentally evaluated to confirm the effectiveness of the investing scheme. Chapter 5 explains the details of the IC design and the measurement results of the prototyped energy-investing piezoelectric harvester. Finally, Chapter 6 concludes the dissertation by revisiting the challenges of miniaturized piezoelectric energy harvesters and by summarizing the fundamental contributions of the research. With the same importance as with the achievements of the investigation, the last chapter lists the technological limits that bound the performance of the proposed harvesters and briefly presents perspectives from the other side of the research boundary for future investigations of micro-scale piezoelectric energy harvesting.

In the present study, the dissolution mechanism and rate of lime, limestone and dolomite in converter slag was studied. Lime dissolution in stagnant slag was studied first and dissolution of lime, limestone and dolomite under forced convection were carried out by new experimental setup. Dissolution of different CaO samples into stagnant converter slags was carried out in a closed tube furnace at 1873K. In the case of CaO-‘FeO’-SiO2 slag, the dissolution of CaO rod in the stagnant slag was retarded after the initial period (2 minutes). A dense layer of 2CaO∙SiO2 was found to be responsible for the total stop of the dissolution. It could be concluded that constant removal of the 2CaO∙SiO2 layer would be of essence to obtain high dissolution rate of lime. In this connection, it was found necessary to study the dissolution of lime in moving slag. In order to obtain reliable information of lime dissolution under forced convection, the commonly used rotating rod method was examined. Both CFD calculation and cold model experiments showed evidently that the mass transfer due to radial velocity introduced by forced convection was zero if the rod was centrally placed in a cylindrical container. A new experimental design was therefore developed. A cube was placed in the crucible and stirred by Mo rod along with slag. The whole system could be quenched in order to maintain the state of the system at high temperature. A linear relationship between normalized length and time was obtained for lime dissolution. Different lime samples showed big difference in dissolution rate. It was found that the main mechanism of CaO dissolution in slag was due to the removal of 2CaO∙SiO2 layer. Decomposition and dissolution of limestone and dolomite in slag at 1873 K were studied. The decomposition was carried out both in argon and in slag under argon atmosphere. The decomposition process was simulated using Comsol. The results showed evidently that the decomposition of limestone and dolomite was controlled mostly by heat transfer. It was also found that the decomposition of limestone product: CaO had very dense structure, no matter the sample was decomposed in slag or in argon. The slow decomposition and the dense CaO layer would greatly hinder the dissolution of lime in the slag. The present results clearly indicate that addition of limestone instead of lime would not be beneficial in converter process. Discontinuous 2CaO∙SiO2 layer along with MgO∙Fe2O3 particles was found on the surface of the dolomite sample. Some 2CaO∙SiO2 islands were found in the vicinity of the sample in the slag, which revealed therefore that the dissolution was dominated by the peeling-off of the layer of 2CaO∙SiO2-MgO∙Fe2O3 mixture. 2CaO∙SiO2, (Mg, Fe)Oss along with super cooled liquid phases were found inside dolomite sample close to the surface. 2CaO∙SiO2 phase was replaced gradually by 3CaO∙SiO2 towards the centre of the decomposed sample. / <p>QC 20120829</p>

In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, class AB opamps are used. The design was fabricated in 0.18um CMOS and occupies an area of 0.35mm2. Operating at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83uW. In incremental mode, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 89dB peak SNDR while operating from 1.67S/s to 1.67kS/s.

In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, class AB opamps are used. The design was fabricated in 0.18um CMOS and occupies an area of 0.35mm2. Operating at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83uW. In incremental mode, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 89dB peak SNDR while operating from 1.67S/s to 1.67kS/s.

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

Since 2002, the department of electricity at Uppsala university has pushed the Lysekil project. The project has a number of wave energy converters installed in the sea southwest of Lysekil. The purpose of this work is to design, build and test a DC-DC converter, which will later be used as a necessary part of the grid connection of a wave energy converter. Since a wave energy converter does not generate electricity at a constant frequency, it is not possible to use a gearbox. Instead, power is rectified and, if there are several wave power energy converters, are put together with the others before it is inverted and transformed to the correct voltage level, and finally connected to the grid [1]. The designed DC-DC converter is a converter of the type "inverting buck-boost", i.e. a converter that can both lower and raise the voltage, and inverts the polarity of the output. Although the voltage in normal circumstances will only be increased, the simulations showed that the efficiency and cost of components did not differ much between a "boost" and "buck-boost" converter, thus considered flexibility to be able to lower the voltage if needed. The project also includes a small part to the construction of a bridge rectifier, but as the most difficult moment in the project is the DC-DC converter, the greatest focus will be there.

This research suggests a novel voltage control scheme that can compensate for voltage sag and swell conditions in three-phase power systems. Faults occurring in power distribution systems or facilities in plants cause the voltage sag or swell. For sensitive loads, even voltage sags of short duration can cause serious problems in the entire system. In order to mitigate power interruptions, this research proposes a scheme called Voltage Sag Supporter utilizing a PWM (Pulse Width Modulation)-Switched Autotransformer. The proposed scheme is able to quickly recognize the voltage sag or swell condition, and it can correct the voltage by either boosting the input voltage during voltage sag events or reducing the input voltage during voltage swell events. Among existing methods, the scheme based on the inverter system such as dynamic voltage restorers (DVR) require an inverter, a rectifier, and a step-up down transformer, which makes the system expensive. AC converters can be used for the purpose of the research. However, they consist of two solid-state switches per one phase and include energy storage devices such as reactors and capacitors. The switching device for the high voltage application is relatively expensive so that this research suggests a scheme utilizing only one switch for the output voltage control, which makes the system more stable and cost effective. The proposed scheme can be applied at any voltage and provides cost and size advantages over existing methods due to the reduced number of switching components and no need of energy storage devices. Simulations and experiments have been carried out to verify the validity of the proposed scheme, and prototype experiments are being done to confirm the control scheme.

In present dissertation, field-driven quantum well (QW) device is proposed to obtain high-speed and high-efficiency all-optical wavelength converter (AOWC). A new type QW material, InGaAsP/InGaAlAs, is employed to improve not only quantum confined Stark effect, but also carrier life time during high electric field excitation. The bandwidth as well as efficiency can be enhanced. Thus, the slow gain recovery mechanism (~100ps) from conventional semiconductor optical amplifier (SOA)-based AOWC can be overcome. The dispersion- and efficient- limited fiber-based AOWC (~10ps) can also be avoided. -3dB frequency bandwidth exceeding 40GHz for both electrical-to-optical and photocurrent response has been observed from InGaAsP/InGaAlAs waveguide of AOWC, leading to above 40GHz bandwidth in optical-to-optical response. A 40 Gb/s measurement setup is finally used for testing eye-diagram and bit-error-ratio in order to verify the data transmission of AOWC. Low power penalty with 0.5 dB comparing with back-to-back system performance is measured, suggesting InGaAsP /InGaAlAs waveguide is applicable to all-optical processing. By exciting short optical pump pulse in such waveguide, as short as 6.4ps probe pulse is observed, breaking through 10ps order in conventional type of QW and thus indicating the plausibility of performing 100Gb/s all optical processing.

Analog-to-digital (A/D) conversion is a process that bridges the real analog world to digital signal processing. It takes a continuous-time, continuous amplitude signal as its input and outputs a discrete-time, discrete-amplitude signal. The resolution and sampling rate of an A/D converter vary depending on the application. Recently, there has been a growing demand for broadband (>1 MHz), high-resolution (>14bits) A/D converters. Applications that demand such converters include asymmetric digital subscriber line (ADSL) modems, cellular systems, high accuracy instrumentation, and medical imaging systems. This thesis suggests some design techniques for such high resolution and high sampling rate A/D converters. As the A/D converter performance keeps on increasing it becomes increasingly difficult for the input driver to settle to required accuracy within the sampling time. This is because of the use of larger sampling capacitor (increased resolution) and a decrease in sampling time (higher speed). So there is an increasing trend to have a driver integrated onchip along with A/D converter. The first contribution of this thesis is to present a new precharge scheme which enables integrating the input buffer with A/D converter in standard CMOS process. The buffer also uses a novel multi-path common mode feedback scheme to stabilize the common mode loop at high speeds. Another major problem in achieving very high Signal to Noise and Distortion Ratio (SNDR) is the capacitor mismatch in Digital to Analog Converters (DAC) inherent in the A/D converters. The mismatch between the capacitor causes harmonic distortion, which may not be acceptable. The analysis of Dynamic Element Matching (DEM) technique as applicable to broadband data-converters is presented and a novel second order notch-DEM is introduced. In this thesis we present a method to calibrate the DAC. We also show that a combination of digital error correction and dynamic element matching is optimal in terms of test time or calibration time. Even if we are using dynamic element matching techniques, it is still critical to get the best matching of unit elements possible in a given technology. The matching obtained may be limited either by random variations in the unit capacitor or by gradient effects. In this thesis we present layout techniques for capacitor arrays, and the matching results obtained in measurement from a test-chip are presented. Thus we present various design techniques for high speed and low noise A/D converters in this thesis. The techniques described are quite general and can be applied to most of the types of A/D converters.

Reactive power, denoted as volt-ampere reactive (VARs), is fundamental to ac power systems and is due to the complex impedance of the loads and transmission lines. It has several undesirable consequences which include increased transmission loss, reduction of power transfer capability, and the potential for the onset of system-wide voltage instability, if not properly compensated and controlled. Reactive power compensation is a technique used to manage and control reactive power in the ac network by supplying or consuming VARs from points near the loads or along the transmission lines. Load compensation is aimed at applying power factor correction techniques directly at the loads by locally supplying VARs. Typical loads such as motors and other inductive devices operate with lagging power factor and consume VARs; compensation techniques have traditionally employed capacitor banks to supply the required VARs. However, capacitors are known to have reliability problems with both catastrophic failure modes and wear-out mechanisms. Thus, they require constant monitoring and periodic replacement, which greatly increases the cost of traditional load compensation techniques. This thesis proposes a reactive power load compensator that uses inductors (chokes) instead of capacitors to supply reactive power to support the load. Chokes are regarded as robust and rugged elements; but, they operate with lagging power factor and thus consume VARs instead of generating VARs like capacitors. A matrix converter interfaces the chokes to the ac network. The matrix converter is controlled using the Venturini modulation method which can enable the converter to exhibit a current phase reversal property. So, although the inductors draw lagging currents from the output of the converter, the converter actually draws leading currents from the ac network. Thus, with the proposed compensation technique, lagging power factor loads can be compensated without using capacitor banks. The detailed operation of the matrix converter and the Venturini modulation method are examined in the thesis. The application of the converter to the proposed load compensation technique is analyzed. Simulations of the system in the MATLAB and PSIM environments are presented that support the analysis. A digital implementation of control signals for the converter is developed which demonstrates the practical feasibility of the proposed technique. The simulation and hardware results have shown the proposed compensator to be a promising and effective solution to the reliability issues of capacitor-based load-side VAR compensation techniques.