The Worldwide Interoperability for Microwave Access, or WiMax, is a wireless communication technique based on IEEE 802.16 standards. Its advantage of sending high data rates over long distances, while using a single base station to cover a large area, has made this technique a flexible and reliable solution for public wireless networks. WiMax has two main types of networks: Fixed and Mobile. The most popular transceiver used in WiMax applications is the “Direct-Conversion Architecture” due to its high level of integration and less component requirements, which leads to reduced power dissipation. In Direct Conversion Architecture, the mixer is a key block in the transceiver chain. Depending on design specifications and constraints, different types of mixers may be considered. However, the most appropriate down converter mixer for WiMax applications is the Gilbert-cell mixer. This thesis will then explore the design of a down converter Gilbert-Cell Mixer within the realm of Fixed WiMax technology. This design was achieved in the commercial circuit simulator Advanced Design System (ADS) using the 0.15mm InGaAs pHEMT technology process provided by Win Semiconductor Crop.

The thesis describes an optimal selective harmonic elimination strategy suitable for singlephase AC-DC converter-fed traction drives. The objective is to eliminate low-order supply current harmonics, including those injected into the supply due to load-side current ripple. Other advantages that the switching strategy has to offer over phase-control include improved supply power factor, reduced VA consumption for a given demand speed and load, reduced torque and speed ripple and smaller armature circuit smoothing inductance. The effect of field current boost on the dynamic response of the drive is also described. It is shown that field boost helps to reduce the speed rise-time by increasing the electromagnetic torque available during acceleration periods. Closed-loop control of a 4-quadrant DC drive is described and a comparison made between the performance of PID-control and pseudo-derivative feedback control. It is shown that pseudo-derivative feedback control has several advantages to offer, amongst which are ease of tuning of the controller gains and a superior performance following load torque disturbances. A laboratory size drive system was designed and built, and used to validate simulation predictions for both the switching strategy and pseudo-derivative feedback control. A microcontroller based hardware implementation of both the switching strategy and a digital pseudo-derivative feedback controller was adopted, with the switching strategy being implemented using an off-line approach of precalculating the switching angles and storing these in look-up tables. The armature voltage controller comprises a dual-converter employing IGBTs as switching devices. The use of IGBTs allows higher switching frequencies at significant power levels than would be possible if GTOs were used. It also simplifies the gate drive circuit design and minimises the need to use snubber circuits.

The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the subject modules are often designed to comply with different interface protocols. For such modules to communicate correctly there is a need for some glue logic, also called a protocol converter that mediates between them. Though much research has been dedicated to the protocol converter synthesis problem of SoC communication, converter synthesis is still performed manually, consuming development and verification time and risking human error. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the Hardware Description Language (HDL) implementation level or grossly simplify the structure of the protocols considered. This thesis develops and presents techniques for automatic synthesis of provably correct on-chip protocol converters. Basing the solution on a formal approach, a novel state-machine based formalism is presented for modelling bus-based protocols and formalizing the notions of protocol compatibility and correct protocol conversion. Algorithms for automatic compatibility checking and provably-correct converter synthesis are derived from the formalism, including a systematic exploration of the design space of the protocol converter, the first in the field, which enables generation of various alternative deterministic converters. The work presented is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modelling of protocol characteristics and automatic translation of the constructed converter to HDL.

The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the subject modules are often designed to comply with different interface protocols. For such modules to communicate correctly there is a need for some glue logic, also called a protocol converter that mediates between them. Though much research has been dedicated to the protocol converter synthesis problem of SoC communication, converter synthesis is still performed manually, consuming development and verification time and risking human error. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the Hardware Description Language (HDL) implementation level or grossly simplify the structure of the protocols considered. This thesis develops and presents techniques for automatic synthesis of provably correct on-chip protocol converters. Basing the solution on a formal approach, a novel state-machine based formalism is presented for modelling bus-based protocols and formalizing the notions of protocol compatibility and correct protocol conversion. Algorithms for automatic compatibility checking and provably-correct converter synthesis are derived from the formalism, including a systematic exploration of the design space of the protocol converter, the first in the field, which enables generation of various alternative deterministic converters. The work presented is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modelling of protocol characteristics and automatic translation of the constructed converter to HDL.

abstract: State of art modern System-On-Chip architectures often require very low noise supplies without overhead on high efficiencies. Low noise supplies are especially important in noise sensitive analog blocks such as high precision Analog-to-Digital Converters, Phase Locked Loops etc., and analog signal processing blocks. Switching regulators, while providing high efficiency power conversion suffer from inherent ripple on their output. A typical solution for high efficiency low noise supply is to cascade switching regulators with Low Dropout linear regulators (LDO) which generate inherently quiet supplies. The switching frequencies of switching regulators keep scaling to higher values in order to reduce the sizes of the passive inductor and capacitors at the output of switching regulators. This poses a challenge for existing solutions of switching regulators followed by LDO since the Power Supply Rejection (PSR) of LDOs are band-limited. In order to achieve high PSR over a wideband, the penalty would be to increase the quiescent power consumed to increase the bandwidth of the LDO and increase in solution area of the LDO. Hence, an alternative to the existing approach is required which improves the ripple cancellation at the output of switching regulator while overcoming the deficiencies of the LDO. This research focuses on developing an innovative technique to cancel the ripple at the output of switching regulator which is scalable across a wide range of switching frequencies. The proposed technique consists of a primary ripple canceller and an auxiliary ripple canceller, both of which facilitate in the generation of a quiet supply and help to attenuate the ripple at the output of buck converter by over 22dB. These techniques can be applied to any DC-DC converter and are scalable across frequency, load current, output voltage as compared to LDO without significant overhead on efficiency or area. The proposed technique also presents a fully integrated solution without the need of additional off-chip components which, considering the push for full-integration of Power Management Integrated Circuits, is a big advantage over using LDOs. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

The Worldwide Interoperability for Microwave Access, or WiMax, is a wireless communication technique based on IEEE 802.16 standards. Its advantage of sending high data rates over long distances, while using a single base station to cover a large area, has made this technique a flexible and reliable solution for public wireless networks. WiMax has two main types of networks: Fixed and Mobile. The most popular transceiver used in WiMax applications is the “Direct-Conversion Architecture” due to its high level of integration and less component requirements, which leads to reduced power dissipation. In Direct Conversion Architecture, the mixer is a key block in the transceiver chain. Depending on design specifications and constraints, different types of mixers may be considered. However, the most appropriate down converter mixer for WiMax applications is the Gilbert-cell mixer. This thesis will then explore the design of a down converter Gilbert-Cell Mixer within the realm of Fixed WiMax technology. This design was achieved in the commercial circuit simulator Advanced Design System (ADS) using the 0.15mm InGaAs pHEMT technology process provided by Win Semiconductor Crop.

Hydrogen is a potential future energy storage medium to supplement a variety of renewable energy sources. It can be regarded as an environmentally-friendly fuel, especially when it is extracted from water using electricity obtained from solar panels or wind turbines. The focus in this thesis is on solar energy, and the theoretical background (i.e., PSCAD computer simulation) and experimental work related to a water-splitting, hydrogen-production system are presented. The hydrogen production system was powered by a photovoltaic (PV) array using a proton exchange membrane (PEM) electrolyser. The PV array and PEM electrolyser display an inherently non-linear current-voltage relationship that requires optimal matching of maximum operating power. Optimal matching between the PV system and the electrolyser is essential to maximise the transfer of electrical energy and the rate of hydrogen production. A DC/DC converter is used for power matching by shifting the PEM electrolyser I-V curve as closely as possible toward the maximum power the PV can deliver. By taking advantage of the I-V characteristics of the electrolyser (i.e., the DC/DC converter output voltage is essentially constant whereas the current increases dramatically), we demonstrated experimentally and in simulations that the hydrogen production of the PV-electrolyser system can be optimised by adjusting the duty cycle generated by the pulse-width modulation (PWM) circuit. The strategy used was to fix the duty cycle at the ratio of the PV maximum power voltage to the electrolyser operating voltage. A stand-alone PV energy system, using hydrogen as the storage medium, was designed. The system would be suitable for providing power for a family's house located in a remote area in the Libyan Sahara.

Multiple wave energy devices supported by a common structure represent one possible method of efficiently converting ocean wave energy into electricity. In this study, experimental measurements of multiple small-scale wave energy devices are reported to assist the development and validation of numerical models. Through observation and measurement, the response of two float geometries subjected to a range of wave conditions and device settings were determined. A range of regular wave conditions were identified that caused a linear relationship to occur between the heave displacement amplitude of the float and the incident wave amplitude. These test cases will enable comparisons to be made with linear simulations of response. Tests conducted in various wave conditions have highlighted the capability of altering the device response by changing the equilibrium draft of one float geometry. Additional damping on the upper surface of the float, due to wave overtopping, could be exploited as a method of limiting the heave response of the device in large amplitude waves. The influence of hydrodynamic interactions on arrays of closely spaced devices has been experimentally investigated for devices subjected to regular and irregular wave conditions. The magnitude and occurrence of interactions and their affect on the individual device response is demonstrably dependent on the incident wave frequency and device separation distance. Compared to an isolated device, positive interactions result in higher average power outputs for an array of devices at certain wave frequencies. Positive interactions occuring at particular wave frequencies are balanced by negative interactions at other wave frequencies, in agreement with published numerical studies of array performance. Varying the level of mechanical damping applied to the float through the power take-off system results in a frequency shift of the calculated power transfer function and alters the motion path of the float. This finding implies that the level of generator torque could be used as an alternative method to tune the response of the device based on the measured incident wave-field. Several time-averaged and time-varying approaches to simulating the response of a wave energy device subjected to wave-field forcing and undergoing free response have been studied. By comparing the simulated and measured responses, the feasibility of using linear and non-linear force terms in a time-varying model has been assessed. In general, single degree-of-freedom simulations based on linear hydrodynamic parameters tend to over-predict device response amplitudes, requiring the application of additional damping. The simulation approach which resulted in the closest agreement with measured responses required the combination of linear diffraction force and radiation added mass terms with non-linear drag and buoyancy force terms, as well as body inertia and gravity forces. This approach goes part way to simulating the complex time-varying hydrodynamics associated with a wave energy device subjected to wave-field forcing.

abstract: Modular multilevel converters (MMCs) have become an attractive technology for high power applications. One of the main challenges associated with control and operation of the MMC-based systems is to smoothly precharge submodule (SM) capacitors to the nominal voltage during the startup process. The existing closed-loop methods require additional effort to analyze the small-signal model of MMC and tune control parameters. The existing open-loop methods require auxiliary voltage sources to charge SM capacitors, which add to the system complexity and cost. A generalized precharging strategy is proposed in this thesis. For large-scale MMC-embedded power systems, it is required to investigate dynamic performance, fault characteristics, and stability. Modeling of the MMC is one of the challenges associated with the study of large-scale MMC-based power systems. The existing models of MMC did not consider the various configurations of SMs and different operating conditions. An improved equivalent circuit model is proposed in this thesis. The solid state transformer (SST) has been investigated for the distribution systems to reduce the volume and weight of power transformer. Recently, the MMC is employed into the SST due to its salient features. For design and control of the MMC-based SST, its operational principles are comprehensively analyzed. Based on the analysis, its mathematical model is developed for evaluating steady-state performances. For optimal design of the MMC-based SST, the mathematical model is modified by considering circuit parameters. One of the challenges of the MMC-based SST is the balancing of capacitor voltages. The performances of various voltage balancing algorithms and different modulation methods have not been comprehensively evaluated. In this thesis, the performances of different voltage-balancing algorithms and modulation methods are analyzed and evaluated. Based on the analysis, two improved voltage-balancing algorithms are proposed in this thesis. For design of the MMC-based SST, existing references only focus on optimal design of medium-frequency transformer (MFT). In this thesis, an optimal design procedure is developed for the MMC under medium-frequency operation based on the mathematical model of the MMC-based SST. The design performance of MMC is comprehensively evaluated based on free system parameters. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020