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Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters. Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis. VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept. CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented. VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control. CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage. / Ph. D.

Advances in very large scale integration (VLSI) technologies impose challenges for voltage regulator modules (VRM) to deliver high-quality power to modern microprocessors. As an enabling technology, multiphase converters have become the standard practice in VRM industry. The primary objectives of this dissertation are to develop advanced topologies and innovative integrated magnetics for high-efficiency, high-power-density and fast-transient VRMs. The optimization of multiphase VRMs has also been addressed. Today's multiphase VRMs are almost universally based on the buck topology. With increased input voltage and decreased output voltage, the multiphase buck converter suffers from a very small duty cycle and cannot achieve a desirable efficiency. The multiphase tapped-inductor buck converter is one of the simplest topologies with a decent duty cycle. However, the leakage inductance of its tapped inductors causes a severe voltage spike problem. An improved topology, named the multiphase coupled-buck converter, is proposed. This innovative topology enables the use of a larger duty cycle with clamped device voltage and recovered leakage energy. Under the same transient responses, the multiphase coupled-buck converter has a significantly better efficiency than the multiphase buck converter. By integrating all the magnetic components into a single core, in which the windings are wound around the center leg and the air gaps are placed on the two outer legs, it is possible for multiphase VRMs to further improve efficiency and cut the size and cost. Unfortunately, this structure suffers from an undesirable core structure and huge leakage inductance. An improved integrated magnetic structure is proposed to overcome these limitations. All the windings are wound around the two outer legs and the air gap is placed on the center leg. The improved structure also features the flux ripple cancellation in the center leg and strongly reverse-coupled inductors. Both core loss and winding loss are reduced. The steady-state current ripples can be reduced without compromising the transient responses. The overall efficiency of the converter is improved. The input inductor can also be integrated in the improved integrated magnetic structure. Currently, selecting the appropriate number of channels for multiphase VRMs is still an empirical trial-and-error process. This dissertation proposes a methodology for determining the right number of channels for the optimal multiphase design. The problem formulation and general method for the optimization are proposed. Two examples are performed step by step to demonstrate the proposed optimization methodology. Both are focused on typical VRM 9.0 designs for the latest Pentium 4® microprocessors and their results are compared with the industry practice. / Ph. D.

This research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex. This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics. The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint. / Ph. D.

The conventional power factor correction circuit has a fixed output voltage. However, in some applications, a PFC circuit with a wide output voltage range is needed. A single phase power factor correction circuit with wide output voltage range is developed in this work. After a comparison of two main power stage candidates (Buck+Boost and Sepic) in terms of efficiency, complexity, cost and device rating, the buck+boost converter is employed as the variable output PFC power stage. From the loss analysis, this topology has a high efficiency from light load to heavy load. The control system of the variable output PFC circuit is analyzed and designed. Charge average current sensing scheme has been adopted to sense the input current. The problem of high input harmonic currents at low output voltage is discussed. It is found that the current loop gain and cross over frequency will change greatly when the output voltage changes. To solve this problem, an automatic gain control scheme is proposed and a detailed circuit is designed and added to the current loop. A modified input current sensing scheme is presented to overcome the problem of an insufficient phase margin of the PFC circuit near the maximum output voltage. The charge average current sensing circuit will be bypassed automatically by a logical circuit when the output voltage is higher than the peak line voltage. Instead, a resistor is used to sense the input current at that condition. Therefore, the phase delay caused by the charge average current sensing circuit is avoided. The design and analysis are based on a novel air conditioner motor system application. Some detailed design issues are discussed. The experimental results show that the variable output PFC circuit has good performance in the wide output voltage range, under both the Boost mode when the output voltage is high and the Buck+Boost mode when the output voltage is low. / Master of Science

Analysis of three-phase, three-level VSIs is done for high-power high-voltage applications. Complete Space Vector Modulation (SVM) algorithm is developed for a three-phase, three-level converter. Special attention is given to minimization of output ripple and voltage balance of the dc-link input capacitors. Verification of the proposed SVM algorithm is done by computer simulation. Comprehensive small-signal modeling of the three-level converter with a resistive load is developed the first time. Steady-state solutions reveal that the voltage across dc-link input capacitors is constant at the half of the dc-link voltage. / Master of Science

DC nano-grid system shows promising prospect and enjoys some advantages over AC micro-grid system. It enables easier integration of multiple renewable energy sources with multiple loads. Photovoltaic (PV) is essentially a typical renewable source that serves as main power source in DC nano-grid system. Traditional PV system includes centralized PV system, string PV system and micro-converter PV system. More recently, smart converter PV system has been introduced and shown great improvement in aspects of power generation achieved by distributed Maximum Power Point Tracking (MPPT). It is also advantageous over micro-converter PV system due to lower cost and flexibility. Detailed case study demonstrates that power generation efficiency can be easily compromised because of mismatch between different panels in centralized and string PV systems. In smart converter PV system, this problem can be solved due to distributed MPPT for each individual panel. The smart converter system has a very wide voltage range within which all panels can generate maximum power. The location and the width of this range are subject to change under different mismatch conditions. A second stage converter is needed to locate the array MPPT range. However, there is instability problem when doing second stage MPPT with traditional methods. Modified methods based on conductance control and resistance control are analyzed and compared. Both methods can solve the MPPT instability problem. However, in terms of steady state performance, resistance control MPPT is more promising in terms of higher utilization ratio and faster tracking speed. It is because both methods are of inherited variable operating point step size with constant conductance or resistance perturbation step size. However, the operating point change decreases with resistance perturbation but increases with conductance perturbation otherwise. Therefore, resistance control MPPT is chosen as a good candidate. Both simulation and experimental results verifies the concept. / Master of Science

The demand for high power density, high efficiency bus converters has increased interest in resonant topologies, particularly the LLC resonant converter. LLC resonant converters offer several advantages in efficiency, power density, and hold up time extension capability. Among high voltage (>500V) MOSFETs, Super Junction MOSFETs, such as Infineon's CoolMOS parts, offer lower Rds on than conventional parts and are a natural choice for this application to improve efficiency. However, there is a history of converter failure due to reverse recovery problems with the primary switch's body diode. Before selecting CoolMOS devices for use in a LLC resonant converter, it is necessary to investigate its performance in this application. Field failures of PWM soft switching phase shift full bridge converters have been attributed to large reverse recovery charge in the primary side MOSFET body diode. Under low load conditions the device cannot fully recover, and the large reverse recovery current can cause the device to enter secondary break down, leading to failure. The unique structure of Super Junction MOSFETs, such as CoolMOS, avoid this failure mode by providing a different path for the reverse current; however, the reverse recovery charge of CoolMOS devices is large and can cause a loss of efficiency. For this reason, it is important to avoid conditions under which the reverse recovery characteristics of the body diode can be seen. / Master of Science

This thesis presents the conducted electro-magnetic interference (EMI) prediction results for a continuous conduction mode (CCM) power factor correction (PFC) converter as well as the theoretical analysis for the noise generation and propagation mechanisms. In this thesis, multiple modeling and characterization techniques in the medium and high frequency ranges are developed for the circuit components that are important contributors to the EMI noise, so that a detailed simulation circuit for EMI prediction can be constructed. The conducted EMI noise prediction from the simulation circuit closely matches the measurement results obtained by a spectrum analyzer. Simulation time step and noise separator selection are two important issues for the noise simulation and measurement. These two issues are addressed and the solutions are proposed. The conducted EMI generation and propagation mechanisms are analyzed in a systematic way. Two loop models are proposed to explain the EMI noise behavior. The effects of the PFC inductor, the parasitic capacitance between the device and the heatsink, the rising/falling time of the MOSFET VDS voltage, and the input wires are studied to verify the validity of the loop models. / Master of Science

This master thesis is done within the Energy Systems Engineering program at Uppsala University and performed for CorPower Ocean. Wave energy converters (WECs) are devices that utilize ocean waves for generation of electricity. The WEC developed by CorPower Ocean is small and intended to be deployed in an array. Placed in an array the different WECs will interact hydrodynamically and the combined power output is altered. The aim of this thesis is to model and investigate how the array configuration affects the electric power output. The goal is to target an optimal array layout for CorPower Ocean WECs, considering both average power and power smoothness in the optimization.   In this thesis multiple buoys have been implemented in the time-domain model at CorPower Ocean. The hydrodynamic interactions are computed using an analytical interactions theory together with a recently developed calibration method able of handling WEC bodies of complicated shapes. The array behavior in regular waves is analyzed and it is identified how the beneficial separation distances vary with wave length. It is observed that the best separation distances for high average power does not exactly correspond to the best for minimizing the peak-to-average power. Simulation results show that it is possible to obtain both high average array power as well as increased power smoothening in a regular wave. A genetic algorithm for optimizing the array configuration is designed and tested for two different array patterns. Initial simulations are conducted in realistic multi-directional irregular waves. The power smoothening capacity of the array remains even in these conditions but the exact extent of it is still uncertain.   This thesis delivers a WEC array simulation model as well as an initial view on the array characteristics of the phase controlled CorPower Ocean WEC. Additionally, it demonstrates an optimization algorithm taking both average power and power smoothness into account.