DC/DC buck converters are cascaded in order to generate proper load voltages. Rectified line voltage is normally converted to 48V, which then, by a bus voltage regulating converter also called the line conditioner converter, is converted to the bus voltage, e.g. 12V. A polynomial controller converter transforms the 12V into to a suitable load voltage, a fraction of or some few voltages. All cascaded converters are individually controlled in order to keep the output voltage stable constant. In this presentation focusing on the polynomial controller converter implemented as Ericsson’s buck converter BMR450. In this paper modeling, discretization and control of a simple Buck converter is presented. For the given DC-DC-Converter-Ericsson BMR 450 series, analyzing the disturbance properties of a second order buck converter controllers by a polynomial controller. The project is performed in Matlab and Simulink. The controller properties are evaluated for measurement noise, EMC noise and for parameter changes. / +46-762795822

The market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is presented that attempts to mitigate some of the sampling rate limitations of a SAR while maintaining its power and resolution advantages. Special techniques are used to reduce the overall sampling capacitance required in both SAR stages and to increase the linearity of the multiplying digital to analog converter (MDAC) output. The SAR sampling network, control logic, and MDAC blocks are completely implemented. Ideal components were used for the clocking, comparators, and switches. At the end of this design, a figure of merit of 51 fJ/conversion-step was achieved. / text

This dissertation systematically explores multiple-input converters (MICs) configuration and topologies, and then proposes improvements on certain beneficial MICs—time-sharing MICs and soft-switching MICs for distributed generation (DG) applications with high voltage transfer ratio. Compared with other MIC families which are derived from same input and output cells, time-sharing MICs have the fewest circuit components. However, time-sharing MICs lack for bi-directional power flow capability due to their special input switches requirement. In addition, their hard-switching characteristic leads to a low efficiency problem when isolation is necessary. The dissertation investigates into time-sharing MIC input switch selection, which leads to a new driving strategy and new input switch combinations. With the new input switch combinations, bi-directional and high efficiency time-sharing MICs are made possible. Besides isolated time-sharing MIC, Soft-switching MICs might also be a common choice for high voltage transfer ratio DG applications. However, the enormous amount of circuit components makes the soft-switching MICs become less attractive. An input cell reduction method is introduced in this dissertation to greatly reduce the component count of isolated MICs, including soft-switching MICs. In addition to the improvement on existing MIC families, a new push-pull connected MIC family is proposed in this dissertation as another choice of high voltage transfer ratio DG applications. Moreover, a comparison among MIC families is made to provide a sense of topologies selection in certain applications. Prototypes of time-sharing dual-input (DI) SEPICs, a push-pull connected DI-Boost converter, and a DI full-bridge (FB) converter are built to verify aspects discussed in this dissertation. Bi-directional power flow capability of time-sharing MIC is confirmed with a time-sharing DI-SEPIC and a soft-switching time-sharing MIC is realized by an isolated time-sharing DI-SEPIC with an active clamping leg. Maximum power point tracking control feasibility in these converters is evaluated with real photovoltaic modules that are connected to the push-pull connected DI-Boost converter that uses a perturb-and-observe method. Finally, an efficiency comparison is made between time-sharing MIC and push-pull connected MIC. / text

Η παρούσα διπλωματική εργασία είχε σαν στόχο τον σχεδιασμό και την υλοποίηση τεσσάρων μετατροπέων από αναλογικό σε ψηφιακό σήμα και οι οποίοι είναι οι εξής: • Ο Dual-Slope Analog to Digital Converter. • O Tracking Analog to Digital Converter. • O Successive Approximation Analog to Digital Converter. • O Algorithmic Analog to Digital Converter. Η παραπάνω υλοποίηση αποτελεί μέρος ενός μεγαλύτερου σχεδίου, που διεξάγεται στο Εργαστήριο Ηλεκτρονικών Εφαρμογών του τμήματος Ηλεκτρολόγων Μηχανικών και Τεχνολογίας Υπολογιστών του Πανεπιστημίου Πατρών. Στόχος της ιδέας αυτής είναι η δημιουργία ενός «εξ Αποστάσεως Ελεγχόμενου Εργαστηρίου Ηλεκτρονικών» (Remoted Monitored & Controled Laboratory), το οποίο αφενός δεν θα υστερεί σε τίποτα από τα συνηθισμένα εργαστήρια, αφετέρου θα είναι εύκολα προσπελάσιμο από οποιονδήποτε το θελήσει, αφού θα μπορεί να δουλέψει ακόμα και «κατ’οίκον» μέσω του Διαδικτύου. / In this work four Analog to Digital converters has been designed and implemented on a single PCB: Dual-Slope Analog to Digital Converter. Tracking Analog to Digital Converter. Successive Approximation Analog to Digital Converter. Algorithmic Analog to Digital Converter. The aforementioned system of four converters enchances the capabilities of an internal project that is carried out in the Laboratory of Electronic Applications of the ECE department of University Patras. Objective of this project named “Remoted Monitored & Controled Laboratory” (RMCLab), is to provide to the departmet’s students access via the internet to an electronic laboratory that employs real infrastructure, real hardware and real circuits.

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

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The power supply designers choose flyback topology due to its promising features of design simplicity, cost effectiveness and multiple outputs handling capability. The designed product based on flyback topology should be smaller in size, cost effective and energy efficient. Similarly, designers focus on reducing the circuit losses while operating at high frequencies that affect the converter efficiency and performance. Based on the above circumstances, an energy efficient open loop high frequency flyback converter is designed and operated in MHz frequency region using step down multilayer PCB planar transformer. The maximum efficiency of 84.75% is observed and maximum output power level reached is 22.8W. To overcome the switching losses, quasi-resonant soft switching technique is adopted and a high voltage CoolMOS power transistor is used.

Primarily because of its low cost and ease of implementation, analogue control has been the dominant control strategy in modern switch-mode power supply designs. The 'on/off' nature of power switches is essentially digital, which makes it tempting for power elec- tronics engineers to combine the emerging capability of digital technologies with existing switch-mode power supply designs. Whereas an analogue controller is usually cheaper to implement, it lacks the flexibility and capacity to implement the complex control func- tions which a digital controller can offer. The research presented in this thesis addresses the practical implementation of a digi- tal controller for a Series-Loaded Resonant Converter (SLR). The resonant frequency of the SLR converter is around 60 kHz, and the switching frequency varies up to around 80 kHz to regulate the 12V dc output voltage across a 100W, variable resistive load, from a variable 46.6V 60.2V input voltage. This provides a fair challenge for digital waveform generators as the digital processor needs to have a high clock rate to produce high speed, high resolution and linearly varying frequency square waves, to regulate the output volt- age with adequate resolution. Digital compensation algorithms also need to be efficient to minimise the phase lag caused by the instruction overhead. In order to completely understand the control needs of the SLR converter, an analogue controller was constructed using a UC3863N. The feedback compensation consists of an error amplifier in an integrator configuration. Digital control is accomplished with a TMS320F2812 Digital Signal Processor (DSP). Its high throughput of 150 MIPS provides sufficient resolution to digitally generate linearly varying frequency switching signals util- ising Direct Digital Synthesis (DDS). Time domain analysis of the switching signals, shows that the DDS generated square iv ABSTRACT waves display evidence of jitter to minute variations in pulse-widths caused by the digi- tisation process, while in the frequency domain, this jitter displays itself as additional sidebands that deteriorate the fundamental frequency of the switching signal. Overall, DDS generated square waves are shown experimentally to be adequate as control signals for the MOSFET power switches. Experiments with step load changes show the digi- tal controller is able to regulate the output voltage properly, with the drawback of the settling time being a little longer than the analogue counterpart, possibly caused by the unpredictable damping effects of switching signal jitter. Variations in input voltage shows that the digital controller excels at operating under noisier conditions, while the analogue controlled output has slightly greater noise as input voltage is increased. As the digital technology continues to improve its speed, size and capacity, as well as becoming more affordable, it will not be long before it becomes the leading form of control circuitry in power supplies.

This thesis deals with the problem of control system design for power electronic controllers when high performance is desired despite unaccounted for internal and external conditions. Factors such as parameter variations, operating condition changes, and filtering and measurements delays, may adversely impact the performance of a circuit whose controller design is not immune to external and internal disturbances. The thesis explores the method of internal model design as a viable approach for designing controllers with superior performance despite system variations. Following a presentation of the theoretical background of the internal model design, the thesis considers two examples of state variable models, improving the stability of a voltage source converter and speed control of an induction motor. Conclusions show the new control system is more stable and offers better controllability despite unexpected system variations, compared to classical control system.