Forests have as a of late become increasingly plagued with bark beetle infestations as a result of climate change. The damage caused by tree killing bark beetles has within recent years seen a substantial increase. Detecting and removing infested trees at an early stage is an essential part of mitigating the spread of and the damage caused by the beetle. Today, the most common way of early detection is visual detection by forestry personnel. However, this is time consuming with highly variable results. In this thesis a novel approach to tracing the European spruce bark beetle through pheromone detection is investigated. With this approach, the antennae of the beetle were paired with an epitaxial graphene chip in order to create a bioinspired smell sensor. Tests were conducted on the sensor in order to investigate how the resistance changed over the chip as a result of the sensor being exposed to the pheromone 2-methyl-3-buten-2-ol. As a result of the tests, a corelation between exposing the sensor to pheromone and an increase of the resistance over the graphene chip was noted. However, more tests need to be conducted in order to draw any definite conclusions about the efficacy of the sensor in its current form. Additionally there are opportunities to investigate further optimization alternatives regarding the design of the sensor.

Este trabalho apresenta o estudo do comportamento da resistência série de fonte e dreno em transistores SOI FinFET de porta tripla e com canal tensionado. Nos dispositivos SOI FinFETs há um aumento da resistência série de fonte e dreno devido ao estreitamento dessas regiões, sendo esse parâmetro considerado como uma das limitações quanto à introdução desses dispositivos em tecnologias futuras. O uso de tensão mecânica no canal dos dispositivos surge como alternativa para aumentar a condução de corrente através do aumento da mobilidade dos portadores do canal, reduzindo assim, a resistência total dos transistores e, conseqüentemente, a resistência série de fonte e dreno. Inicialmente, foi feito o estudo de alguns métodos de extração da resistência série de fonte e dreno existentes na literatura, com o objetivo de se obter o mais adequado para aplicação e análise posterior. Esse trabalho foi realizado baseado em resultados experimentais e em simulações numéricas que possibilitaram o entendimento físico do fenômeno estudado. A resistência série de fonte e dreno foi explorada em diferentes tecnologias, como transistores SOI FinFETs de porta tripla convencionais e sob influência de tensionamento uniaxial e biaxial. O uso do crescimento seletivo epitaxial (SEG) nas regiões de fonte e dreno altamente dopadas das diferentes tecnologias também foi analisado, pois com essa técnica, a resistência série de fonte e dreno é reduzida substancialmente não comprometendo a condução de corrente e a transcondutância. Os resultados obtidos das diferentes tecnologias com e sem o uso de SEG foram analisados e comparados mostrando que em transistores SOI FinFETs de porta tripla, com crescimento seletivo epitaxial, apresentam o menor valor da resistência série de fonte e dreno mesmo para aqueles sem tensão mecânica na região do canal. / This work presents the study of the source and drain series resistance behavior in standard and strained SOI FinFETs triple gate transistors. In SOI FinFETs transistors there is an increase of the source and drain series resistance due to the narrow of these regions, being this parameter a key limiting factor to the next generations. The use of strained transistors is one of the potential technologies to the next generation high performance because it increase the drive current through an enhance in the carrier mobility, decreasing the transistors total resistance and, therefore, the source and drain series resistance. Initially, a study of some series resistance extraction methods, present in the literature was done, in order to obtain the most appropriate for applications and analysis subsequent. This work was done based on experimental results and numerical simulations, enabling the physical understanding of the phenomenon studied. The series resistance was explored in different technologies, as standard SOI FinFETs triple gates and with uniaxial and biaxial strain. The use of selective epitaxial growth (SEG) in the source and drain regions, with high doping levels, was also studied in the different technologies, because with the use of this technique, the series resistance decreases substantially without compromising the drive current and transconductance. The obtained results from the different technologies with and without the use of SEG were analyzed and compared showing that, SOI FinFETs triple gate transistors with SEG present the lower values of series resistance even for standard devices if compared with strained ones without the use of SEG.

Este trabalho apresenta o estudo da influência do tensionamento mecânico (strain) no efeito de abaixamento de barreira induzido pelo dreno (DIBL) em dispositivos SOI FinFETs de porta tripla com e sem crescimento seletivo epitaxial. Também é analisada a influência do uso de crescimento seletivo epitaxial nesses dispositivos em relação ao efeito de canal curto mencionado. O uso de transistores verticais de múltiplas portas tem permitido a continuidade do escalamento dos dispositivos, apresentando melhora nos níveis de corrente bem como a supressão dos efeitos de canal curto. No entanto, ao reduzir a largura do canal, aumenta-se a resistência total do transistor, diminuindo seu desempenho. A fim de melhorar essa característica, as técnicas de tensionamento mecânico e crescimento de fonte e dreno tem sido empregadas. No primeiro caso, ao se deformar mecanicamente a estrutura do canal, altera-se o arranjo das camadas eletrônicas que ocasiona o aumento da mobilidade dos portadores. Conseqüentemente, a corrente aumenta tal como a transcondutância do dispositivo. A técnica de crescimento de fonte e dreno chamada de crescimento seletivo epitaxial (SEG) tem como finalidade reduzir ainda mais a resistência elétrica total da estrutura, uma vez que a área dessas regiões aumenta, possibilitando o aumento das áreas de contato, que são responsáveis pela maior parcela da resistência total. Esse trabalho baseia-se em resultados experimentais e simulações numéricas tridimensionais que analisam o comportamento dos transistores com as tecnologias acima apresentadas em função do efeito de DIBL. / This work presents a study about the influence of strain in the drain induced barrier lowering effect (DIBL) in triple gate SOI FinFETs. Also it is analyzed the selective epitaxial growth used in that structures, comparing their behavior in relation to DIBL effect. Using the vertical multi-gate devices become possible the downscale whereas they present higher current level and suppressed short channel effects. However, reducing the channel width, the transistors total resistance increases and consequently its performance decreases. In order to improve this feature, the strained technology and the Source/Drains growth technique has been employed. In the first case, the mechanical deformation causes a change in the electron shell, which improves the carrier mobility. Consequently, the current level and the transconductance also improve. The selective epitaxial growth technique aims to reduce the devices total resistance since these regions areas increase, allowing large contacts which are responsible for the main parcel of the total resistance. This work is based on experimental results and tridimensional simulations that analyze the transistor behavior using the technologies above presented as a function of DIBL effect.

Este trabalho apresenta o estudo do comportamento da resistência série de fonte e dreno em transistores SOI FinFET de porta tripla e com canal tensionado. Nos dispositivos SOI FinFETs há um aumento da resistência série de fonte e dreno devido ao estreitamento dessas regiões, sendo esse parâmetro considerado como uma das limitações quanto à introdução desses dispositivos em tecnologias futuras. O uso de tensão mecânica no canal dos dispositivos surge como alternativa para aumentar a condução de corrente através do aumento da mobilidade dos portadores do canal, reduzindo assim, a resistência total dos transistores e, conseqüentemente, a resistência série de fonte e dreno. Inicialmente, foi feito o estudo de alguns métodos de extração da resistência série de fonte e dreno existentes na literatura, com o objetivo de se obter o mais adequado para aplicação e análise posterior. Esse trabalho foi realizado baseado em resultados experimentais e em simulações numéricas que possibilitaram o entendimento físico do fenômeno estudado. A resistência série de fonte e dreno foi explorada em diferentes tecnologias, como transistores SOI FinFETs de porta tripla convencionais e sob influência de tensionamento uniaxial e biaxial. O uso do crescimento seletivo epitaxial (SEG) nas regiões de fonte e dreno altamente dopadas das diferentes tecnologias também foi analisado, pois com essa técnica, a resistência série de fonte e dreno é reduzida substancialmente não comprometendo a condução de corrente e a transcondutância. Os resultados obtidos das diferentes tecnologias com e sem o uso de SEG foram analisados e comparados mostrando que em transistores SOI FinFETs de porta tripla, com crescimento seletivo epitaxial, apresentam o menor valor da resistência série de fonte e dreno mesmo para aqueles sem tensão mecânica na região do canal. / This work presents the study of the source and drain series resistance behavior in standard and strained SOI FinFETs triple gate transistors. In SOI FinFETs transistors there is an increase of the source and drain series resistance due to the narrow of these regions, being this parameter a key limiting factor to the next generations. The use of strained transistors is one of the potential technologies to the next generation high performance because it increase the drive current through an enhance in the carrier mobility, decreasing the transistors total resistance and, therefore, the source and drain series resistance. Initially, a study of some series resistance extraction methods, present in the literature was done, in order to obtain the most appropriate for applications and analysis subsequent. This work was done based on experimental results and numerical simulations, enabling the physical understanding of the phenomenon studied. The series resistance was explored in different technologies, as standard SOI FinFETs triple gates and with uniaxial and biaxial strain. The use of selective epitaxial growth (SEG) in the source and drain regions, with high doping levels, was also studied in the different technologies, because with the use of this technique, the series resistance decreases substantially without compromising the drive current and transconductance. The obtained results from the different technologies with and without the use of SEG were analyzed and compared showing that, SOI FinFETs triple gate transistors with SEG present the lower values of series resistance even for standard devices if compared with strained ones without the use of SEG.

The present research work focuses on the fabrication and characterization of epitaxial heterostructures of 0.7 Pb(Mg1/3N2/3)O3 – 0.3 PbTiO3 (PMN-PT) and La0.6Sr0.4MnO3 (LSMO) using multi target pulsed laser ablation technique. Different heterostructures such as bilayered thin films with different individual layer thickness; symmetric and asymmetric superlattices of different periodicities were fabricated. Roles of individual layer thickness, elastic strain and interfaces between PMN-PT and LSMO layers on different physical properties were studied. An attempt has been made to understand the influence of the charge depleted interface states in addition to the probable strain mediated elastic coupling effect on the observed magneto-dielectric response in these engineered heterostructures. Chapter 1 provides a brief introduction to the multiferroic materials, occurrence of magnetoelectric (ME) coupling in them, their possible technological applications and the challenges involved. A short historical account of the multiferroic research is discussed to emphasize the importance of artificial multiferroics, particularly the engineered thin film heterostructures. Finally the specific objectives of the current research are outlined. Chapter 2 deals with the various experimental studies carried out in this research work. It gives the details of the experimental set up and the basic operation principles of various structural and physical characterizations of the materials prepared. A brief explanation of material fabrication, structural, micro structural and physical property measurements is discussed. Chapter 3 addresses the phase formation, structural and microstructural features of the engineered heterostructures fabricated epitaxially on single crystalline LaAlO3 (100) substrates. A thin layer of LaNiO3 used as the bottom electrode material for electrical characterizations was grown on the bare substrate prior to the fabrication of the PMN-PT/LSMO heterostructures. The structural and microstructural features of different individual layers were also studied by fabricating single layer thin films of the materials. The effects of individual layer thicknesses on the surface roughness, grain size and lattice strain of the heterostructures are discussed. Chapter 4 deals with the ferroelectric studies of the PMN-PT/LSMO epitaxial heterostructures. Polarization hysteresis (P-E), capacitance – voltage (C-V) and pulsed polarization (PUND) measurements were carried out as functions of applied voltage, frequency and delay time to characterize the ferroelectric properties of the heterostructures. All the bilayered heterostructures exhibited robust ferroelectric response and contribution of non – remnant components to their polarization behaviour were observed from the P-E studies. The symmetric superlattices did not exhibit any ferroelectricity due to high leakage current conduction. After optimizing the LSMO and PMN-PT layer thicknesses ferroelectricity was observed in the asymmetric superlattices accompanied by substantial reduction in the leakage current conduction. The P-E loops were found to be asymmetrically shifted along the electric field axis in all the superlattices indicating the presence of dielectric passive layers and strong depolarizing fields at the interfaces between PMN-PT and LSMO. Chapter 5 deals with the ferromagnetic studies of the PMN-PT/LSMO heterostructures. All the heterostructures exhibited ferromagnetic behaviour in the temperature range of 10 K – 300 K with an in plane magnetic easy axis ([100]) compared to the out of plane ([001]) direction. The magnetization behaviour of the bilayers and superlattices as a function of magnetic field strength, temperature and different individual layer thickness of PMN-PT and LSMO are discussed in terms of the oxygen deficiency, magnetic dead layers and lattice strain effects in these engineered epitaxial heterostructures. Chapter 6 addresses the magneto-dielectric response, dielectric properties and ac conduction properties of the engineered biferroic heterostructures. In order to investigate the manifestation of strain mediated ME coupling in these heterostructures their dielectric response as a function of ac electric signal frequency have been studied under different static magnetic fields over a wide range of temperatures. The appearance of magneto-capacitance and its dependence on magnetic field strength and temperature along with the magnetoresistive characteristics of the heterostructures suggested that the charge depleted interfaces between PMN-PT and LSMO can have an effect on the observed dielectric response in addition to the probable strain mediated ME coupling. Dielectric characterization of the heterostructures performed over a wide range of temperature indicated a Maxwell-Wagner type relaxation mechanism. The manifestation of Maxwell-Wagner effect and the very low activation energy of ac conductivity obtained from the ac conduction studies revealed the strong influence of the charge depleted interfaces between PMN-PT and LSMO on the dielectric properties of the heterostructures. Chapter 7 deals with the dc leakage current conduction characteristics of the heterostructures. The leakage current characterization was performed over a wide range of temperature and analyzed in the framework of different models to investigate the leakage mechanism. All the heterostructures were found to obey the power law I∝Vα over the entire range of temperature with different values of α at different applied voltages. The bilayered heterostructures exhibited ohmic conduction in the lower electric field region and space charge limited conduction was observed at higher electric fields. On the other hand the low field dc conduction behaviour of the superlattices could not be attributed unambiguously to a single mechanism. Depending on the superlattice periodicity the low field conduction behaviour was dominated by either Poole-Frenkel (PF) emission or a combined contribution from the PF effect and ohmic conduction. At higher electric fields all the superlattices exhibited space charge limited conduction. Chapter 8 gives the summary and conclusions of the present study and also discusses about the future work that could give more insight into the understanding of the engineered epitaxial biferroic heterostructures.

Este trabalho apresenta o estudo da influência do tensionamento mecânico (strain) no efeito de abaixamento de barreira induzido pelo dreno (DIBL) em dispositivos SOI FinFETs de porta tripla com e sem crescimento seletivo epitaxial. Também é analisada a influência do uso de crescimento seletivo epitaxial nesses dispositivos em relação ao efeito de canal curto mencionado. O uso de transistores verticais de múltiplas portas tem permitido a continuidade do escalamento dos dispositivos, apresentando melhora nos níveis de corrente bem como a supressão dos efeitos de canal curto. No entanto, ao reduzir a largura do canal, aumenta-se a resistência total do transistor, diminuindo seu desempenho. A fim de melhorar essa característica, as técnicas de tensionamento mecânico e crescimento de fonte e dreno tem sido empregadas. No primeiro caso, ao se deformar mecanicamente a estrutura do canal, altera-se o arranjo das camadas eletrônicas que ocasiona o aumento da mobilidade dos portadores. Conseqüentemente, a corrente aumenta tal como a transcondutância do dispositivo. A técnica de crescimento de fonte e dreno chamada de crescimento seletivo epitaxial (SEG) tem como finalidade reduzir ainda mais a resistência elétrica total da estrutura, uma vez que a área dessas regiões aumenta, possibilitando o aumento das áreas de contato, que são responsáveis pela maior parcela da resistência total. Esse trabalho baseia-se em resultados experimentais e simulações numéricas tridimensionais que analisam o comportamento dos transistores com as tecnologias acima apresentadas em função do efeito de DIBL. / This work presents a study about the influence of strain in the drain induced barrier lowering effect (DIBL) in triple gate SOI FinFETs. Also it is analyzed the selective epitaxial growth used in that structures, comparing their behavior in relation to DIBL effect. Using the vertical multi-gate devices become possible the downscale whereas they present higher current level and suppressed short channel effects. However, reducing the channel width, the transistors total resistance increases and consequently its performance decreases. In order to improve this feature, the strained technology and the Source/Drains growth technique has been employed. In the first case, the mechanical deformation causes a change in the electron shell, which improves the carrier mobility. Consequently, the current level and the transconductance also improve. The selective epitaxial growth technique aims to reduce the devices total resistance since these regions areas increase, allowing large contacts which are responsible for the main parcel of the total resistance. This work is based on experimental results and tridimensional simulations that analyze the transistor behavior using the technologies above presented as a function of DIBL effect.

[pt] Substratos de germânio (Ge) são utilizados para o crescimento de dispositivos optoeletrônicos III-V, como células solares. Porém, o Ge é uma matéria-prima crítica devido à sua disponibilidade limitada. Além disso, o substrato de Ge representa cerca de 30-40 por cento dos custos totais de uma célula solar de junção tripla. Neste trabalho, foram crescidas amostras e células solares III-V sobre substratos de Ge com diferentes tecnologias (tec). Três diferentes tecs foram investigadas: 1) utilizando substratos de Ge com camadas porosas para crescer materiais III-V, sendo que a camada porosa é retirada para que o substrato possa ser reutilizado; 2) utilizando substratos mais finos e com menos processos de finalização da superfície, o que a deixa mais rugosa comparada a substratos comerciais; 3) substituindo o substrato de Ge por substratos alternativos que compreendam outros elementos, como um substrato de Si onde é depositado um buffer metamórfico de SiGe, no qual o parâmetro de rede foi ajustado até o chegar no de Si0.1Ge0.9. Os substratos utilizados não são perfeitos como os substratos comerciais de Ge e podem gerar defeitos nas camadas de III-V subsequentes. Para investigar a influência desses substratos nas camadas III-V foram crescidas heteroestruturas duplas (HED) de AlGaInAs/GaInAs nos substratos das tecs 1 e 2 e HED de AlGaAs/GaAs nos substratos da tec 3. Suas propriedades foram avaliadas com AFM para obter a rugosidade média quadrática e possíveis defeitos da superfície, catodoluminescência para estimar a densidade de defeitos na estrutura e Electron Channeling Contrast Imaging para identificar os tipos de defeitos encontrados com CL. Além disso, para as amostras crescidas sobre os substratos tec 1, suas composições e espessuras foram investigadas por XRD e com fotoluminescência resolvida no tempo avaliou-se o tempo de vida dos elétrons. Nos substratos das tecs 2 e 3 também foram crescidas células solares de junção tripla, que foram processadas e caracterizadas por curvas I-V e EQE. Os resultados obtidos com todas as tecs levam a uma perspectiva otimista para um futuro com células solares mais baratas e que utilizem menos Ge. / [en] Germanium (Ge) substrates are used for the growth of III-V optoelectronic devices such as solar cells. However, Ge is a critical raw material due to its limited availability. Furthermore, Ge substrate accounts for about 30-40 percent of the total costs of a triple junction solar cell. In this work III-V samples and solar cells were grown on Ge substrates with different technologies (techs). Three different techs were investigated: 1) using Ge substrates with porous layers to grow III-V materials, in which the porous layer is removed so that the substrate can be reused; 2) using thinner substrates and with fewer surface finishing processes, which makes it rougher compared to commercial substrates; 3) replacing the Ge substrate with alternative substrates that comprise other elements, such as a Si substrate where a metamorphic SiGe buffer is deposited, in which the lattice parameter is gradually adjusted until it reaches Si0.1 Ge0.9. The substrates used are not as perfect as commercial Ge substrates and can generate defects in the subsequent III-V layers. To investigate the influence of these substrates on III-V layers, double heterostructures (DH) of AlGaInAs/GaInAs were grown on the substrates of techs 1 and 2 and DH of AlGaAs/GaAs on the substrates of tech 3. Their properties were evaluated with AFM to obtain the root mean square roughness and possible surface defects, cathodoluminescence to estimate the density of defects in the structure and Electron Channeling Contrast Imaging to identify the types of defects found with CL. Furthermore, for samples grown on tech 1 substrates, the compositions and thicknesses were evaluated by XRD, and with time-resolved photoluminescence, the lifetime of the electrons was evaluated. Triple junction solar cells were also grown on techs 2 and 3 substrates, which were processed and characterized by I-V and EQE curves. The results obtained with all tecs lead to an optimistic perspective for a future with cheaper solar cells that use less Ge.

For graphene to be a viable platform for nanoscale devices, high quality growth and structures are necessary. This means structuring the SiC surface to prevent graphene from having to be patterned using standard microelectronic processes. Presented in this thesis are new processes aimed at improving the graphene as well as devices based on high quality graphene nanoribbons. Amorphous carbon (aC) corrals deposited prior to graphene growth are demonstrated to control SiC step-flow. SiC steps are shown to be aligned by the presence of the corrals and can increase SiC terrace widths. aC contacts deposited and crystallized during graphene growth are shown as a way to contact graphene without metal lift-off. Observation of the Quantum Hall Effect demonstrates the high quality of the graphene grown alongside the nanocrystalline graphite contacts. Continuing the ballistic transport measurements on sidewall graphene nanoribbons, the invasive probe effect is observed using an atomic force microscope (AFM) based technique that spatially maps the invasive probe effect. Cleaning experiments demonstrate the role of scattering due to resist residues and environmental adsorbates on graphene nanoribbons. Finally, switches based on junctions formed in the graphene nanoribbons are shown as a route toward graphene based devices.

Die vorliegende Arbeit befasst sich mit dem Einfluss einer hyperthermischen Stickstoffionenbestrahlung (Ekin < 25 eV) auf das Galliumnitrid-Schichtwachstum. Dabei wird insbesondere der Einfluss einer Oberflächenrekonstruktion, einer Strukturierung der Oberfläche, einer Zwischenschicht (Pufferschicht) und der Einfluss verschiedener Siliziumsubstratorientierungen auf das epitaktische Wachstum von dünnen Galliumnitrid-Schichten nach einer hyperthermischen Stickstoffionenbestrahlung diskutiert. Ziel war es, möglichst dünne, epitaktische und defektarme Galliumnitrid-Schichten zu erhalten. Für die Charakterisierung der Galliumnitrid-Schichten und der Siliziumsubstrate standen diverse Analysemethoden zur Verfügung. Die kristalline Oberflächenstruktur konnte während des Wachstums mittels Reflexionsbeugung hochenergetischer Elektronen beobachtet werden. Nachfolgend wurde die Oberflächentopografie, die kristalline Struktur und Textur, sowie die optischen Eigenschaften der Galliumnitrid-Schichten mittels Rasterkraftmikroskopie, Röntgenstrahl-Diffraktometrie, hochauflösender Transmissionselektronenmikroskopie und Photolumineszenzspektroskopie untersucht.

Gallium Oxide (Ga2O3) has emerged over the last decade as a new up-and-coming alternative to traditional wide bandgap semiconductors. It exists as five polymorphs (α-, β-, γ-, δ-, and ε-Ga2O3), of which β-Ga2O3 is the thermodynamically stable form, and the most extensively studied phase. β-Ga2O3 has a wide bandgap of ~4.8 eV and exhibits a superior figure-of-merit for power devices compared to other wide bandgap materials, such as SiC and GaN. These make β-Ga2O3 a promising candidate in a host of electronic and optoelectronic applications. Recent advances in β-Ga2O3 single crystals growth have also made inexpensive β-Ga2O3 single crystal grown from the melt a possibility in the near future. Despite the plethora of literature on β-Ga2O3-based devices, understanding of contacts to this material --- a device component that fundamentally determines device characteristics — remained lacking. For this research, ohmic and Schottky metal contacts to Sn-doped β-Ga2O3 (-201) single crystal substrates, unintentionally doped (UID) homoepitaxial β-Ga2O3 (010) on Sn-doped β-Ga2O3 grown by molecular beam epitaxy (MBE), and UID heteroepitaxial β-Ga2O3 (-201) epitaxial layers on c-plane sapphire by metal-organic chemical vapor deposition (MOCVD) were investigated. Each of the substrates was characterized for their structural, morphological, electrical, and optical properties, the results will be presented in the following document. Nine metals (Ti, In, Ag, Sn, W, Mo, Sc, Zn, and Zr) with low to moderate work functions were studied as possible ohmic contacts to β-Ga2O3. It was found that select metals displayed either ohmic (Ti and In) or pseudo-ohmic (Ag, Sn and Zr) behavior under certain conditions. However, the morphology was often a problem as many thin film metal contacts dewetted the substrate surface. Ti with a Au capping layer with post-metallization annealing treatment was the only consistently reliable ohmic contact to β-Ga2O3. It was concluded that metal work function is not a dominant factor in forming an ohmic contact to β-Ga2O3 and that limited interfacial reactions appear to play an important role. Prior to a systematic study of Schottky contacts to β-Ga2O3, a comparison of the effects of five different wet chemical surface treatments on the β-Ga2O3 Schottky diodes was made. It was established that a treatment with an organic solvent clean followed by HCl, H2O2 and a deionized water rinse following each step yielded the best results. Schottky diodes based on (-201) β-Ga2O3 substrates and (010) β-Ga2O3 homoepitaxial layers were formed using five different Schottky metals with moderate to high work functions: W, Cu, Ni, Ir, and Pt. Schottky barrier heights (SBHs) calculated from current-voltage (I-V) and capacitance-voltage (C-V) measurements of the five selected metals were typically in the range of 1.0 – 1.3 eV and 1.6 – 2.0 eV, respectively, and showed little dependence on the metal work function. Several diodes also displayed inhomogeneous Schottky barrier behavior at room temperature. The results indicate that bulk or near-surface defects and/or unpassivated surface states may have a more dominant effect on the electrical behavior of these diodes compared to the choice of Schottky metal and its work function. Lastly, working with collaborators at Structured Materials Industries (SMI) Inc., heteroepitaxial films of Ga2O3 were grown on c-plane sapphire (001) using a variety of vapor phase epitaxy methods, including MOVPE, and halide vapor phase epitaxy (HVPE). The stable phase β-Ga2O3 was observed when grown using MOVPE technique, regardless of precursor flow rates, at temperatures ranging between 500 – 850 °C. With HVPE growth techniques, instead of the stable β-phase, we observed the growth of the metastable α- and ε-phases, often a combination of the two. Cross-sectional transmission electron microscopy (TEM) shows the better lattice matched α-phase first growing semi-coherently on the c-plane sapphire substrate, followed by domain matched epitaxy of ε-Ga2O3 on top. Secondary ion mass spectrometry (SIMS) revealed that epilayers forming the ε-phase contain higher concentrations of chlorine, which suggests that compressive stress due to Cl- impurities may play a role in the growth of ε-Ga2O3 despite it being less than thermodynamically favorable.