The main purpose of this dissertation was to address key issues in the design and analysis of RF/microwave filters for wireless applications. Since RF/microwave filters are one of the bulkiest parts of communication systems, their miniaturization is one of the most important technological challenges for the development of compact transceivers. In this work, novel miniaturization techniques were investigated for single-band, dual-band, ultra-wideband and tunable bandpass filters. In single-band filters, the use of cross-shaped fractals in half-mode substrate-integrated-waveguide bandpass filters resulted in a 37 percent size reduction. A compact bandpass filter that occupies an area of 0.315 mm2 is implemented in 90-nm CMOS technology for 20 GHz applications. For dual-band filters, using half-mode substrate-integrated-waveguides resulted in a filter that is six times smaller than its full-mode counterpart. For ultra-wideband filters, using slow-wave capacitively-loaded coplanar-waveguides resulted in a filter with improved stopband performance and frequency notch, while being 25 percent smaller in size. A major part of this work also dealt with the concept of 'hybrid' RF MEMS tunable filters where packaged, off-the-shelf RF MEMS switches were used to implement high-performance tunable filters using substrate-integrated-waveguide technology. These 'hybrid' filters are very easily fabricated compared to current state-of-the-art RF MEMS tunable filters because they do not require a clean-room facility. Both the full-mode and half-mode substrate-integrated waveguide tunable filters reported in this work have the best Q-factors (93 - 132 and 75 - 140, respectively) compared to any 'hybrid' RF MEMS tunable filter reported in current literature. Also, the half-mode substrate-integrated waveguide tunable filter is 2.5 times smaller than its full-mode counterpart while having similar performance. This dissertation also presented detailed analytical and simulation-based studies of nonlinear noise phenomena induced by Brownian motion in all-pole RF MEMS tunable filters. Two independent mathematical methods are proposed to calculate phase noise in RF MEMS tunable filters: (1) pole-perturbation approach, and (2) admittance-approach. These methods are compared to each other and to harmonic balance noise simulations using the CAD-model of the RF MEMS switch. To account for the switch nonlinearity in the mathematical methods, a nonlinear nodal analysis technique for tunable filters is also presented. In summary, it is shown that output signal-to-noise ratio degradation due to Brownian motion is maximum for low fractional bandwidth, high order and high quality factor RF MEMS tunable filters. Finally, a self-sustained microwave platform to detect the dielectric constant of organic liquids is presented in this dissertation. The main idea is to use a voltage- controlled negative-resistance oscillator whose frequency of oscillation varies according to the organic liquid under test. To make the system self-sustained, the oscillator is embedded in a frequency synthesizer system, which is then digitally interfaced to a computer for calculation of dielectric constant. Such a system has potential uses in a variety of applications in medicine, agriculture and pharmaceuticals.

Sintetizadores de Freqüências são circuitos que geram sinais em freqüências pré-determinadas, sendo estes sinais usados tanto na recepção como na transmissão de Rádio Freqüência. Os circuitos Sintetizadores possuem diversos blocos, dentre os quais podemos citar, osciladores controlados por tensão (VCO Voltage-Controlled Oscillator), divisores programáveis (Prescaler), comparadores de fase (DFF Detectores de Fase e Freqüência), bombas de carga (CP Charge Pump) e Filtros Passa Baixas (LPF Low Pass Filters). Em 2003 foi projetado por Angel M.G. Argüello [Ar04] um circuito Sintetizador de Freqüências com arquitetura tipo Integer-N. Este circuito, projetado para ter banda centrada em torno de 2,4 GHz e 16 canais de 4,78 MHz, foi implementado na tecnologia CMOS 0,35 µm da AMS (Austrian Micro Systems), que possui quatro níveis de metais e dois níveis de polisilício. Após testes do circuito as seguintes conclusões sobre seu funcionamento foram derivadas: o circuito funcionou qualitativamente como projetado, sintetizando 16 tons de freqüência; o ruído de fase medido ficou acima do valor desejado; a potência consumida esteve dentro dos valores previstos, porém elevada. No decorrer de 2004 foram feitas alterações no layout do circuito de Argüello com o objetivo de melhorar o ruído de fase. Estas alterações serviram como estudo preliminar para este trabalho. Dando continuidade ao desenvolvimento de Sintetizadores, em 2005 foram estudadas novas estruturas e layouts mais eficientes no tocante a ruído de fase, dando-se especial atenção às alimentações dos circuitos digitais e analógicos e ao isolamento entre os mesmos. Um novo circuito Sintetizador foi desenvolvido para aplicações em sistemas ZigBee, que operam na banda de freqüência entre 2,400 GHz a 2,485 GHz, com 16 canais de largura igual 2 à 5 MHz. Resultados de simulação sobre o circuito projetado apontaram o funcionamento adequado, com consumo de potência inferior a 32 mW para tensão de alimentação de 3,3 V. / Frequency Synthesizers are circuits that generate pre-determined frequencies, used in both radio frequency reception and transmission. The Synthesizer circuits are composed by several blocks, such as Voltage-Controlled Oscillator (VCO), Prescaler, PFD (Phase/Frequency Detector), Charge Pump (CP), and Low Pass Filters (LPF). In 2003, an Integer-N architecture Frequency Synthesizer circuit was developed by Angel M.G. Argüello [Ar04]. This circuit, designed to have a band centered around 2.4 GHz and 16 channels with a 4.78 MHz, were implemented with the 0.35 µm CMOS technology from AMS (Austrian Micro Systems), using four metal levels and two polisilicon levels. After the circuit tests, the following conclusions about its operation were derived: the designed circuit operated as expected, generating 16 tons of frequency; the phase noise stayed above of the desired value; the power consumption were within the expected values although high. During the year of 2004, several modifications in the Argüello circuit layout have been done in order to improve the phase noise. These modifications were a preliminary study to this work. Advancing in the development of Synthesizers, in 2005 new structures and more efficient layouts, in terms of noise, were studied, with special attention given to the digital and analog power supplies and their isolation. A new Synthesizer was developed for applications with the ZigBee, which operates with frequencies from 2.400 GHz to 2.485 GHz and 16 channels of 5 MHz. The simulation results pointed out the correct operation of the circuit, with power consumption lower than 32 mW for power supply of 3.3 V.

A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. The approach provides fine resolution and wide bandwidth as well as low phase noise and should find application in many contemporary communication systems. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs when operated in the second mode. For example, in an application to a P-GSM 900 system, it is capable of tuning from 890 – 915 MHz with a channel spacing of 200 kHz and shows worst case phase spurs of -100 dBc at an offset frequency of 833 kHz. Because of the low magnitude and location of the worst case spurs, the phase-locked loop filters can be designed with a wide bandwidth which in turn results in a fast settling time. A linear frequency-switching settling time (to 0.01% of frequency increments) of 128 μs is typical in the P-GSM 900 application.

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No description available.

Networked wireless sensor systems have the potential to play a major role in critical applications including: environmental monitoring of chemical/biological attacks; condition-based maintenance of vehicles, ships and aircraft; real-time monitoring of civil infrastructure including roads, bridges etc.; security and surveillance for homeland defense systems; and battlefield surveillance and monitoring. Such wireless sensor networks can provide remote monitoring and control of operations of large-scale systems using low-power, low-cost, "throw-away" sensor nodes. This thesis focuses on two aspects of wireless sensor node development: (1) post-IC assembly of nanosensor devices onto prefabricated complementary-metal-oxide-semiconductor (CMOS) integrated circuits using a technique called dielectrophoretic (DEP) assembly; and (2) design of a low-power SiGe BiCMOS multi-band ultra-wideband (UWB) transmitter for wireless communications with other nodes and/or a central control unit in a wireless sensor network. For the first part of this work, a DEP assembly test chip was designed and fabricated using the five-metal core CMOS platform technology of Motorola's HiP6W low-voltage 0.18_m Si/SiGe BiCMOS process. The CMOS chip size was 2.5mm x 2.5 mm. The required AC signal for assembling nanowires is provided to the bottom electrodes defined in the Metal 4 (M4) layer of the IC process. This signal is then capacitively coupled to the top/assembly electrodes defined in the top metal (M5) layer that is also interconnected to appropriate readout circuitry. The placement and alignment of the nanowires on the top electrodes are defined by dielectrophoretic forces that act on the nanowires. For proof of concept purposes, metallic rhodium nanowires ((length = 5μm and diameter = 250 nm) were used in this thesis to demonstrate assembly onto the prefabricated CMOS chip. The rhodium nanowires were manufactured using a nanotemplated electroplating technique. In general, the DEP assembly technique can be used to manipulate a wider range of nanoscale devices (nanowire sensors, nanotubes, etc.), allowing their individual assembly onto prefabricated CMOS chips and can be extended to integrate diverse functionalized nanosensors with sensor readout, data conversion and data communication functionalities in a single-chip environment. In addition, this technique provides a highly-manufacturable platform for the development of multifunctional wireless sensor nodes based on assembled nano-sensor devices. The resistances of the assembled nanowires were measured to be on the order of 110 Ω consistent with prior prototype results. Several issues involved in achieving successful assembly of nanowires and good electrical continuity between the nanowires and metal layers of IC processes are addressed in this thesis. The importance of chemical/mechanical planarization (CMP) technique in modern IC processes and considerations for electrical isolation of readout circuit from the assembly sites are discussed. For the second part of this work, a multi-band hopping ultrawideband transmitter was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for the multi-band PLL frequency synthesizer. The CMOS PFD provided phase tracking over a range of -2π to +2π radians. The on-chip passive loop filter was designed for a 62_ phase margin, 250 μA-charge pump output current and 4 MHz-PLL loop-bandwidth. The CMOS pseudorandom code generator provided a two-bit output that helped switch the frequency bands of the UWB transmitter. With all these components, along with a BiCMOS VCO, a CMOS charge pump and a CMOS frequency divider, the simulated PLL frequency synthesizer locked within a relatively short time of 700ns in all three design frequency bands. The die area for the multi-band UWB transmitter as laid out was 1.5 mm x 1.0 mm. Future work proposed by this thesis includes sequential assembly of diverse functionalized gas/chemical nanosensor elements into arrays in order to realize highly sensitive "electronic noses". With integration of such diverse functionalized nano-scale sensors with low-power read-out and data communication system, a versatile and commercially viable low-power wireless sensor system can be realized. / Master of Science

Osciladores Controlados por Tensão (VCOs - Voltage-Controlled Oscillators) são circuitos de grande importância em sistemas de comunicação por radiofrequência atuais. Muitos trabalhos de pesquisa recentes têm focado no desenvolvimento de VCOs para aplicações em uma faixa muito grande de frequências (isto é, suportando amplo tunning range). O desenvolvimento de VCOs com uma ampla faixa de sintonia tem motivação na abertura de bandas de frequência, que até pouco tempo estavam licenciadas apenas para usos específicos, porém agora estão também abertas para a utilização de sistemas de rádios cognitivos. A ideia é que o rádio cognitivo tenha recursos para detectar se um canal (ou faixa de frequência) está sendo usado e, em caso de o canal não estar sendo usado, o rádio cognitivo deve se reconfigurar para operar nesse canal. Desse modo, os rádios cognitivos devem possuir um alto grau de reconfigurabilidade, de forma que possam operar em uma faixa muito ampla de frequências. Esse requisito exige o uso de de VCOs com um amplo tunning range. Este trabalho apresenta um projeto completo de um LC-VCO com uma larga faixa de frequência de operação (widedand). Um amplo tunning range foi obtido a partir do chaveamento (ou programação) do valor da capacitância total do tanque-LC do VCO, gerando assim várias sub-bandas de frequência. O ganho do VCO (KVCO) manteve-se com pequenas variações para todas as subbandas de frequência, com um valor médio de 88.6MHz, sendo 112MHz e 80MHz os valores máximo e mínimo, respectivamente. O ruído de fase variou de -118.4dBc/Hz a -107.4dBc/Hz para as portadores em 3.7GHz e 8.1GHz, respectivamente, enquanto que a potência dissipada do circuito LC-VCO variou de 1.8mW a 5.6mW para todo o tunning range. Para a figura de mérito power-frequency-tunning-normalized (FOMPFTN), os valores obtidos foram na faixa 3.1dB e 11.2dB, comparáveis com a maioria dos trabalhos publicados na área. / Voltage-Controlled Oscillators (VCOs) are very important circuits in current radio frequency communication systems. Much research has been focused recently on developing wideband VCOs in CMOS. The motivation on wideband VCOs is based on the opening of frequency bands, which until recently were licensed for specific uses, for use by cognitive radio systems. The idea is that cognitive radio must have the ability to detect whether a channel (or frequency band) is being used and if the channel is not being used, the cognitive radio must reconfigure itself to operate on that channel. Thus, cognitive radios should possess a high degree of reconfigurability, so that they can operate in a very wide frequency range. This requires the use of VCOs with a wide tunning range. This work presents a complete design of a LC-VCO with a wide operating frequency range (widedand). A wide tunning range has been obtained from the switching (or programming) the value of the total capacitance of the LC-tank of the VCO, thereby generating multiple frequency sub-bands. The VCO gain (KVCO) was maintained with small variations for all frequency sub-bands, with an average value of 88.6MHz, with 80MHz and 112MHz for the minimum and maximum values, respectively. The phase noise ranged from -118.4dBc/Hz to -107.4dBc/Hz for carriers at 3.7GHz and 8.1GHz, respectively, while the power dissipated in the LC-VCO circuit ranged from 1.8mW to 5.6mW for all tunning range. For the figure of merit power-frequency-tuning-normalized (FOMPFTN), the results were in the 3.1dB to 11.2dB range, comparable to most recently published works.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

A fully integrated, fast-locking fractional-N frequency synthesizer is proposed and demonstrated in this work. In this design, to eliminate the need for large, inaccurate capacitors and resistors in a loop filter, an analog continuous-time loop filter whose performance is sensitive to process and temperature variations and aging has been replaced with a programmable digital Finite Impulse Response (FIR) filter. In addition, using the adaptive loop gain control proportional to the frequency difference, the frequency-locking time has been reduced. Also, the phase noise and spurs have been reduced by a Multi-stAge noise SHaping (MASH) controlled Fractional Frequency Detector (FFD) that generates a digital output corresponding directly to the frequency difference. The proposed frequency synthesizer provides many benefits in terms of high integration ability, technological robustness, fast locking time, low noise level, and multimode flexibility. To prove performance of the proposed frequency synthesizer, the frequency synthesizers analysis, design, and simulation have been carried out at both the system and the circuit levels. Then, the performance was also verified after fabrication and packaging.

In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototype system is pretty good which is measured as -123.2 dBc/Hz at 100 kHz offset and less than -141.3 dBc/Hz at 1 MHz offset. Made up of discrete components, the VCO used in the designed local oscillator is not integrable to frequency synthesizer which is implemented in CMOS technology. Considering technological progress, integrabilitiy of system components becomes important for designing single chip complete systems like transmitters, receivers or transceivers. Therefore considering a potential single chip transceiver production, also a CMOS voltage controlled oscillator is designed using standard TSMC 0.18um technology operating in between 2.05 GHz and 2.35 GHz . Since low phase noise is the main concern, phase noise models and phase noise reduction techniques that are derived from the models are studied. These techniques are applied to the VCO core to see the effects. Design is finalized by applying some of those techniques which are found to be noticeably effective to the core design. Finalized core operates from 2.15 GHz to 2.25 GHz and phase noise is simulated as -107.265 dBc/Hz at 100 kHz offset and -131.167 dBc/Hz at 1 MHz offset. Also oscillator has figure of merit of -185.4 at 100 kHz offset. These values show that designed core is considerably good when compared to similar designs.