The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

[pt] Esta dissertação de mestrado demonstra o princípio do funcionamento de um sistema gerador e multiplexador óptico utilizando pulsos curtos. Através do efeito de mode locked fiber ring laser pulsos curtos ópticos são gerados para taxa de repetição de 2.48 GHz ao passo que o escalonamento é atribuído ao uso de dispositivos passivos ópticos os quais compõem o conjunto experimental permitindo que a freqüência de 9.95 GHz seja atingida mediante a combinação exata das técnicas utilizadas. O coração de sistema está contido na geração e controle dos pulsos os quais determinarão a taxa de repetição em baixa freqüência e posteriormente a multiplexação através de linhas de atraso devidamente combinadas fornecerão o valor escalonado de operação de frequência. / [en] This master thesis demonstrates the principle of the functioning of an optical time domain multiplex system using short pulses. Through the effect of mode locked to fiber ring laser, optical short pulses are generated at repetition of 2.48 GHz to the step that the scheduling is attributed to the use of optic passive devices which compose the experimental setup allowing that the frequency of 9.95 GHz is reached by means of the accurate combination of the used techniques. The system heart is contained in the generation and control of the pulses which will later determine the rate of repetition in low frequency and multiplexing through lines of delay duly combined.

No description available.

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

Master of Science / Department of Electrical and Computer Engineering / Andrew Rys / Clock and data recovery (CDR) circuits form the backbone of high speed receivers. These receivers are used in various applications such as chip to chip interconnects, optical communications and backplane routing. The received data in CDR circuits are potentially noisy and asynchronous, i.e. they are not accompanied by a clock. The CDR circuit has to generate a clock from the data and then retime the data. The CDR circuit that recovers the clock and retimes the data has to remove the jitter that is accumulated during its transport through channels due to inter symbol interference (ISI). There are stringent jitter specifications defined by various communication standards that must be addressed by CDR circuits. These make the design of CDR circuits more difficult for system designers as well the circuit designer. Many parameters have to be taken into consideration while designing a CDR circuit. The problem becomes even more interesting as there are various tradeoffs in the design. As speeds of communications increase, the maximum allowable jitter decreases. Jitter in CDR circuits arises due to a lot of factors and is also dependent on the method used for clock and data recovery. In CDR circuits that use phase locked loops to recover the clock and retime the data, jitter may be caused by the metastability of sequential elements used in phase detectors. Jitter is also caused by the phase noise of the VCO used in the PLL. In CDR circuits that use the delay locked loop to recover the clock and data, jitter may be caused by the metastability of sequential elements in phase detectors as well as the quality of reference clock that is used to re-time the data. Additional effects that can cause jitter in CDR circuits include the use of spread spectrum clocking, delta sigma noise shaping performance, etc. In this thesis a non-sequential linear phase detector has been proposed which does not use any sequential elements to avoid metastability issues in phase detectors. The output jitter in a CDR circuit that uses the proposed phase detector is measured and compared to a Hogge Phase Detector [5].

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The U.S. Army’s Hardened Subminiature Telemetry and Sensor Systems (HSTSS) program has engaged the M/A-COM Corporation to work in the development of a highly accurate, crystal controlled telemetry transmitter chip set to be used in Army and other U.S. military munitions. A critical factor in this work is the operating environment of up to 100,000-g launch accelerations. To support the Army in this project, M/A-COM is developing integrated Voltage Controlled Oscillators (VCO) for L and S band, a silicon synthesizer/phase locked loop (PLL) IC, and a family of power amplifiers. Lastly, the transmitter module will be miniaturized and hardened using M/A-COM’s latest chip-onboard mixed technology manufacturing capabilities. This new chip set will provide the telemetry engineer with unprecedented design flexibility. This paper will review the overall transmitter system design and provide an overview for each functional integrated circuit.

Bakgrund: Patienter som ofta vårdas inom den psykiatriska slutenvården är patienter med psykotiska störningar, depression och patienter med risk för självmord. Tvångsåtgärder som kan förekomma på en psykiatrisk vårdavdelning kan exempelvis vara bältesläggning, tvångsmedicinering och isolering. För att en sjuksköterska ska kunna vårda dessa patienter behövs såväl kunskap som förståelse. För att axla denna roll behöver sjuksköterskor mer forskning som är fokuserad på patienters erfarenheter. Syfte: Syftet med studien var att beskriva patienters erfarenheter av sluten psykiatrisk tvångsvård samt att beskriva de inkluderade artiklarnas urvalsmetod och undersökningsgrupp. Metod: Litteraturstudien genomfördes med en beskrivande design. Studien innefattas av elva stycken kvalitativa vetenskapliga artiklar som svarar på studiens syfte. Resultat: Fem teman var grunden till beskrivningen av denna litteraturstudie: Betydelsen av relationen till vårdpersonalen, Betydelsen av information, Förståelsen av att vårdas mot sin vilja, Erfarenheter av tvångsåtgärder samt Erfarenheter av vårdmiljön. Resultatet avslutas med en beskrivning av artiklarnas urvalsmetod och urvalsgrupp. Slutsats: Patienter beskrev både bra och dåliga erfarenheter av sluten psykiatrisk tvångsvård. Viktiga aspekter som framgick enligt patienterna var: God information, god relation till vårdpersonal, förståelse samt en god vårdmiljö. Det är av stor vikt att sjuksköterskan har god kunskap om patienters erfarenheter för att kunna ge så god omvårdnad som möjligt. / Background: Patient who is treated in a locked psychiatric coercive care unit is patient with psychotic disorders, depression and patients with risk for suicide. Coercive measures that may be present in a psychiatric ward could be, for example medical restraint, forced medication and isolation. For a nurse to be able to care this patients who is in a need for good care it´s important with knowledge and understanding. To handle this role, nurses need more research and focus at the experiences of patients. Purpose: The aim of this study was to describe patient´s experience of a locked psychiatric coercive care unit. Present the selected articles' selection method and study group. Method: This is a literature study with a descriptive design. In this study eleven articles of qualitative approach are included to answer to the purpose of this study. Results: The result is based on five themes: Significance of relationship with health professionals, Significance of information, Understandning of being cared against their own will, Experience of being cared under coercion and Experience of the care environment. The last part om the result descibe the selctions method and the of the study group of the article. Conclusion: Patients described both good and bad experiences of locked psychiatric care. According to the patient important aspects was: Good information, Good Relationships with the health professionals and understanding, God care environment. It´s of great importance that the nurses have good knowledge about patients experience to be able to give such good nursing care as possible.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / M/A-COM, Inc. has previously developed a highly integrated transmitter chip set for wireless telemetry applications for the military L and S band frequencies and the commercial 2.4GHz ISM band. The original chip set is comprised of a voltage controlled oscillator (VCO), a silicon phase locked loop (PLL), and a family of power amplifiers (PA's). Using these components, M/A-COM has produced a miniature IRIG-compliant transmitter module, which has been flight-tested by the U.S. Army’s Hardened Subminiature Telemetry and Sensor System (HSTSS) program. Since the initial offering, several product enhancements have been added. The module performance has been improved by tailoring the VCO specifically for direct frequency modulation applications. In addition to improving noise performance, these enhancements have produced improved modulation linearity, decreased lock time and increased carrier stability. Modulation rates in excess of 10Mbps have been demonstrated. High efficiency power amplifiers operating at 3V have also been added to the family of amplifiers (PAE > 50%). This greatly enhanced efficiency allows higher RF power output while maintaining the same miniature form factor for the transmitter. Further, M/A-COM has added a silicon-on-sapphire PLL to the chip set, which operates at frequencies up to 3.0GHz. This paper details the enhancements to the components within the chip set, and the improvement in performance of the transmitter module. Test data is presented for the transmitter modules and individual components.

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2008. / This thesis discusses the design, development and measured results of a phase-locked loop based frequency synthesiser for X-band Doppler radar. The objective is to obtain phase noise comparable or lower than that typically achieved with direct analogue frequency synthesis techniques. To meet this objective, a theoretical study of the noise contributions of individual components of the synthesiser and their effect on the total phase noise within and outside the loop bandwidth of the PLL is performed. The effect of different phase margins on the closed-loop frequency response of the PLL, and hence the total phase noise, is investigated. Based on the results, an optimal phase-frequency detector reference frequency, loop bandwidth, adequate phase margin, and suitable components are chosen for optimal phase noise performance. The total phase noise at the output of the synthesiser is calculated and it is shown that the phase noise specification can be met. A significant part of this thesis is devoted to the design, modelling and characterisation of a frequency multiplier, as well as to a combline and interdigital bandpass filter required for the frequency synthesiser. In the first case, a piecewise linear circuit model is used to model the behaviour of the nonlinear multiplier circuit. Fourier theory is used to calculate the large-signal driving point input and output impedances of the nonlinear circuit, enabling the computation of the circuit elements for the input and output matching networks. The measured response of the frequency multiplier under various different operating conditions is presented and discussed. The design of the microwave bandpass filters is based on the theory of coupling and external quality factors. To aid in the verification and optimisation of the design, a software simulation tool is used. The presented S-parameter measurements of the filters show how well the theory matches with what is obtained in practice. The measured spectral and phase noise response of various components comprising the synthesiser, are discussed. These measurements provide insight into the response of individual components under different operating conditions and show the behaviour of important subsystems of the synthesiser. The thesis culminates in the presentation of the measured phase noise of the complete synthesiser. It is shown how well the measured phase noise correlates with the calculated phase noise. In addition, the measured spectral content and transient behaviour of the synthesiser are investigated and discussed. High power spurious components at some output frequencies are indentified and reduced. The feasibility of using the developed prototype phase-locked loop based frequency synthesiser for coherent X-band Doppler radar is discussed and demonstrated.

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012