Phased array receivers are a set of antenna elements that are capable of forming multiple simultaneous beams over a field of view. In radio astronomy, the study of deep space radio sources, a phased array feed (PAF) is placed at the focus of a large dish telescope that spatially samples the focal plane. PAFs provide an increase in the field of view as compared to the traditional single pixel horn feed, thereby increasing survey speed while maintaining low sensitivity. Phased arrays are also capable of radio frequency interference (RFI) mitigation which is useful in both radio astronomy and wireless communications when detecting signals in the presence of interferers such as satellites. Digital signal processing algorithms are used to process and analyze data provided by phased array receivers. During the commissioning of the Focal-plane L-band Array feed for the Green Bank telescope (FLAG), sensitivity consistent with an equivalent system temperature below 18 K was measured. To demonstrate the astronomical capability of the receiver, a pulsar (PSR B2011+38) was detected, and an HI source (NGC4258) was mapped with the real-time beamformer and fine channel correlator, respectively. This work also details improvements made to the software of the FLAG digital backend such as the design and implementation of an algorithm to remove scalloping ripple from the spectrum of two cascading polyphase filter banks (PFB). This work will also provide a brief introduction to a model-based beam interpolation algorithm capable of increasing spatial resolution of radio source maps as well as reducing time spent performing calibration. The development of a phased array receiver digital back end for the Office of Naval Research (ONR) is also detailed. This broadband system will be capable of communication in hostile RFI-rich environments with the aid of a real-time RFI mitigation algorithm currently implemented in software. This algorithm will be compatible with other PAF receiver systems and will enable RFI mitigation in other applications such as radio astronomy. This work will provide details on the implementation of this algorithm, the development and modification of other system software as well as full system tests of the 150 MHz bandwidth receiver have been conducted and will be shown in this document.

Phased array receivers are a set of antenna elements that are capable of forming multiple simultaneous beams over a field of view. In radio astronomy, the study of deep space radio sources, a phased array feed (PAF) is placed at the focus of a large dish telescope that spatially samples the focal plane. PAFs provide an increase in the field of view as compared to the traditional single pixel horn feed, thereby increasing survey speed while maintaining low sensitivity. Phased arrays are also capable of radio frequency interference (RFI) mitigation which is useful in both radio astronomy and wireless communications when detecting signals in the presence of interferers such as satellites. Digital signal processing algorithms are used to process and analyze data provided by phased array receivers. During the commissioning of the Focal-plane L-band Array feed for the Green Bank telescope (FLAG), sensitivity consistent with an equivalent system temperature below 18 K was measured. To demonstrate the astronomical capability of the receiver, a pulsar (PSR B2011+38) was detected, and an HI source (NGC4258) was mapped with the real-time beamformer and fine channel correlator, respectively. This work also details improvements made to the software of the FLAG digital backend such as the design and implementation of an algorithm to remove scalloping ripple from the spectrum of two cascading polyphase filter banks (PFB). This work will also provide a brief introduction to a model-based beam interpolation algorithm capable of increasing spatial resolution of radio source maps as well as reducing time spent performing calibration. The development of a phased array receiver digital back end for the Office of Naval Research (ONR) is also detailed. This broadband system will be capable of communication in hostile RFI-rich environments with the aid of a real-time RFI mitigation algorithm currently implemented in software. This algorithm will be compatible with other PAF receiver systems and will enable RFI mitigation in other applications such as radio astronomy. This work will provide details on the implementation of this algorithm, the development and modification of other system software as well as full system tests of the 150 MHz bandwidth receiver have been conducted and will be shown in this document.

Modern radar and signal processing applications require data acquisition systems capable of high-speed analog data reception and processing. These systems need to support sophisticated signal processing algorithms and reliable high-speed interfaces. The objective of this project is to develop a prototype of a state of the art data acquisition system to aid NASA’s Surface Water and Ocean Topography (SWOT) mission. The SWOT mission aims at monitoring water levels of various water bodies to predict and avoid any catastrophic events. The principal instrument is a Ka-band Radar Interferometer (KaRIN) that is used for the measurement of water levels. The collected data need to be digitized and processed using an FPGA based-data acquisition system housed in a satellite. The scope of this project involves the design, implementation and test of a high-speed printed circuit board (PCB) that serves as the prototype data acquisition system. A lot of emphasis is placed on layout design, as the PCB needs to support data rates up to three Giga samples per second. The goal of this research is to provide Jet Propulsion Laboratory (JPL), NASA with a prototype version of the high- speed acquisition system that can be integrated with the KaRIN system in future.

In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit. / Master of Science

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.

In this study we present a high-performance computing architecture and hardware acceleration strategy for a heterogeneous multi-gigabit computing system. The system architecture integrates a BeeGFS distributed file system, capable of achieving 80 Gbps of sustained write throughput across five nodes, essential for managing the high data volumes generated by a 25 high performance computer (HPC) compute cluster. To ensure operational efficiency and scalability, the tasks performed on the Linux compute cluster consisting of 30 nodes are automated using Ansible, facilitating seamless deployment, management, and updates. We present compilation strategies for a hardware accelerated Polyphase Filter Bank (PFB) channelization routine optimized for Xilinx Ultrascale+ FPGAs, capable of simultaneously processing 2048 channels per 12 input streams. This setup shows the efficiency of High Level Sysnthesis of FPGA-based signal processing in handling demanding data analysis tasks. We also present the implementation and verification of a 1.6 Gsps Direct Memory Access (DMA) transfer from DDR4 memory to a modern Radio Frequency System on Chip (RFSoC) digital to analog converter. The combination of a high-throughput file system, streamlined automation, and advanced signal processing capabilities shows these system's ability to meet the needs of complex, real-time data analysis and processing applications, advancing the field of computational research.

This work explores the application of various power amplifier design techniques for mobile communications. Several circuit configurations including class A amplifier, Doherty amplifier and power combining amplifier have been developed, which are to improve the performance of power amplifiers in terms of power added efficiency transmission power and bandwidth. In chapter 2, the cascode PA adopting tuning capacitor structure is proposed and implemented to enhance the efficiency. In chapter 3, a novel Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is introduced. Moreover, the second harmonic cancellation function of balun combining PA is analysed and verified with experimental results in chapter 4. The fully integrated cascode class A amplifier adopts RC negative feedback, which is to enhance bandwidth and input/output matching. The integrated choke inductor compensating the parasitic capacitor of transistors has very low quality factor, which decreases the efficiency of the power amplifier. To reduce the inductance value of the choke inductor, a tuning capacitor is connected in parallel with the choke inductor. As a result, the inductor resistance is reduced as well, which diminishes the power consumption induced by the resistance of the choke inductor. This proposed PA configuration is validated by simulation results with the PAE improved by 3 % at the 1 dB compression point compared to the topology without tuning capacitor. The experimental results demonstrate a PA which delivers an output power of 21.3 dBm with PAE of 21 % at the 1 dB compression point. The Doherty amplifier with 2-way Wilkinson power splitter is integrated in a 0.9 mm×1.8 mm chip. The main and peak amplifier adopt cascode configuration to improve the stability of the Doherty amplifier. To minimize the chip size, the quarter wave transmission line in the topology is replaced by π-type lumped element equivalent network. To increase the operating bandwidth, the Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is proposed. The topology consists of 3-stage RC polyphase filter, drive amplifiers, main amplifier, peak amplifier, and impedance inverter. By employing the polyphase filter, the quarter-wave transmission line at the input of the peak amplifier for compensating the phase shift of the impedance inverter is eliminated. According to the analysis of the polyphase filter prototype, the 3-stage polyphase filter is selected, and the component parameters are determined. The main amplifier and peak amplifier are using differential cascode configuration. The drive amplifier is to increase the power gain and provide proper impedance matching for the Doherty amplifier. The results demonstrate an outstanding broadband Doherty amplifier with a bandwidth of 1.8 GHz. The chip temperature rises dramatically due to the high power consumption of power amplifier. Consequently, the collector currents of the SiGe transistors are varying with the changing temperature, which deteriorates the PA performance. In the improved 3-stage PPF Doherty design, the bias voltages of the transistors in the first version 3-stage PPF Doherty amplifier are replaced by reference currents feeding through bias circuits. With current sources providing bias current to the transistors, the performance of the improved Doherty amplifier is enhanced. The power combining PAs are constructed on FR-4 PCB boards using discrete components. The single ended power amplifier in the power combining PA is built with high linearity HEMT transistor. The balun combining PA has an advantage of second harmonic cancellation, which is validated by both analysis and measurements. Moreover, power combining PAs with 2-way transmission line and lumped element Wilkinson power divider are designed. The transmission lines in these designs are analyzed using EM simulation tool and verified with testing structures on PCB boards.