No description available.

Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

No description available.

This thesis aims to design and build a power electronics system for the rectification and control of magnetization currents in synchronous generators with rotating exciters.The rotating exciter provides three-phase AC while the generator rotor needs DC with a high degree of control. The system needs to be able to rectify the three-phase AC to a stable DC without unwanted harmonic content, neither on the DC or the AC side. For control purposes it is also important that the current in the rotor can be changed very swiftly, preferably by several amperes during a single revolution ofthe machine.The system of choice is a synchronous rectifier bridge consisting of six MOSFET switches operated using the Space vector pulse width modulation (SVPWM) algorithm. This method gives a stable and controllable DC voltage while it keeps the harmonic content of the input currents at a minimum. However the DC voltage will always be higher than the peak line-to-line voltage from the exciter. To be able to lower the voltage below this value a Buck-converter is placed after the rectifier bridge.To gain a higher degree of control of the current density in the rotor windings the windings have been subdivided into three parts. To provide individual control of the current in the three rotor parts each part have been outfitted with a Push and Pull H-bridge.The proposed system has been both simulated using MATLAB Simulink and built and tested in the laboratory with satisfactory results. / I detta examensarbete presenteras ett kraftelektroniksystem för förbättrad kontroll av magnetiseringsstömmar i vattenkraftsgeneratorer som är utrustade med roterande matare.Generatorer används för att konvertera energi från rörelseenergi till elektrisk energi. Detta görs genom att man utsätter spolar för varierande magnetfält; då induceras spänning i spolarna. I vattenkraftsgeneratorer används oftast stora elektromagneter placerade i en rotor för att skapa dessa magnetfält. För att magnetisera elektromagneterna behövs ström som på något sätt måste överföras mellan den statiska och den roterande sidan i generatorn. Traditionellt görs detta med hjälp av släpringar och kolborstar som genom mekanisk kontakt överför elektriciteten. En roterande matare kan beskrivas som en liten generator som har sina elektriska utgångar på den roterande sidan istället för på den statiska sidan. Genom att placera en roterande matare på samma axel som den stora generatorn kan man istället alstra den elektricitet som behövs för att magnetisera generatorn direkt på den roterande sidan. Däregenom undviks många problem som är associerade med lösningen med släpringar.Den roterande mataren ger dock växelström medan magnetiseringsströmmen måste vara likström. Det är här kraftelektroniken kommer in i bilden. Det finns flera sätt att åstadkomma likriktning av ström. I det här projektet har ett fullständigt aktivt system byggts. Systemet är uppbyggt av transistorer av MOSFET typ och kan kontrolleras trådlöst med hjälp av Bluetoothteknik. Systemet ger full kontroll över strömmar och spänningar både på växelströmssidan och på likströmssidan och ska användas till en testgenerator på avdelningen för ellära vid Uppsala Universitet. Där ska den utökade kontroll som systemet ger förutsättningar till användas för att undersöka hur den här typen av system kan optimera de magnetiska krafterna inuti generatorn. En sådan optimering kan minska vibrationerna i generatorn och därigenom minska slitaget på lager och andra delar i maskinen.

Thesis (MScEng)--Stellenbosch University, 2012 / ENGLISH ABSTRACT: The class-D audio power amplifier has found widespread use in both the consumer and professional audio industry for one reason: efficiency. A higher efficiency leads to a smaller and cheaper design, and in the case of mobile devices, a longer battery life. Unfortunately, the basic class-D amplifier has some serious drawbacks. These include high distortion levels, a load dependent frequency response and the potential to radiate EMI. Except for EMI, the aforementioned issues can be mitigated by the proper implementation of global negative feedback. Negative feedback also has the potential to indirectly reduce EMI, since the timing requirements of the output devices can be relaxed. This thesis discusses the design of a clocked analogue controlled pulse-width modulated class-D audio amplifier with global negative feedback. The analogue control loop is converted to the z-domain by modelling the PWM comparator as a sampling operation. A method is implemented that improves clip recovery and ensures stability during over-modulation. Loop gain is shaped to provide a high gain across the audio band, and ripple compensation is implemented to minimize the negative effect of ripple feedback. Experimental results are presented. / AFRIKAANSE OPSOMMING: Die klas-D klankversterker geniet wydverspreide gebruik in beide die verbruiker en professionele oudio industrie vir een rede: benuttingsgraad. ’n Hoër benuttingsgraad lei tot ’n kleiner en goedkoper ontwerp, en in die geval van draagbare toestelle, tot langer batterylewe. Ongelukkig het die basiese klas-D klankversterker ernstige tekortkominge, naamlik hoë distorsievlakke, ’n lasafhanklike frekwensierespons en die vermoë om EMI te genereer. Behalwe vir EMI kan hierdie kwessies deur die korrekte toepassing van globale negatiewe terugvoer aangespreek word. Negatiewe terugvoer het ook die potensiaal om EMI indirek te verminder, aangesien die tydvereistes van die skakel stadium verlaag kan word. Hierdie tesis bespreek die ontwerp van ’n geklokte analoog-beheerde pulswydte-modulerende klas-D klankversterker met globale negatiewe terugvoer. Die analoogbeheerlus word omgeskakel na die z-vlak deur die PWM vlakvergelyker as ’n monster operasie te modelleer. ’n Metode word geïmplementeer wat die stabiliteit van die lus verseker tydens oormodulasie. Die lusaanwins word gevorm om ’n hoë aanwins in die oudioband te verseker en riffelkompensasie word geïmplementeer om die negatiewe effek van terugvoerriffel teen te werk. Eksperimentele resultate word voorgelê.

Power electronics have a significant role in modern electrical devices, for instance, hybrid electric vehicles. Power electronics are the technology in between the source and the load circuits and can convert the power from dc to ac or from dc to ac. There are also many types of dc-dc converters, like such as boost and buck converters, which exhibit switching ripple behavior. A boost converter increases the output voltage (with respect to the input voltage) and reduces the output current. A buck converter decreases the output voltage and increases the output current. Many models are used to predict the behavior of the boost and buck converters. The detailed (DET), state-space averaged (SSA), and generalized averaging method (GAM) models are capable of predicting the average behavior of dc-dc converters. For DET and GAM models, the rippling behavior can also be predicted. These models differ in terms of required run time, existence of constant equilibrium points, and accuracy. The DET model has a long run time and does not have constant equilibrium, but it is very accurate. The SSA technique is a mathematical and time-invariant model that capable of describing the behavior of a dc-dc boost converters. It can derive the small signal ac equations of a switching converter and is used to illustrate the average behavior of any linear or nonlinear system in converters. The SSA does not take extensive runtime simulation and has constant equilibrium points, and can be applied to continuous, discrete and sample data systems. The GAM model can predict the average and ripple behavior in power electronic systems and has constant equilibrium and fast run time. However, it has a numerical stability issue. The integrator stabilized multifrequency averaging (ISMFA) model is employed to solve the stability issue in the GAM model, but it is a complicated dynamic method and has restrictions in its process. In the present study, a simplified but stable GAM model is introduced to predict the average and ripple behavior of boost dc-dc converters and to overcome the limitations of other methods. In this work, the stabilized GAM model has been used for a dc-dc boost converters. The stability of the proposed model is analyzed. The performance of the improved GAM model is compared with the DET, SSA, and GAM models. The results show that the stabilized GAM model is stable with the additional poles created by the GAM assignable by parameter choice. The new GAM model predicts the same results as the existing GAM method without the underlying stability concerns. The stabilized GAM model exhibits constant ii equilibrium point and requires significantly lower run times than the DET model, but it is also able to predict the ripple performance of the converter. The stabilized GAM model does not take a long run time, is less complicated, has fewer restrictions, has constant equilibrium and internal stability, and has more straightforward implementation than other models, like the ISMFA model. It represents a suitable alternative to DET models when high accuracy simulations are desired without long simulation run times.

<p>With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.</p><p>Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).</p>

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches. Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains. A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses. The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives. / Power Engineering and Power Electronics

Switching mode DC/DC converters are critical building blocks in portable devices and hence their power efficiency, accuracy and cost are a major issue. The primary focus of this thesis is to address these critical issues.This thesis focuses on the different methods of feedback control loop which are employed in the switching mode DC/DC converters such as voltage mode control and current mode control. It also discusses about the structure of buck converter and tries to find an efficient solution for stepping-down the DC voltage level in ultra-low power applications. Based on this analysis, a 20 MHz voltage mode DC/DC buck converter with an on-chip compensated error amplifier in 65 nm CMOS process is designed and implemented.The power efficiency has been improved by sizing the power switches to have a low parasitic output and gate capacitances to reduce the capacitive and gate-drive losses. Also the error amplifier biasing current is chosen a small value (12.5 μA) to reduce the power dissipations in the control loop of the system. The maximum 84% power efficiency is achieved at 1.1 V to 500 mV conversion, above 81% efficiency can be achieved at load current from 0.5 mA to 1.26 mA. Due to wide bandwidth error amplifier and proper compensation network the fast transient response with settling time around 45 μs is achieved.