With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.

The objective of the proposed research is to develop solutions for High-Performance Low-Cost Passives for Radar, Identification, and Communication Applications up to mm-Wave Frequencies. This research will bring to the table potential solutions that will meet three main requirements: small size (or low weight), high performance, and low cost. This research embarks on antenna design and development for passive RFID tags on LCP substrates, and then a transition towards lower cost modules investigates and explores the possibilities of using paper as RF substrates with inkjet printing as a low cost fabrication technology. Modules such as dual band antenna for Wifi frequencies (2.4 GHz and 5 GHz) and UWB (up to 10GHz) on paper substrate using inkjet printing are presented. This work then bridges into developing higher frequency modules. These include: highly selective filter design on LCP for X-band Radar application to be used as a benchmark for an easy adjustment for higher frequencies, and antenna modules LCP using inkjet printing for communication such as mm-Wave WLAN or WPAN. A transition into mm-Wave Modules then takes place for the general realization of low-cost high-performance mm-Wave modules and more specifically the low cost automotive radar. After proposing an architecture for integrated mm-Wave module, this work then investigates 2D/3D interconnections (and their integration with antennas) on LCP using conventional etching design guidelines up to 100GHz. Antenna arrays that are implemented with phase shifters for beam steering are then designed using edge fed and multilayer technology. Furthermore, crosstalk reductions for highly dense transmission lines are analyzed via simulations for the optimum performance and space saving of such mm-Wave modules such as the IC interface where space restrictions are strictly enforced.

With higher frequencies now being used in RFID systems, antennas are becoming much smaller resulting in more space on tags that can be used for innovative array designs to harvest more wireless energy. This master's thesis outlines and details a new methodology for designing and simulating the staggered pattern charge collector, a technique to improve harvesting wireless energy. Staggered pattern charge collectors enable RFID tag's to produce a higher DC voltage from a charge pump circuit by creatively using multiple arrays to increase the antenna power conversion gain without limiting the half power beamwidth. This thesis discusses the basics of patch antennas and charge pumps as well as an optimization technique for the staggered pattern array by maximizing integrated power conversion gain (IPCG). An example of a staggered pattern charge collector is fully specified from design through simulation, in preparation for fabrication. This methodology allows for the staggered pattern charge collectors to be designed, simulated, and fabricated quickly and effectively.

Dans le domaine de la chaîne logistique, nous constatons des besoins croissants d'information et d'interactions entre produits, processus et clients, et ceci durant le cycle de vie du produit. Cela entraîne le besoin, au niveau du produit, de nouvelles capacités de communication, de gestion de l'information, de perception et d'action avec son environnement physique. Ces besoins ont engendré le concept de produit ou objet communicant. Un produit avec ces nouvelles capacités pourra interagir avec d'autres entités physiques ou informationnelles dans son environnement et apporter des transformations significatives sur la gestion de la chaîne logistique. Le travail présenté dans cette thèse vise à analyser et contribuer à appliquer la notion d'objet communicant aux produits physiques dans le domaine de la chaîne logistique. L'approche proposée considère un produit comme un demandeur ou un fournisseur de services. La méthodologie proposée de gestion des produits communicants s'appuie sur la caractérisation d'une architecture de services ambiants devant permettre de gérer les services d'un produit d'une façon automatique et ubiquiste. Nous avons choisi l'architecture UPnP pour gérer les services des objets communicants. La communication directe avec le produit est supportée par les méthodes d'identification automatique RFID. Nous nous sommes appuyés sur le formalisme standard de modélisation UML afin de modéliser les interactions et les services associés à un produit physique. Comme résultat, nous avons élaboreé des démonstrateurs de laboratoire validant la faisabilité de notre proposition méthodologique de gestion de la chaîne logistique par les objets communicants.

Presented is a radiometric sensor and associated electromagnetic propagation models, developed to facilitate non-invasive core body temperature extraction. The system has been designed as a close-proximity sensor to detect thermal emissions radiated from deep-seated tissue 1 cm – 3 cm inside the human body. The sensor is intended for close proximity health monitoring applications, with potential implications for deployment into the improved astronaut liquid cooling garment (LCG). The sensor is developed for high accuracy and resolution. Therefore, certain design issues that distort the close proximity measurement have been identified and resolved. An integrated cavity-backed slot antenna (CBSA) is designed to account for antenna performance degradation, which occurs in the near field of the human body. A mathematical Non-Contact Model (NCM) is subsequently used to correlate the observed brightness temperature to the subsurface temperature, while accounting for artifacts induced by the sensor’s remote positioning from the specimen. In addition a tissue propagation model (TPM) is derived to model incoherent propagation of thermal emissions through the human body, and accounts for dielectric mismatch and losses throughout the intervening tissue layers. The measurement test bed is comprised of layered phantoms configured to mimic the electromagnetic characteristics of a human stomach volume; hence defines the human core model (HCM). A drop in core body temperature is simulated via the HCM, as the sensor monitors the brightness temperature at an offset distance of approximately 7 mm. The data is processes through the NCM and TPM; yielding percent error values < 3%. This study demonstrates that radiometric sensors are indeed capable of subsurface tissue monitoring from the near field of the body. However, the following components are vital to achieving an accurate measurement, and are addressed in this work: 1) the antenna must be designed for optimum functionality in close proximity to biological media; 2) a multilayer phantom model is needed to accurately emulate the point of clinical diagnosis across the tissue depth; 3) certain parameters of the non-contact measurement must be known to a high degree of accuracy; and 4) a tissue propagation model is necessary to account for electromagnetic propagation effects through the stratified tissue.

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In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers. / A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations. / The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA control functions, it is demonstrated that the method is better positioning GaAs HBT technologies, which are known to offer very competitive RF performances but inherently have limited integration capabilities. / Finally, an analytical approach for the evaluation of inter-modulation distortion (IMD) in envelope feedback architectures is introduced, and the proposed design equations and methodology for IMD analysis may prove very helpful for theoretical analyses, for simulation tasks, and for experimental work.

The Internet of Things paradigm establishes interaction and communication with a huge amount of actors. The concept is not a new-from-scratch one; actually, it combines a vast number of technologies and protocols and surely adaptations of pre-existing elements to offer new services and applications. One of the key technologies of the Internet of Things is the Radio Frequency Identification just abbreviated RFID. This technology proposes a set of solutions that allow tracking and tracing persons, animals and practically any item wirelessly. Considering the Internet of Things concept, multiple technologies need to be linked in order to provide interactions that lead to the implementation of services and applications. The challenge is that these technologies are not necessarily compatible and designed to work with other technologies. Within this context, the main objective of this thesis is to design a heterogeneous framework that will permit the interaction of diverse devices such as RFID, sensors and actuators in order to provide new applications and services. For this purpose in this work, our first contribution is the design and analysis of an integration architecture for heterogeneous devices. In the second contribution, we propose an evaluation model for RFID topologies and an optimization tool that assists in the RFID network planning process. Finally, in our last contribution, we implemented a simplified version of the framework by using embedded hardware and performance metrics are provided as well as the detailed configuration of the test platform

In recent years, tremendous growth of the wireless market can be defined through the following words: smartphone and high-data rate wireless communication. This situation gives new challenges to RF power amplifier design, which includes high-efficiency, multi-band operation, and robustness to antenna mismatch conditions. In addition to these issues, the industry and consumers demand a low-cost small-sized wireless device. A fully integrated single-chip CMOS transceiver is the best solution in terms of cost and level of integration with other functional blocks. Therefore, the effective approaches in a CMOS process for the abovementioned hurdles are highly desirable. In this dissertation, the new challenges are overcome by introducing adaptability to a CMOS power amplifier. Meaningful achievements are summarized as follows. First, a new CMOS switched capacitor structure for high power applications is proposed. Second, a dual-mode CMOS PA with an integrated tunable matching network is proposed to extend battery lifetime. Third, a switchless dual-band matching structure is proposed, and the effectiveness of dual-band matching is demonstrated with a fully-integrated CMOS PA. Lastly, a reconfigurable CMOS PA with an automatic antenna mismatch recovery system is presented, which can maintain its original designed performance even under various antenna mismatch conditions. Conclusively, the research in this dissertation provides various solutions for new challenges of advanced mobile terminals.