The process control domain is intrinsically complex and dynamic. It has proved to be difficult to construct and maintain process control systems under the traditional software development methodologies. Object Orientation is the latest paradigm in software development. The reason for its widespread acceptance is that it allows the application of the principles of hierarchical structuring and component abstraction which is essential in building large systems. It also promotes component reusability which makes systems easier to maintain and modify. For the process control domain, these are important benefits. Furthermore, most process control systems have physical devices which can be modeled naturally as objects with the timing and performance issues of each object directly addressed. A Target System Reference Model which addresses various aspects of the process control domain is proposed within this dissertation. The objective is to provide a frame of reference within which a process control system can function. / Computing / M. Sc. (Computer Science)

Thesis is focused on management of business informatics. The aim of this thesis is to develop Reference management model for managing business informatics and to integrate this reference model into ITGPM Reference management model for managing business informatics. Within an analytical part is reviewed current situation in the field of managing economics of business informatics as well as managing economics out of business informatics. Attention is paid to costs in busi-ness informatics, their classification, categorisation and their management. Very important part is analysis of methods for cost management thought various types of calculations and especially thought ABC methods. The principles of these methods are applied in the design of the Reference model. Further are solved questions of business informatics effect, their categorisations, classification, definition of their attributes and also their management. Development of this field is an important part of this thesis. The main part of the thesis contains the Business informatics management Reference model design. This design contains identification of the most important metrics of measuring business informatics, dimen-sions used for analysis of proposed metrics and relationships between metrics and dimensions. An impor-tant part is also a presentation level design and definition of condition that should be fulfilled, if the pres-entation level should be beneficial to final users. The main part also contains designed method for imple-mentation of the Reference model into a company. Application parts are devoted to preparation of a pilot application based on the Reference model design developed in the main part of the thesis. Designed Reference model for managing business informatics is adapted according to the needs, requests and characteristics of the company in which this pilot application is implemented. In these parts are also verified designs, processes and methods designed in the first and second part of this thesis, so there are verified possibilities of adaption of the designed model to the requests of the target company, adaption of the pilot application to the target environment including data level, ELT procedures and presentation level. In application part of the thesis is verified correctness of the designed implantation methodology into the company.

A verificação funcional é o conjunto de tarefas destinado a descobrir erros gerados durante o projeto de circuitos integrados, e representa um importante desafio ao influenciar fortemente a eficiência do ciclo inteiro de produção. Estima-se que até 80% dos custos totais de projeto são devidos à verificação, tornando esta atividade o gargalo principal para reduzir o time-to-market. Tal problemática tem provocado a aparição de diversas estratégias para diminuir o esforço, ou para aumentar a capacidade de cobertura da verificação. Por um lado existe a simulação, que permite descobrir um número razoável de erros de projeto; porém, a lentidão da simulação de descrições RTL torna mínima a cobertura real de estados. Por outro lado, os métodos formais de verificação fornecem alta cobertura de estados. Um deles é a checagem de modelos, que checa a validade de um conjunto de propriedades para todos os estados do projeto sob verificação. No entanto, esta técnica padece do problema de explosão de estados, e da dificuldade de especificar um conjunto robusto de propriedades. Outra alternativa formal é a checagem de equivalência que, ao invés de verificar propriedades, compara o projeto com um modelo de referência. No entanto, a checagem de equivalência tradicional é aplicável, unicamente, a descrições no mesmo nível de abstração, e com interfaces idênticas. Como fato importante, não foram encontrados registros na literatura de sobre a verificação formal de descrições RTL, considerando ambos os aspectos computacionais (presentes no modelo de referência) e de comunicação às interfaces (provenientes da especificação funcional de protocolo). Neste trabalho apresenta-se uma metodologia de verificação formal, através do uso de técnicas de checagem de equivalência para determinar a validade de uma implementação em RTL, comparando-a com um modelo de referência em alto nível, e com um modelo formal do protocolo de comunicação. Para permitir tal checagem, a metodologia baseia-se no conceito de sequências de estados, ao invés de estados individuais como na checagem de equivalência tradicional. As discrepâncias entre níveis diferentes de abstração são consideradas, incluindo alfabetos diferentes, mapeamento entre estados, e dessemelhanças temporais. A caracterização e solução do problema são desenvolvidas através de um quadro teórico, onde se apresentam conceitos, e definições, cuja validade é provada formalmente. Uma ferramenta para aplicação prática da metodologia foi desenvolvida e aplicada sobre diferentes tipos de descrições RTL, escritas nas linguagens VHDL e SystemC. Os resultados demonstram efetividade e eficiência na verificação formal de circuitos digitais que incluem, mas não se limitam à correção de erros, encriptação, processamento de imagens, e funções matemáticas. Também, evidencia-se a capacidade da ferramenta para descobrir erros de tipo combinatório e sequencial injetados propositalmente, relacionados com a funcionalidade do modelo de referência, assim como, com a da especificação do protocolo de comunicação, dentro de tempos e número de iterações praticáveis em casos reais. / Functional verification is the group of tasks aiming the discovery of bugs created during integrated circuit design, and represents an important challenge by its strong influence on efficiency throughout production cycles. As an estimative, up to 80% of the whole design costs are due to verification, which makes verification the greatest bottleneck while attempting to reduce time-to-market. Such problem has given rise to a series of techniques to reduce the effort, or to increase verification coverage capability. On the one side, simulation allows finding a good number of bugs, but it is still far from reaching high state coverage because of RTL cycle-accurate slowness. On the other side, formal approaches supply high state coverage. Model checking, for instance, checks the validness of a set of properties for all designs states. However, a strong disadvantage resides in defining and determining the quality of the set of properties to verify, not to mention state explosion. Sequential equivalence checking, which instead of checking properties compares the design with a reference model. Nevertheless, traditionally it can only be applied between circuit descriptions where a one-to-one correspondence for states, as well as for memory elements, is expected. As a remarkable issue, no works were found in literature that dealt with formal verification of RTL designs, while taking care of both computational aspects, present in the high-level reference model, and interface communication aspects, which proceed from the protocol functional specification. This work presents a formal verification methodology, which uses equivalence checking techniques, to validate RTL descriptions through direct comparison with a high-level reference model, and with formal model of the communication protocol. It is based on extracting and comparing complete sequences of states, instead of single states as in traditional equivalence checking, in order to determine if the design intention is maintained in RTL implementation. The natural discrepancies between system level and RTL code are considered, including non-matching interface and memory elements, state mapping, and process concurrency. For the complete problem characterization and solution, a theoretical framework is introduced, where concepts and definitions are provided, and whose validity is formally proved. A tool to apply systematically the methodology was developed and applied on different types of RTL descriptions, written in VHDL and SystemC languages. The results show that the approach may be applied effectively and efficiently to verify formally digital circuits that include, but are not limited to error correction, encryption, image processing, and math functions. Also, evidence has been obtained about the capacity of the tool to discover both combinatory and sequential bugs injected on purpose, related with computational and protocol functionalities, on real scenarios.

A verificação funcional é o conjunto de tarefas destinado a descobrir erros gerados durante o projeto de circuitos integrados, e representa um importante desafio ao influenciar fortemente a eficiência do ciclo inteiro de produção. Estima-se que até 80% dos custos totais de projeto são devidos à verificação, tornando esta atividade o gargalo principal para reduzir o time-to-market. Tal problemática tem provocado a aparição de diversas estratégias para diminuir o esforço, ou para aumentar a capacidade de cobertura da verificação. Por um lado existe a simulação, que permite descobrir um número razoável de erros de projeto; porém, a lentidão da simulação de descrições RTL torna mínima a cobertura real de estados. Por outro lado, os métodos formais de verificação fornecem alta cobertura de estados. Um deles é a checagem de modelos, que checa a validade de um conjunto de propriedades para todos os estados do projeto sob verificação. No entanto, esta técnica padece do problema de explosão de estados, e da dificuldade de especificar um conjunto robusto de propriedades. Outra alternativa formal é a checagem de equivalência que, ao invés de verificar propriedades, compara o projeto com um modelo de referência. No entanto, a checagem de equivalência tradicional é aplicável, unicamente, a descrições no mesmo nível de abstração, e com interfaces idênticas. Como fato importante, não foram encontrados registros na literatura de sobre a verificação formal de descrições RTL, considerando ambos os aspectos computacionais (presentes no modelo de referência) e de comunicação às interfaces (provenientes da especificação funcional de protocolo). Neste trabalho apresenta-se uma metodologia de verificação formal, através do uso de técnicas de checagem de equivalência para determinar a validade de uma implementação em RTL, comparando-a com um modelo de referência em alto nível, e com um modelo formal do protocolo de comunicação. Para permitir tal checagem, a metodologia baseia-se no conceito de sequências de estados, ao invés de estados individuais como na checagem de equivalência tradicional. As discrepâncias entre níveis diferentes de abstração são consideradas, incluindo alfabetos diferentes, mapeamento entre estados, e dessemelhanças temporais. A caracterização e solução do problema são desenvolvidas através de um quadro teórico, onde se apresentam conceitos, e definições, cuja validade é provada formalmente. Uma ferramenta para aplicação prática da metodologia foi desenvolvida e aplicada sobre diferentes tipos de descrições RTL, escritas nas linguagens VHDL e SystemC. Os resultados demonstram efetividade e eficiência na verificação formal de circuitos digitais que incluem, mas não se limitam à correção de erros, encriptação, processamento de imagens, e funções matemáticas. Também, evidencia-se a capacidade da ferramenta para descobrir erros de tipo combinatório e sequencial injetados propositalmente, relacionados com a funcionalidade do modelo de referência, assim como, com a da especificação do protocolo de comunicação, dentro de tempos e número de iterações praticáveis em casos reais. / Functional verification is the group of tasks aiming the discovery of bugs created during integrated circuit design, and represents an important challenge by its strong influence on efficiency throughout production cycles. As an estimative, up to 80% of the whole design costs are due to verification, which makes verification the greatest bottleneck while attempting to reduce time-to-market. Such problem has given rise to a series of techniques to reduce the effort, or to increase verification coverage capability. On the one side, simulation allows finding a good number of bugs, but it is still far from reaching high state coverage because of RTL cycle-accurate slowness. On the other side, formal approaches supply high state coverage. Model checking, for instance, checks the validness of a set of properties for all designs states. However, a strong disadvantage resides in defining and determining the quality of the set of properties to verify, not to mention state explosion. Sequential equivalence checking, which instead of checking properties compares the design with a reference model. Nevertheless, traditionally it can only be applied between circuit descriptions where a one-to-one correspondence for states, as well as for memory elements, is expected. As a remarkable issue, no works were found in literature that dealt with formal verification of RTL designs, while taking care of both computational aspects, present in the high-level reference model, and interface communication aspects, which proceed from the protocol functional specification. This work presents a formal verification methodology, which uses equivalence checking techniques, to validate RTL descriptions through direct comparison with a high-level reference model, and with formal model of the communication protocol. It is based on extracting and comparing complete sequences of states, instead of single states as in traditional equivalence checking, in order to determine if the design intention is maintained in RTL implementation. The natural discrepancies between system level and RTL code are considered, including non-matching interface and memory elements, state mapping, and process concurrency. For the complete problem characterization and solution, a theoretical framework is introduced, where concepts and definitions are provided, and whose validity is formally proved. A tool to apply systematically the methodology was developed and applied on different types of RTL descriptions, written in VHDL and SystemC languages. The results show that the approach may be applied effectively and efficiently to verify formally digital circuits that include, but are not limited to error correction, encryption, image processing, and math functions. Also, evidence has been obtained about the capacity of the tool to discover both combinatory and sequential bugs injected on purpose, related with computational and protocol functionalities, on real scenarios.

Submitted by Joana Azevedo (joanad@id.uff.br) on 2017-08-22T19:01:56Z No. of bitstreams: 1 Dissert José Francisco Penido Xavier.pdf: 2135252 bytes, checksum: cb7d34022557de01bf39c24cbf92c593 (MD5) / Approved for entry into archive by Biblioteca da Escola de Engenharia (bee@ndc.uff.br) on 2017-09-04T16:20:18Z (GMT) No. of bitstreams: 1 Dissert José Francisco Penido Xavier.pdf: 2135252 bytes, checksum: cb7d34022557de01bf39c24cbf92c593 (MD5) / Made available in DSpace on 2017-09-04T16:20:18Z (GMT). No. of bitstreams: 1 Dissert José Francisco Penido Xavier.pdf: 2135252 bytes, checksum: cb7d34022557de01bf39c24cbf92c593 (MD5) Previous issue date: 2017-01-03 / As Instituições Públicas de Ensino necessitam de métodos, técnicas e ferramentas gerenciais para auxiliar na gestão de seus processos. O Governo implementou um modelo de excelência em Gestão Pública para contribuir com a melhoria da capacidade de governança e governabilidade das estruturas executivas que deve ser modelado de acordo com as suas premissas. A partir da percepção da necessidade de mudanças na gestão do Cefet/RJ, Campus Maracanã, responsável pelo ensino e pesquisa nas áreas do ensino médio/técnico, tecnológico e superior, esta dissertação tem por objetivo propor um modelo de gestão organizacional baseado nos modelos de referência da qualidade e excelência e Gespública com a finalidade de investigar e caracterizar os elementos da atual gestão do Cefet-RJ através da abordagem do estudo de caso, com a utilização de entrevistas, análise de documentos e questionários realizados com a comunidade. Identificou-se que o modelo de gestão da instituição estudada caracteriza-se como misto, pois tanto o sistema de gestão burocrático quanto o colegiado são observados no estudo. A construção do Meta-Modelo ocorrerá com a integração de diferentes modelos de referência condicionado a uma abordagem sintética e compreensiva, especificando os componentes dos requisitos do Artefato. A escolha da abordagem pelo conceito de Design Science pretende desenvolver soluções que tragam melhorias para a gestão atual, resolvendo problemas que com a criação do artefato que está na interface entre o conceitual e o praticado. Acredita-se, portanto, que o artefato modelo é capaz de promover uma cultura de melhoria contínua do gerenciamento dos processos internos e a análise da aderência da gestão do Cefet-RJ ao artefato conceitual, que é um conjunto de proposições que expressam a relação entre os elementos, formando os requisitos. A pesquisa foi desenvolvida a partir do referencial teórico-conceitual adquirido com um estudo exploratório que posteriormente tornou-se a base para o desenvolvimento de um Meta-Modelo que promoveu o destaque da fragilidade do modelo de gestão atual praticado pela instituição de ensino analisada e as características principais que determinaram a aderência ou não aderência aos requisitos apresentados como solução para a melhoria do processo de gestão para a qualidade com excelência em um processo de ensino, bem como a apresentação de uma proposta sugestiva para a implantação e implementação do Artefato. Desta forma, obteve-se como conclusão que não existe aderência significativa do modelo de gestão praticado com o Meta-Modelo desenvolvido com base na pesquisa. A partir deste resultado, acredita-se que se aplicado, o modelo proposto trará benefícios para a gestão, pois, promoverá soluções quanto aos problemas gerados por procedimentos inadequados que não são os melhores para a execução das atividades que compõem o processo de gestão de uma instituição pública de ensino. Por fim, este trabalho apresenta o artefato modelo e também sugestões para pesquisas posteriores acerca do tema abordado. / The Public Educational Institutions need methods, techniques and management tools to assist in the management of their processes. The Government has implemented a model of excellence in Public Management to contribute to the improvement of the governance and governance capacity of executive structures that must be shaped according to its premises. Campus Maracanã, responsible for teaching and research in the areas of secondary / technical, technological and higher education, this dissertation aims to propose a model of organizational management based on the models of Reference of quality and excellence and Gespública with the purpose of investigating and characterizing the elements of the current management of Cefet-RJ through the approach of the case study, with the use of interviews, document analysis and questionnaires conducted with the community. It was identified that the management model of the studied institution is characterized as mixed, since both the bureaucratic and collegiate management system are observed in the study. The construction of the Meta-Model will occur with the integration of different reference models conditioned to a synthetic and comprehensive approach, specifying the components of the requirements of the Artifact. The choice of approach by the concept of Design Science aims to develop solutions that bring improvements to the current management, solving problems that with the creation of the artifact that is at the interface between the conceptual and the practiced. It is believed, therefore, that the model artifact is capable of promoting a culture of continuous improvement of the management of internal processes and the analysis of the adherence of the Cefet-RJ management to the conceptual artifact, which is a set of propositions that express the relation between The elements, forming the requirements. The research was developed from the theoretical-conceptual framework acquired with an exploratory study that later became the basis for the development of a Meta-Model that promoted the highlight of the fragility of the current management model practiced by the analyzed teaching institution and the Main characteristics that determined the adherence or non-adherence to the requirements presented as solution for the improvement of the management process for quality with excellence in a teaching process, as well as the presentation of a suggestive proposal for the implementation and implementation of the Artifact. Thus, it was concluded that there is no significant adherence of the management model practiced with the Meta-Model developed based on the research. The results obtained with the analysis of the data demonstrate that if applied, the proposed model will bring benefits to the management, including to define the procedures conditioning the operations to the appropriate requirements to the management model of a public educational institution that has its peculiarities. Finally, this paper presents the model artifact and also suggestions for further research on the subject. / The Public Educational Institutions need methods, techniques and management tools to assist in the management of their processes. The Government has implemented a model of excellence in Public Management to contribute to the improvement of the governance and governance capacity of executive structures that must be shaped according to its premises. Campus Maracanã, responsible for teaching and research in the areas of secondary / technical, technological and higher education, this dissertation aims to propose a model of organizational management based on the models of Reference of quality and excellence and Gespública with the purpose of investigating and characterizing the elements of the current management of Cefet-RJ through the approach of the case study, with the use of interviews, document analysis and questionnaires conducted with the community. It was identified that the management model of the studied institution is characterized as mixed, since both the bureaucratic and collegiate management system are observed in the study. The construction of the Meta-Model will occur with the integration of different reference models conditioned to a synthetic and comprehensive approach, specifying the components of the requirements of the Artifact. The choice of approach by the concept of Design Science aims to develop solutions that bring improvements to the current management, solving problems that with the creation of the artifact that is at the interface between the conceptual and the practiced. It is believed, therefore, that the model artifact is capable of promoting a culture of continuous improvement of the management of internal processes and the analysis of the adherence of the Cefet-RJ management to the conceptual artifact, which is a set of propositions that express the relation between The elements, forming the requirements. The research was developed from the theoretical-conceptual framework acquired with an exploratory study that later became the basis for the development of a Meta-Model that promoted the highlight of the fragility of the current management model practiced by the analyzed teaching institution and the Main characteristics that determined the adherence or non-adherence to the requirements presented as solution for the improvement of the management process for quality with excellence in a teaching process, as well as the presentation of a suggestive proposal for the implementation and implementation of the Artifact. Thus, it was concluded that there is no significant adherence of the management model practiced with the Meta-Model developed based on the research. The results obtained with the analysis of the data demonstrate that if applied, the proposed model will bring benefits to the management, including to define the procedures conditioning the operations to the appropriate requirements to the management model of a public educational institution that has its peculiarities. Finally, this paper presents the model artifact and also suggestions for further research on the subject.

在電腦整合製造（Computer Integrated Manufacturing）的系統中 ，資訊整合的良好與否，往往是系統成敗的關鍵所在。在現行組織中，常 常因為資訊的缺乏相互溝通，造成資訊的重覆製作，遂使得人力、時間經 常耗費在一些沒有價值的活動上，因而造成組織中的工作效率無法提升； 然而要真正瞭解組織中各個地區、各部單位到底擁有那些資訊，以及需求 那些資訊，並且將這些往來的資訊整合起來，卻是件相當不容易的事。為 達到此目的則端賴一完整的資訊流程（Information Flow）分析方法，並 參照電腦整合製造資訊流程參考模式（Reference Model ）來幫助我們尋 找及建立製造企業內正確的資訊流程。在本研究中，我們採用由上往下 （ Top-Down）的分析方式，並透過功能拆解（Functional Decomposition）的技術來分析電腦整合製造系統中資訊流程的關聯性， 最後再使用物件導向方法（Object-Oriented Method）來分析系統內細部 的資訊流程；經上述方式，我們發展出一套電腦整合製造系統資訊流程分 析方法，此方法中包含了分析進行的步驟與使用工具。此外，我們亦將依 據此套分析方法，試圖提出一套電腦整合製造資訊流程參考模式，以提供 分析時參考的依據，並驗證此套分析方法的可用性。

Taiwan steel industry has stepped from grown-up into mature period. Especially, the midstream and downstream of steel industries will face the problems of sterner challenges and overcapacity, because of the oversupply of global steel. Not only the prices of oil, coal, water and power have climbed, but also the shipping cost has increased continuously. The improvement of Supply-Chain-Management (SCM) has become a significant issue under the circumstances. The SCM of Taiwan flat cold-rolled steel industry is different from the other ones that it doesn¡¦t use BOM. The main feature of Technical System ¡V ¡§Standard of Operation¡¨(SOP) is the kernel module that links the sales order entry, production management, purchasing, ¡Ketc. The production type is to input a sole coil and output many sub-coils. It is not like the electronic industry to assemble many parts on a product. It only coats the surface of steel with microelements, such as oil, zinc, aluminum and paint. The feature makes it impossible to apply SCM or ERP package directly on this industry. The procedures of this study are mainly through the interview of steel companies, and review on the relevant reference documents related to the subject of those have been published domestically and internationally, meanwhile to get a better understanding on the most recent development of Supply Chain Management and e-business of steel industry. Besides, through the comparison of the similar companies, it is likely to understand the associated topics and models on the SCM and e-Business for flat cold-rolled steel industry. The key point is to analyze the characters of supply chain system of Taiwan cold-rolled steel industry and consider the features of flat cold-rolled steel ¡V SOP and coil- based Standard Cost system, to establish an appropriate e-SCM model, exploring the suitable information technologies and applications to improve the drawbacks of present SCM. Finally, to make a recommendation for the industry as their reference when they plan for the implementation of e-SCM.

No description available.

Configurable process models are integrated representations of multiple variants of a process model in a given domain, e.g. multiple variants of a shipment-to-delivery process in the logistics domain. Configurable process models provide a basis for managing variability and for enabling reuse of process models in Process-Aware Information Systems. Rather than designing process models from scratch, analysts can derive process models by configuring existing ones, thereby reusing proven practices. This thesis starts with the observation that existing approaches for capturing and managing configurable process models suffer from three shortcomings that affect their usability in practice. Firstly, configuration in existing approaches is performed manually and as such it is error-prone. In particular, analysts are left with the burden of ensuring the correctness of the individualized models. Secondly, existing approaches suffer from a lack of decision support for the selection of configuration alternatives. Consequently, stakeholders involved in the configuration of process models need to possess expertise both in the application domain and in the modeling language employed. This assumption represents an adoption obstacle in domains where users are unfamiliar with modeling notations. Finally, existing approaches for configurable process modeling are limited in scope to control-flow aspects, ignoring other equally important aspects of process models such as object flow and resource management. Following a design science research method, this thesis addresses the above shortcomings by proposing an integrated framework to manage the configuration of process models. The framework is grounded on three original and interrelated contributions: (i) a conceptual foundation for correctness-preserving configuration of process models; (ii) a questionnaire-driven approach for process model configuration, providing decision support and abstraction from modeling notations; (iii) a meta-model for configurable process models covering control-flow, data objects and resources. While the framework is language-independent, an embodiment of the framework in the context of a process modeling language used in practice is also developed in this thesis. The framework was formally defined and validated using four scenarios taken from different domains. Moreover, a comprehensive toolset was implemented to support the validation of the framework.

The process control domain is intrinsically complex and dynamic. It has proved to be difficult to construct and maintain process control systems under the traditional software development methodologies. Object Orientation is the latest paradigm in software development. The reason for its widespread acceptance is that it allows the application of the principles of hierarchical structuring and component abstraction which is essential in building large systems. It also promotes component reusability which makes systems easier to maintain and modify. For the process control domain, these are important benefits. Furthermore, most process control systems have physical devices which can be modeled naturally as objects with the timing and performance issues of each object directly addressed. A Target System Reference Model which addresses various aspects of the process control domain is proposed within this dissertation. The objective is to provide a frame of reference within which a process control system can function. / Computing / M. Sc. (Computer Science)