In recent years, more and more vendors adopt Linux to be the embedded operating system for their electronic products because of its combination of reliability, performance, good tool chains, portability, and configurability. However, Linux kernel is complex, and different electronic products may use different platforms. For this reason, it often requires that Linux be ported to different platforms. In this thesis, we describe the details of how we port Linux to a new platform which is similar to but not exactly the same as another platform and thus is not currently supported by the kernel. Moreover, we propose two robust debugging techniques to solve the problems we had encountered in this thesis. One is to make it easier to trace a module with ICE; the other is to allow us to access the internal registers of the processor through the /proc filesystem rather than write a program every time we need to access those internal registers for the purpose of, say, debugging. By using these techniques, we show that the time required to port and debug a Linux kernel can be definitely reduced.

Mehrseitige Rechenblätter in Mathcad werden leicht unübersichtlich. Die nötige Übersicht kann geschaffen werden, in dem man zusammengehörige Informationen auf Registerkarten zusammenfasst. Über Reiter kann direkt zwischen den einzelnen Karten hin und her gesprungen werden. Derartige Strukturen lassen sich in Mathcad überraschend einfach realisieren. Im Beispiel wird der Entwicklungsingenieur durch die Vorauslegung für ein Ventil geführt.

In this paper we seek to answer the following question: How complete is the Swespineregister? In order to answer this question we believe that in a register that has the ambitionto follow-up patients throughout a specified period of time, two types of completeness haveto be defined: external and internal completeness. In our opinion, the correct assessment ofa register’s level of completeness, results in an increase in its credibility, revealing whetherthe register has met its desired level of quality.By defining the register’s target population we came to the conclusion that the methodused by Swespine to calculate external completeness yielded misleading results. We definedanother method of assessing external completeness and concluded that our questioncannot be answered.We have also found an appropriate way to calculate the register’s internal completenesslevel. Since the internal completeness decreases as the follow-up period increases, wesought to discover which groups of patients are more likely to respond to the follow-upquestionnaire. For this a Logistic Regression Method was applied.

Modern computer systems are power or energy limited. While the number of transistors per chip continues to increase, classic Dennard voltage scaling has come to an end. Therefore, architects must improve a design's energy efficiency to continue to increase performance at historical rates, while staying within a system's power limit. Throughput processors, which use a large number of threads to tolerate memory latency, have emerged as an energy-efficient platform for achieving high performance on diverse workloads and are found in systems ranging from cell phones to supercomputers. This work focuses on graphics processing units (GPUs), which contain thousands of threads per chip. In this dissertation, I redesign the on-chip storage system of a modern GPU to improve energy efficiency. Modern GPUs contain very large register files that consume between 15%-20% of the processor's dynamic energy. Most values written into the register file are only read a single time, often within a few instructions of being produced. To optimize for these patterns, we explore various designs for register file hierarchies. We study both a hardware-managed register file cache and a software-managed operand register file. We evaluate the energy tradeoffs in varying the number of levels and the capacity of each level in the hierarchy. Our most efficient design reduces register file energy by 54%. Beyond the register file, GPUs also contain on-chip scratchpad memories and caches. Traditional systems have a fixed partitioning between these three structures. Applications have diverse requirements and often a single resource is most critical to performance. We propose to unify the register file, primary data cache, and scratchpad memory into a single structure that is dynamically partitioned on a per-kernel basis to match the application's needs. The techniques proposed in this dissertation improve the utilization of on-chip memory, a scarce resource for systems with a large number of hardware threads. Making more efficient use of on-chip memory both improves performance and reduces energy. Future efficient systems will be achieved by the combination of several such techniques which improve energy efficiency. / text

The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed. / text

Music is an essential piece of the culture of south Louisiana. Three genres -- Cajun, Zydeco, and Swamp Pop -- grew up in this region. The genres developed as separate cultures, primarily Cajun and Creole, developed and blended before entering a period of cultural assimilation in the early twentieth century. The music, and the social dancing that accompanies it, took place at weekly gatherings in rural residences in the eighteenth century. Commercial dance halls began to appear in the state around 1900 and have evolved throughout the century. The evolution of dance halls and their use follows a cultural evolution from relative isolation to assimilation and eventually cultural awareness and promotion as tourism blossomed in the state. Despite their significant place in the region's history, dance halls are not yet recognized in any official capacity, including the National Register of Historic Places. The Center for Louisiana Studies is collecting information about the extant and demolished buildings to advocate for preservation of dance hall culture and extant buildings. I am contributing to this advocacy effort with a National Register of Historic Places Multiple-Property Documentation Form for extant historic dance halls. The form will discuss the historic contexts of Cajun, Zydeco, and Swamp Pop music and establish typical and variable characteristics, both physical and associative, for dance hall buildings. Registration requirements based on significance and integrity will establish criteria for eligibility of extant buildings for the National Register of Historic Places. / text

La motivación principal de esta tesis es el desarrollo de nuevas técnicas de compilación dirigidas a conseguir mayor rendimiento encódigos numéricos complejos que definen es pacios de iteraciones no rectangulares. En particular, nos centramos en la trasformación de "loop tiling" (también conocida como "blocking") y nuestro propósito es mejorar la transformación de loop tiling cuando se aplica a códigos numéricos complejos. Nuestro objetivo es conseguir, a través de la transformación de loop tiling, los mismos o mejores rendimientos que las librerías numéricas proporcionadas por el fabricante que están optimizadas manualmente.En la tesis se muestra que la razón principal por la que los compiladores comerciales actuales consiguen bajos rendimiento en este tipo de aplicaciones es que no son capaces de aplicar loop tiling a nivel de registros. En su lugar, para mejorar la localidad de los datos y el ILP, los compiladores actuales usan y combinan otras transformaciones que no explotan el nivel de registros tan bien como loop tiling. Previamente no se ha considerado aplicar loop tiling a nivel de registro porque en códigos numéricos complejos no es trivial debido a la naturaleza irregular de los espacios de iteraciones. La primera contribución de esta tesis es un algoritmo general de loop tiling a nivel de registros que es aplicable a cualquier tipo de espacio de iteraciones y no sólo a los espacios rectangulares. Nuestro método incluye una heurística muy sencilla para decidir los parámetros de los cortes a nivel de registros. A primera vista parece que loop tiling a nivel de registros (a partir de ahora, register tiling) se tiene que aplicar de tal manera que el bucle que ofrece más reuso temporal de los datos no debe de ser partido. De esta manera maximizamos la reutilización de los registros y minimizamos el número total de load/stores ejecutados. Sin embargo, mostraremos que en espacios de iteraciones no rectangulares, si solamente tenemos en cuenta las direcciones del reuso y no la forma del espacio de iteraciones, los códigos pueden sufrir una degradación en rendimiento. Nuestra segunda contribución es la propuesta de una heurística muy sencilla que determina los parámetros del tiling a nivel de registros considerando no sólo el reuso temporal sino también la forma del espacio de iteraciones. Además, la heurística es suficientemente sencilla para que pueda ser implementada en un compilador comercial.Sin embargo, para conseguir rendimientos similares que códigos optimizados a mano, no es suficiente con aplicar loop tiling a nivel de registros. Con las arquitecturas de hoy en día que disponen de jerarquías de memoria complejas y múltiples procesadores, es necesario que el compilador aplique loop tiling en cuatro o más niveles (paralelismo, cache L2, cache L1 y registros) para conseguir altos rendimientos. Por lo tanto, en las arquitecturas actuales es crucial tener un algoritmo eficiente para aplicar loop tiling en varios niveles de la jerarquía de memoria (tiling multinivel). Además, como mostramos en esta tesis, la transformación de tiling multinivel siempre tendrá que incluir el nivel de registro porque este es el nivel de la jerarquía de memoria que ofrece mayor rendimiento cuando es tratado correctamente.Cuando tiling multinivel incluye el nivel de registros, es necesario que los límites de los bucles sean exactos y que no haya límites redundantes. La razón es que la complejidad y la cantidad de código que se genera con nuestra técnica de register tiling depende polinómicamente del número de límites de los bucles.Sin embargo, hasta ahora, el problema de calcular límites exactos y eliminar límites redundantes es que todas las técnicas conocidas son muy caras en términos de tiempo de compilación y, por ello, difícil de integrar en un compilador comercial. La tercera contribución de esta tesis es una nueva implementación de tiling multinivel que calcula límites exactos y es mucho menos costosa que técnicas tradicionales. Mostraremos que la complejidad de nuestra implementación es proporcional a la complejidad de aplicar una permutación de bucles en el código original (antes de aplicar loop tiling), mientras que las técnicas tradicionales tienen complejidades más altas. Además, nuestra implementación genera menos límites redundantes y permite eliminar los límites redundantes que quedan a menor coste. En conjunto, la eficiencia de nuestra implementación hace posible que pueda ser implementada dentro de un compilador comercial sin tener que preocuparse por los tiempos de compilación.La última parte de esta tesis está dedicada al estudio del rendimiento de tiling multinivel. Se muestran los efectos de tiling en los diferentes niveles de memoria y presentamos datos que comparan los beneficios de tiling a nivel de registros, tiling a nivel de cache y tiling a los dos niveles, cache y registros, simultáneamente. Finalmente, comparamos el rendimiento de códigos optimizados automáticamente con códigos optimizados manualmente (librerías numéricas que ofrecen los fabricantes) sobre dos arquitecturas diferentes (ALPHA 21164 and MIPS R10000) para concluir que actualmente la tecnología de los compiladores hace posible que códigos numéricos complejos consigan el mismo rendimiento que códigos optimizados manualmente. / The main motivation of this thesis is to develop new compilation techniques that address the lack of performance of complex numerical codes consisting of loop nests defining non-rectangular iteration spaces. Specifically, we focus on the loop tiling transformation (also known as blocking) and our purpose is the improvement of the loop tiling transformation when dealing with complex numerical codes. Our goal is to achieve via the loop tiling transformation the same or better performance as hand-optimized vendor-supplied numerical libraries. We will observe that the main reason why current commercial compilers perform poorly when dealing with this type of codes is that they do not apply tiling for the register level. Instead, to enhance locality at this level and to improve ILP, they use/combine other transformations that do not exploit the register level as well as loop tiling. Tiling for the register level has not generally been considered because, in complex numerical codes, it is far from being trivial due to the irregular nature of the iteration space. Our first contribution in this thesis will be a general compiler algorithm to perform tiling at the register level that handles arbitrary iteration space shapes and not only simple rectangular shapes.Our method includes a very simple heuristic to make the tile decisions for the register level. At first sight, register tiling should be performed so that whichever loop carries the most temporal reuse is not tiled. This way, register reuse is maximized and the number of load/store instructions executed is minimized. However, we will show that, for complex loop nests, if we only consider reuse directions and do not take into account the iteration space shape, the tiled loop nest can suffer performance degradation. Our second contribution will be a proposal of a very simple heuristic to determine the tiling parameters for the register level, that considers not only temporal reuse, but also the iteration space shape. Moreover, the heuristic is simple enough to be suitable for automatic implementation by compilers.However, to be able to achieve similar performance to hand-optimized codes, it is not enough by tiling only for the register level. With today's architectures having complex memory hierarchies and multiple processors, it is quite common that the compiler has to perform tiling at four or more levels (parallelism, L2-cache, L1-cache and registers) in order to achieve high performance. Therefore, in today's architectures it is crucial to have an efficient algorithm that can perform multilevel tiling at multiple levels of the memory hierarchy. Moreover, as we will see in this thesis, multilevel tiling should always include the register level, as this is the memory hierarchy level that yields most performance when properly tiled.When multilevel tiling includes the register level, it is critical to compute exact loop bounds and to avoid the generation of redundant bounds. The reason is that the complexity and the amount of code generated by our register tiling technique both depend polynomially on the number of loop bounds. However, to date, the drawback of generating exact loop bounds and eliminating redundant bounds has been that all techniques known were extremely expensive in terms of compilation time and, thus, difficult to integrate in a production compiler. Our third contribution in this thesis will be a new implementation of multilevel tiling that computes exact loop bounds at a much lower complexity than traditional techniques. In fact, we will show that the complexity of our implementation is proportional to the complexity of performing a loop permutation in the original loop nest (before tiling), while traditional techniques have much larger complexities. Moreover, our implementation generates less redundant bounds in the multilevel tiled code and allows removing the remaining redundant bounds at a lower cost. Overall, the efficiency of our implementation makes it possible to integrate multilevel tiling including the register level in a production compiler without having to worry about compilation time.The last part of this thesis is dedicated to studying the performance of multilevel tiling. We will discuss the effects of tiling for different memory levels and present quantitative data comparing the benefits of tiling only for the register level, tiling only for the cache level and tiling for both levels simultaneously. Finally, we will compare automatically-optimized codes against hand-optimized vendor-supplied numerical libraries, on two different architectures (ALPHA 21164 and MIPS R10000), to conclude that compiler technology can make it possible for complex numerical codes to achieve the same performance as hand-optimized codes on modern microprocessors.

Šiuo darbu buvo siekiama įgyvendinti tikslą, sukurti Vilniaus Pedagoginio Universiteto Matematikos ir informatikos fakultetui elektroninį žiniaraštį, kuris palengvintų darbą su studento informaciją. Sistemos kūrimui buvo pasirinkta atviro kodo programinė įranga PHP, MySQL ir Apache. Teorinėje dalyje yra apžvelgiama programinė įranga, organizuojamas darbas ir aprašoma įgyvendinta sistema. Buvo savarankiškai išmokta dirbti su pasirinkta programine įranga ir sukurta sistema „elektroninis žiniaraštis“. / This work is for accomplishing an aim – to create electronic register for "Vilnius Pedagoginis Universitetas" mathematics and informatics faculty, which would make the work with student's information easier. Open source software basis, which consists of PHP, MySQL and Apache, was chosen for creating this system. Theoretical part consists of review on software, work organization and description of realized system. In order to create the system "elektroninis žiniaraštis" ("electronic register") there was a need to learn to use with chosen software.

The purpose of this study was to explore formal and functional characteristics of e-mail letters. Two types of e-mail letters were subjected to analysis - formal and informal. The method chosen for the study was content analysis. The formal and functional characteristics of e-mails were compared to the formal and functional characteristics of conventional letters. The research demonstrated that formal and functional characteristics of an e-mail letter are similar to a conventional letter in many respects; however, an e-mail letter exhibits certain distinctive features. / Šio darbo tikslas yra nustatyti kiek elektroninio laiško struktūra yra panaši į paprasto laiško struktūrą ir kokie yra skyrybos ženklų vartojimo ypatumai elektroniniame laiške. Remiantis darbo tikslu, buvo iškelti šie uždaviniai: 1) apžvelgti formalių ir neformalių laiškų rašymo standartus, 2) ištirti elektroninio laiško, kaip naujo registro ypatumus, 3) apžvelgti skyrybos vartoseną laiškuose, 4) išanalizuoti skyrybos ženklų vartojimo ypatybes elektroniniuose laiškuose. Atliekant tyrimą, buvo panaudotas turinio analizės metodas. Tyrimo metu buvo išanalizuoti 30 formalių ir 40 neformalių elektroninių laiškų. Elektroninio laiško ypatumai buvo išanalizuoti kiekybiškai, iliustruojant juos pavyzdžiais. Tyrimo rezultatai parodė, kad paprastas ir elektroninis laiškai turi panašumų, tačiau elektroninis laiškas turi ir tik jam charakteringų bruožų: • Formalaus tradicinio ir elektroninio laiško struktūra yra gana panaši. Elektroninis laiškas turi visas struktūrines dalis, būdingas tradiciniam laiškui. Skirtumai slypi įžangoje, kreipiniuose, pagrindinėje dalyje, atsisveikinimuose. Elektroninis laiškas turi adresą, datą, laiką ir temą, tuo tarpu tradicinio laiško įžangoje rašomas tik adresas ir data. Tyrimas parodė, kad dauguma formalaus elektroninio laiško kreipinių ir atsisveikinimų yra neoficialūs. Tradicinis laiškas paprastai turi 4 paragrafus, tuo tarpu elektroninio laiško ilgis varijuoja nuo vienos eilutės iki 7 paragrafų. Tik elektroninis laiškas turi priedą (priemonę... [toliau žr. visą tekstą]

No description available.