Esta pesquisa analisou o processo participativo para a criação da Lei Específica da Guarapiranga (Lei n.º 12.233 de 16/01/2006), nos aspectos da governança da água e da aprendizagem social. A análise foi realizada com base na experiência do Subcomitê da Bacia Hidrográfica Cotia-Guarapiranga (SCBH-CG), na Região Metropolitana de São Paulo (RMSP). No processo de negociação para aprovação da referida Lei, estiveram envolvidos os representantes dos segmentos do Poder Público, Estado e prefeituras dos municípios da bacia, e da sociedade civil, no período de 1999 a 2006. Essa vivência demonstrou o quão desafiador é um processo de negociação entre os diferentes atores e diversos interesses no uso da água, que afetam a disponibilidade qualitativa e quantitativa na bacia da Guarapiranga, a qual abastece, aproximadamente, 4 milhões de pessoas na RMSP. Os resultados obtidos mostram que, embora esse processo tenha sido marcado por diversos momentos de tensão, conflitos, indefinições institucionais e morosidade, representou um significativo avanço na consolidação do sistema integrado de recursos hídricos. Cabe observar também que, apesar dos resultados poderem ainda parecer bastante modestos, face aos desafios existentes, estes representam um importante progresso em termos dos seus alcances para o fortalecimento de uma gestão democrática e compartilhada. Nesse contexto, pode-se concluir que a democracia participativa na governança das águas é um processo de aprendizagem social que vem sendo aperfeiçoado gradativamente para a sustentabilidade hídrica. / This research analyzes the participatory process that preceded the creation of the Specific Law for the Guarapiranga Basin (Law nº. 12.233 of 16/01/2006), emphasizing aspects of water governance and social learning. The analysis was based on the experience of the watershed subcommittee Cotia-Guarapiranga (SCBH-CG) in the Metropolitan Region of São Paulo (MRSP). In the negotiation process for the approval of this law, representatives of the segments of the Government, state and local governments of municipalities of the basin, and civil society were involved from 1999 to 2006. This experience demonstrated the challenges of a process of negotiation among different stakeholders and their interests in water use that affect the availability of water in the Guarapiranga basin, which supplies about 4 million people in the MRSP. The results show that, although the process has been characterized by many moments of tension, conflicts, uncertainties and institutional delays, it represented a significant advance in the consolidation of the integrated system of water resources management in the basin. It should be noted also that although outcomes may seem modest, considering the existing challenges, they represent an important progress in terms of its scope to strengthen democratic and shared management of water resources. In this context, the conclusion is that participatory democracy in water governance is a process of social learning that has been improved gradually to reach more sustainability.

Submitted by Silvana Teresinha Dornelles Studzinski (sstudzinski) on 2016-06-29T14:42:16Z No. of bitstreams: 1 Pablo Eduardo Pereira de Araujo Cottens_.pdf: 1315690 bytes, checksum: 78ac4ce471c2b51e826c7523a01711bd (MD5) / Made available in DSpace on 2016-06-29T14:42:16Z (GMT). No. of bitstreams: 1 Pablo Eduardo Pereira de Araujo Cottens_.pdf: 1315690 bytes, checksum: 78ac4ce471c2b51e826c7523a01711bd (MD5) Previous issue date: 2016-03-07 / Nenhuma / Normalmente Redes Neurais Artificiais (RNAs) necessitam estações de trabalho para o seu processamento, por causa da complexidade do sistema. Este tipo de arquitetura de processamento requer que instrumentos de campo estejam localizados na vizinhança da estação de trabalho, caso exista a necessidade de processamento em tempo real, ou que o dispositivo de campo possua como única tarefa a de coleta de dados para processamento futuro. Este projeto visa criar uma arquitetura em lógica programável para um neurônio genérico, no qual as RNAs podem fazer uso da natureza paralela de FPGAs para executar a aplicação de forma rápida. Este trabalho mostra que a utilização de lógica programável para a implementação de RNAs de baixa resolução de bits é viável e as redes neurais, devido à natureza paralelizável, se beneficiam pela implementação em hardware, podendo obter resultados de forma muito rápida. / Currently, modern Artificial Neural Networks (ANN), according to their complexity, require a workstation for processing all their input data. This type of processing architecture requires that the field device is located somewhere in the vicintity of a workstation, in case real-time processing is required, or that the field device at hand will have the sole task of collecting data for future processing, when field data is required. This project creates a generic neuron architecture in programmabl logic, where Artifical Neural Networks can use the parallel nature of FPGAs to execute applications in a fast manner, albeit not using the same resolution for its otputs. This work shows that the utilization of programmable logic for the implementation of low bit resolution ANNs is not only viable, but the neural network, due to its parallel nature, benefits greatly from the hardware implementation, giving fast and accurate results.

Nowadays the ever increasing algorithmic complexity of embedded applications requires the designers to turn towards heterogeneous and highly integrated systems denoted as SoC (System-on-a-Chip). These architectures may embed CPU-based processors, dedicated datapaths as well as recon gurable units. However, embedded SoCs are submitted to stringent requirements in terms of speed, size, cost, power consumption, throughput, etc. Therefore, new computing paradigms are required to ful l the constraints of the applications and the requirements of the architecture. Recon gurable Computing is a promising paradigm that provides probably the best trade-o between these requirements and constraints. Dynamically recon gurable architectures are their key enabling technology. They enable the hardware to adapt to the application at runtime. However, these architectures raise new challenges in SoC design. For example, on one hand, designing a system that takes advantage of dynamic recon guration is still very time consuming because of the lack of design methodologies and tools. On the other hand, scheduling hardware tasks di ers from classical software tasks scheduling on microprocessor or multiprocessors systems, as it bears a further complicated placement problem. This thesis deals with the problem of scheduling online real-time hardware tasks on Dynamically Recon gurable Hardware Devices (DRHWs). The problem is addressed from two angles : (i) Investigating novel algorithms for online real-time scheduling/placement on DRHWs. (ii) Scheduling/Placement algorithms library for RTOS-driven Design Space Exploration (DSE). Regarding the first point, the thesis proposes two main runtime-aware scheduling and placement techniques and assesses their suitability for online real-time scenarios. The first technique discusses the impact of synthesizing, at design time, several shapes and/or sizes per hardware task (denoted as multi-shape task), in order to ease the online scheduling process. The second technique combines a looking-ahead scheduling approach with a slots-based recon gurable areas management that relies on a 1D placement. The results show that in both techniques, the scheduling and placement quality is improved without signi cantly increasing the algorithm time complexity. Regarding the second point, in the process of designing SoCs embedding recon gurable parts, new design paradigms tend to explore and validate as early as possible, at system level, the architectural design space. Therefore, the RTOS (Real-Time Operating System) services that manage the recon gurable parts of the SoC can be re fined. In such a context, gathering numerous hardware tasks scheduling and placement algorithms of various complexity vs performance trade-o s in a kind of library is required. In this thesis, proposed algorithms in addition to some existing ones are purposely implemented in C++ language, in order to insure the compatibility with any C++/SystemC based SoC design methodology.

Les communications entre les applications réseaux sont régies par un ensemble de règles regroupées sous forme de protocoles. Les messages protocolaires sont gérés par une couche de l’application réseau connue comme étant la couche de support protocolaire. Cette couche peut être de nature logicielle, matérielle ou conjointe. Cette couche se trouve à la frontière entre le coeur de l’application et le monde extérieur. A ce titre, elle représente un composant névralgique de l’application. Les performances globales de l’application sont ainsi directement liées aux performances de la couche de support protocolaire associée.Le processus de développement de ces couches consiste à traduire une spécification du protocole, écrite dans un langage de haut niveau tel que ABNF dans un langage bas niveau, logiciel ou matériel. Avec l’avènement des systèmes embarqués, de plus en plus de systèmes sur puce proposent l’utilisation de ressources matérielles afin d’accroître les performances des applicatifs. Néanmoins, peu de processus de développement de couches de support protocolaire tirent parti de ces ressources, en raison notamment de l’expertise nécessaire dans ce domaine.Cette thèse propose une approche générative conjointe logicielle-matérielle au développement du support protocolaire d’applications réseaux, pour améliorer leur performance tout en restant ergonomique pour le développeur de l’application. Notre approche est basée sur l’exploitation d’un langage dédié, appellé Zebra pour générer les différents composants logiciels et matériels formant la couche de support. L’expertise nécessaire est déportée dans l’utilisation du langage Zebra et les composants matériels générés permettent d’accroître les performances de l’application.Les contributions de cette thèse sont les suivantes : Nous avons effectué une analyse des protocoles et applications réseaux. Cette analyse nous a permis d’identifier les composants pour lesquels il est possible d’obtenir des gains de performances.Nous avons conçu et exploité un langage dédié, Zebra, permettant de décrire les différentes entités de la couche de support protocolaire et générant les éléments logiciels et matériels la composant. Nous avons construit un système sur puce exécutant un système d’exploitation Linux afin d’étayer notre approche. Nous avons conçu des accélérateurs matériels déployables pour différents protocoles réseaux sur ce système et pilotables par les applicatifs. Afin de rendre l’accès aux accélérateurs matériels transparent pour les applications réseaux, nous avons développé un intergiciel gérant l’ensemble de ces accès. Cet intergiciel permet à plusieurs applications et/ou à plusieurs clients d’une même application d’utiliser les accélérateurs pour le traitement des messages protocolaires. Nous avons évalué les performances de notre approche dans des conditions réelles. Nous avons comparé ces performances à celles de couches de supports faisant référence dans le domaine. Nous avons constaté un gain de performance conséquent pour l’approche que nous proposons. / Communications between network applications is achieved by using rulesets known as protocols. Protocol messages are managed by the application layer known as the protocol parsing layer or protocol handling layer. Protocol parsers are coded in software, in hardware or based on a co-design approach. They represent the interface between the application logic and the outside world. Thus, they are critical components of network applications. Global performances of network applications are directly linked to the performances of their protocol parser layers.Developping protocol parsers consists of translating protocol specifications, written in a high level language such as ABNF towards low level software or hardware code. As the use of embedded systems is growing, hardware ressources become more and more available to applications on systems on chip (SoC). Nonetheless, developping a network application that uses hardware ressources is challenging, requiring not only expertise in hardware design, but also a knowledge of the protocols involved and an understanding of low-level network programming.This thesis proposes a generative hardware-software co-design based approach to the developpement of network protocol message parsers, to improve their performances without increasing the expertise the developper may need. Our approach is based on a dedicated language, called Zebra, that generates both hardware and software elements that compose protocol parsers. The necessary expertise is deported in the use of the Zebra language and the generated hardware components permit to improve global performances.The contributions of this thesis are as follows : We provide an analysis of network protocols and applications. This analysis allows us to detect the elements which performances can be improved using hardware ressources. We present the domain specific language Zebra to describe protocol handling layers. Software and hardware components are then generated according to Zebra specifications. We have built a SoC running a Linux operating system to assess our approach.We have designed hardware accelerators for different network protocols that are deployed and driven by applications. To increase sharing of parsing units between several tasks, we have developped a middleware that seamlessly manages all the accesses to the hardware components. The Zebra middleware allows several clients to access the ressources of a hardware accelerator. We have conducted several set of experiments in real conditions. We have compared the performances of our approach with the performances of well-knownprotocol handling layers. We observe that protocol handling layers baded on our approach are more efficient that existing approaches.

La modélisation d'un système intégré sur puce nécessite la spécification de l'application logicielle et la modélisation de l'architecture matérielle puis le déploiement du logiciel sur ce matériel. L'objectif du concepteur de systèmes intégrés est de trouver la meilleure solution de déploiement pour optimiser les critères de surface de silicium, de consommation d'énergie, et de performances. Ces critères sont le plus souvent évalués par simulation. En raison du grand nombre de paramètres de l'architecture matérielle et des choix dans le déploiement du logiciel sur l'architecture, le temps nécessaire pour les simulations est important. Les outils permettant de réduire ce temps présentent un grand intérêt. Cette thèse présente des principes et des outils pour faciliter le développement des architectures matérielles et pour accélérer la simulation de modèles d'architectures synchrones décrites en langage SystemC, précis au cycle près et au bit près. Ce document est constitué de quatre chapitres : • La modélisation de composants matériels en SystemC sous la forme d'automates synchrones communicants (CFSM) ; • La génération de modèles SystemC, pour la simulation, à partir de descriptions synthétisables VHDL au niveau RTL ; • La vérification des règles d'écriture des modèles SystemC ; • La simulation rapide à l'aide d'une technique d'ordonnancement totalement statique. Ces outils permettent au concepteur de construire rapidement une architecture matérielle à l'aide de composants synthétisables au niveau RTL et de composants SystemC, respectant le modèle des CFSM. SystemCASS simule une telle architecture avec une accélération supérieure à un facteur 12 par rapport à un simulateur à échéancier dynamique.

<p>This study aims to explore purposes of daily workshops for persons with disabilities. The method used was qualitative interviews. An inductive research strategy was used. Half-structured interviews with six managers of daily workshops were carried out, wherein they expressed their intentions with the daily workshops and the reasons for people to participate. The interviews were analysed with Antonovsky´s salutogenetic perspective,<strong> </strong>in which Sense of Coherence, SOC is a main concept, and with the normalisation principle. The study indicates that the managers aim to create a good, rather than a normalizing work situation for their participants. The main result is that the managers want the work to be meaningful, appreciated and for the benefit of others.</p>

<p>In recent times statistical findings suggesting a deteriorating mental health among teenagers, have been published. Not only did I find the lack of an all-inclusive analysis problematic, but also the fact that the studies themselves where often insufficient. Thus my purpose has been to chart these statistical studies, and then scrutinize the results.My method has been inspired by critical theory, where an interpretive starting point, self-reflection, and the idea that man and society interacts as a whole, is of great importance. Aside from the above mentioned studies, I have also employed secondary empirical data from TV, newspapers and the Internet. My own experience as a social worker has also been an important resource for this paper. The results from the statistical studies are analysed through theories regarding cultural modernisation, in particular Thomas Ziehe's ideas about cultural release of constraints, and Aaron Antonovsky's ideas concerning the importance of SOC (sense of coherence). Rapports from the Welfare Commission pertaining to developments in the Swedish welfare during the 1990's are also central for this thesis. I have found that the results from the statistical studies could be the outcome of other factors than mental illness per se - such as the play down in society concerning some of the taboos associated with it. This means that today's youth have easier access to psychiatric care (in so far as they are more willing to talk about psychiatric problems) and therefore necessarily don't feel worse than preceding age groups. Having said that, my conclusion is that today's youth is more inclined to mental illness than teenagers 10-15 years ago. My belief is that this is due to cultural modernisation and growing shortcomings within the social welfare. Cultural modernisation can make for an arduous upbringing, and a society where traditional norms are being replaced by everlasting possibilities, do put a fair amount of strain on the young individual. In my final discussion I'll conclude that SOC, which was previously created collectively, is now an undertaking of the sole individual. Therefore, I mean, today's teenagers are in the need of sufficient tools in their identity work. Naturally these can be found within the perpetual bombardment of information and symbols that surrounds them, but this should not diminish the importance of an everyday contact with sensible grownups, who understands the need to counterbalance a manipulative market.</p>

<p>This report describes both evaluation and implementation of the new coming image compression standard JPEG XR. The intention is to determine if JPEG XR is an appropriate standard for IP based video surveillance purposes. Video surveillance, especially IP based video surveillance, currently has an increasing role in the security market. To be a good standard for surveillance, the video stream generated by the camera is required to be low bit-rate, low latency on the network and at the same time keep a high dynamic display range. The thesis start with a deep insightful study of JPEG XR encoding standard. Since the standard could have different settings,optimized settings are applied to JPEG XR encoder to fit the requirement of network video surveillance. Then, a comparative evaluation of the JPEG XR versusthe JPEG is delivered both in terms of objective and subjective way. Later, part of the JPEG XR encoder is implemented in hardware as an accelerator for further evaluation. SystemVerilog is the coding language. TSMC 40nm process library and Synopsys ASIC tool chain are used for synthesize. The throughput, area, power ofthe encoder are given and analyzed. Finally, the system integration of the JPEGXR hardware encoder to Axis ARTPEC-X SoC platform is discussed.</p>

<p>A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application.</p><p>These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area.</p><p>The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction.</p><p>The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.</p>

<p>Isberg, A. & Lidén, S. (2008). <em>KASAM- livsfrågeformulär som intervention vid psykisk ohälsa. </em>Högskolan i Gävle; Institutionen för pedagogik, didaktik och psykologi.</p><p> </p><p>Tidigare studier visar samband mellan KASAM, Känsla av sammanhang och människors upplevda hälsa. Då psykisk ohälsa tenderar att öka växer behovet av hälsofrämjande åtgärder. I och med detta ville vi studera om KASAM- livsfrågeformulär kunde användas som intervention vid psykisk ohälsa. Studien utgår ifrån en kvalitativ ansats för att få en djupare förståelse för hur deltagarna tänker och känner. Fyra deltagare med psykisk ohälsa har fyllt i KASAM- livsfrågeformulär samt intervjuats med syfte att undersöka om KASAM- livsfrågeformulär inneburit en förändrad förståelse för deltagarnas livssituation. Resultatet visar att deltagarna upplevde att KASAM- livsfrågeformulär inneburit nya reflektioner över sig själv och sin livssituation.</p>