Thesis (M.S. in Mechanical Engineering)--Naval Postgraduate School, March 2004. / Thesis advisor(s): Indranath Dutta. Includes bibliographical references (p. 45-47). Also available online.

Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Rao. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 103-114). Also available in electronic version. Access restricted to campus users.

Thesis (M. S.)--Mechanical Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Ume, I. Charles; Committee Member: Mayor, J. Rhett; Committee Member: Sadegh, Nader. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Electromigration related damage in solder bumps is one of the emerging issues resulting from the fast scaling-down of features in semiconductor packages. Although the electromigration phenomenon has been intensively studied on silicon level interconnect lines since the late 1960s, it is far less understood in solder bumps. Electromigration in solder joints can be quite different from that of the interconnects due to the differences in material systems and structures. This study addressed the solder joint electromigration and contained three major objectives. The first objective of this study was to set up an effective experimental technique to examine the damage development and determine the time-to-failure in the electromigration tests. The structure and dimension of the flip chip solder bump is very different from that of the chip level interconnect. Consequently, the traditional failure tracking method based on 2-point resistance monitoring is no longer able to provide real-time damage evolution information. A test system based on a Wheat stone bridge circuit was introduced. The technique showed the capability of detecting milliohm resistance changes and could track the interfacial crack growth induced by electromigration damage. Other aspects of the experiment, such as temperature and current distribution inside the test structure, were also examined so that proper lifetime could be extrapolated from testing condition to normal working condition. The second objective was to examine the failure mechanisms in solder bump electromigration which could be significantly different between various solder bump systems. Pb-free and high-Pb solder alloys with different UBM configurations were studied. The research results showed that the most active region during solder bump electromigration was the under bump metallization (UBM) layer and its interface with the solder due to the intermetallic compound formation and UBM dissolution. Therefore, the electromigration-induced damage occurred mostly in this region. The failure mechanisms were found to be highly dependent on the material system as well as the temperature. The third objective was to determine the statistical lifetime of the flip chip solder bumps under electromigration. Lognormal distributions were used to fit the lifetime. The temperature and current dependence was assumed to follow Black's equation and the activation energies was calculated from that. The results showed that the traditional Black's equation might not be applicable to solder bump electromigration due to the different failure mechanism at different temperatures. Special attention is needed to set up design rules for maximum operating current and temperature for a solder bump structure when extrapolating data from high temperature. / text

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