Les travaux précédemment réalises au sein du LPICM ont mis en évidence que le silicium microcristallin est un semi-conducteur a faible cout, possédant une mobilité importante avec malgré tout une très bonne stabilité. Ce qui en fait un matériau particulièrement intéressant pour les transistors TFTs des écrans plats OLED 2. Il nous a donc paru logique de nous intéresser, dans le cadre de cette thèse, a la conception et a la réalisation expérimentalement des structures de pixel OLED à base de transistors TFTs en silicium microcristallin. Pour ce faire, il est indispensable de posséder des modèles comportementaux performants des composants. Ainsi, notre objectif primordial a été de concevoir des modèles Spice de transistors c-Si TFT mais aussi d'OLED. D'un point de vue technologique, nous nous sommes attaches à maitriser l'ensemble de la chaine de fabrication (conception de masques et lithographie en salle blanche). La caractérisation de nos transistors a révèle des mobilités de l'ordre de 1 cm2V−1s−1, des tensions de seuil de 4 V et a montre une bonne stabilité, sous stress, de la tension de seuil et de la mobilité. La faisabilité de ces transistors sur substrats flexibles comme le polyimide a aussi été démontre dans le cadre du Projet Intégré FlexiDis. Du point de vue de la modélisation, un modèle statique et dynamique Spice de transistor en silicium microcristallin est propose. L'écriture de ce modèle dans le langage Verilog-A nous permet de garantir une bonne portabilité et de pouvoir ainsi utiliser facilement des simulateurs professionnels comme Spectre de chez Cadence. De manière complémentaire, un modèle Spice efficient de diode OLED est également propose. Grace à ces outils, nous avons pu simuler des circuits utilisant les TFTs en silicium microcristallin. Ces simulations nous permettent de prédire que ces composants sont pertinents pour la conception de pixel OLED, de drivers de lignes, mais aussi de portes logiques NMOS simples comme l'inverseur et l'oscillateur en anneau.

Le rendement théorique unitaire des convertisseurs à découpage rend ceux-ci attrayants dès qu'il s'agit de traiter l'énergie électrique. Mais les èontraintes de coût et d'encombrement imposent des fréquences de commutation toujours plus élevées (ce qui entraîne des contraintes CEM) et l'utilisation de supports modernes permettant la miniaturisation (SMI, Hybride, Silicium). Dans ce contexte, la simulation est devenue une étape indispensable à la conception de convertisseurs et la modélisation fine des éléments qui les constitue (dont les transistors MOS de puissance font souvent partie à faible tension) une nécessité. Ce travail traite de la modélisation du transistor VDMOS et se partage en trois parties. La première aborde le cas de son comportement statique en intégrant la particularité de son canal réalisé par double diffusion. Le modèle simplifié qui en découle se limite à 5 paramètres dont les méthodes d'extraction utilisées sont décrites. La seconde partie de ce travail est une étude fine du comportement dynamique du VDMOS dans sa cellule de commutation. Elle complète le modèle statique et permet un modèle fiable rendant Gompte de l'influence du niveau de courant sur les commutations moyelmant 6 paramètres supplémentaires. Les différentes méthodes de mesure pelmettant de déterminer les valeurs de ces paramètres sont détaillées. Enfin, la troisième et dernière partie valide le modèle à l'aide de l'outil de simulation Pspice. Une comparaison est faite avec d'autres modèles proposés dans la littérature.

Thermoelectric devices are capable of providing both localized active cooling and waste heat power generation. This work will explore the possibility of embedding thermoelectric devices within electronic packaging in order to achieve better system performance. Intel and Nextreme, Inc. have produced thin-film superlattice thermoelectric devices that have above average performance for thermoelectrics and are much thinner than most devices on the market currently. This allows them to be packaged inside of the electronic package where the thermoelectric devices can take advantage of the increased temperatures and decreased thermal lag as compared to the devices being planted on the outside of the package. This work uses the numerical CFD solver FLUENT and the analog electronic circuit simulator SPICE to simulate activity of thermoelectric devices within an electronics package.

Avionics Division of Saab AB develops advanced electronics that need to be robust and work in harsh environments with for example extreme temperatures and cosmic radiation without any failure. To succeed with this the electronics need to be simulated and tested. Therefore this thesis work is done to strengthen the Avionics Division’s knowledge of hardware modelling and simulation by evaluating the simulation tools LTSpice, PSpice and SystemVision, their functions and capabilities. In this thesis a survey is carried out with help of a questionnaire to study the Avionics Division’s needs for simulation. The survey is underlying an analysis of the analyses that can be performed by the simulation tools for example Sensitivity analysis, Worst Case analysis, Monte Carlo analysis and Parametric Sweep analysis. The different analyses are discussed in the thesis. The questionnaire is also underlying an analysis of the tools LTSpice, PSpice and SystemVision. The result of the analysis is summarized in Table 1. A case study of a circuit simulation in SystemVision, based on an existing circuit used by Avionics Division, is also done within this thesis work. The study is done to evaluate the tool’s usability, to see if it is easy to perform a simulation and if it is easy to find and use suitable models from the model library. The case study describes how a simulation is performed in SystemVision and how an AC analysis of a Butterworth filter is done. A stability and reliability check of the tool is performed as well as a robustness simulation. The analyses were easy to do and the overall impression is that SystemVision is reliable and user friendly structured. In order to check and compare the results of the AC analysis the same analysis is performed using LTSpice. The comparison shows that the results differ. This depending on that the models of the circuit were some what different in LTSpice and SystemVision. The final conclusion is that SystemVision would fit within Avionics Division’s workflow. Using SystemVision demands education of the engineers to secure maximum use of all the advantages of SystemVision.

SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the interface like multiple-level caches between high speed processing elements and low speed peripherals. One method to design the SRAM is to use commercial memory compiler. Such compiler can generate different density/speed SRAM designs with single/dual/multiple ports to fulfill design purpose. There are discrepancy of the SRAM timing parameters between extracted layout netlist SPICE simulation vs. equation-based Liberty file (.lib) by a commercial memory compiler. This compiler takes spec values as its input and uses them as the starting points to generate the timing tables/matrices in the .lib. Originally large spec values are given to guarantee design correctness. While such spec values are usually too pessimistic when comparing with the results from extracted layout SPICE simulation, which serves as the “golden” rule. Besides, there is no margin information built-in such .lib generated by this compiler. A new methodology is proposed to get accurate spec values for the input of this compiler to generate more realistic matrices in .lib, which will benefit during the integration of the SRAM IP and timing analysis.

This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency.A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice.The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison.Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area. The LPFF presented D-to-Q delays of 60% to 69% longer than the delays of the TGFF and 9% to 11% longer than the delays of the TGCGFF. The LPFF cells require an area that is 15% to 34% larger than the TGFF cells and 6% to 17% larger than the TGCGFF cells.

Ertrag und Produktqualität sind entscheidende Größen, um die Vermarktung und Erlöse im ökologischen Heil- und Gewürzpflanzenanbau zu verbessern. Ein hoher Gehalt an Wert gebenden Inhaltsstoffen, geringe Anteile an Beimengungen (Schmutz, Fremdbestandteile), Rückstandsfreiheit an Pflanzenschutzmitteln, niedrige Gehalte an toxischen Schwermetallen und Nitrat sind dabei wichtige Qualitätskriterien, die durch anbautechnische Maßnahmen beeinflussbar sind. Hier sollen für wichtige Heil- und Gewürzpflanzen praxisrelevante Ergebnisse vorgelegt und Anbauempfehlungen abgeleitet werden. Die Analyse der Anbau-, Verarbeitungs- und Vermarktungsstrukturen in Sachsen trägt darüber hinaus dazu bei, dass sich die Marktakteure auf diesem Sektor hinsichtlich ihres Angebotsprofils und der Anbau- und Verarbeitungsmöglichkeiten intensiver kennen lernen und neue Wirtschaftskontakte knüpfen können.

This dissertation is a study of early Islamicate commerce in natural luxuries of the tropical Indian Ocean and Western Pacific Rim, such as spices, ambergris and pearls, between the ninth and eleventh centuries C.E. I approach this topic by looking at a wide array of textual sources, from geographies, anecdotes, travel narratives, inscriptions, and the records of embassies, to materia medica and the oldest surviving Islamicate cookbook. I analyze these sources alongside material culture, archeological evidence from ports in Iran, Oman, and Southeast Asia, and newly-discovered shipwrecks from the Java Sea. Adapting the work of environmental scientists to the thesis, I locate this early Islamicate commerce within a bio-geographical space, the tropical "Indo-Pacific." I argue that desires for the tropical luxuries of the environmentally-distinct Indo-Pacific helped to define the cosmopolitan culture of early Islamicate societies, from Iran and Iraq to Egypt and Spain. These desires promoted an expanding Islamicate maritime commerce across the Indo-Pacific, which led to the flourishing of port-cities in southern Iran and Oman. This maritime trade expanded Islamicate geographical horizons, as reflected in the evolving "wonders" and geographical literature of the era. It also led to early contacts between the Islamic world and the peoples of the tropical Pacific Rim, a phenomenon that contributed, in time, to the formation of Islamicate societies in maritime Southeast Asia. / Near Eastern Languages and Civilizations

Šio dokumento tikslas sukurti metodus ir papildomą medžiagą, kuri leistų analizuoti ir verifikuoti "PKP Branda" modelio vertinimų rezultatus. "PKP Branda" modelis buvo sukurtas CMMI bei SPICE modelių pagrindu. Šiame darbe, panaudojant modelyje aprašytus darbo produktus (DP), buvo nagrinėjami "PKP Branda" modelio ryšiai tarp procesų. Darbo metu buvo apskaičiuoti modelio ryšiai tarp procesų, procesų svoriai, išskirti esminiai procesai. Šio darbo rezultatai gali būti naudojami kaip papildoma medžiaga analizuojant vertinimų rezultatus. / The aim of this thesis is to create methods and extra material which would allow to analyze and verify the assessment results from the “PKP Branda” maturity model. "PKP Branda" model was created using CMMI and SPICE best practices. In this work relations between the ����PKP Branda” model processes were researched using work products described in the model. During this research relations between processes and their weight were calculated, essential processes were excluded. The results of this work can be used as an extra material to analyze assessment results.

Due to the prevalence of pulse encoders for system state information, an all-digital proportional-integral-derivative (ADPID) is proposed as an alternative to traditional analog and digital PID controllers. The basic concept of an ADPID stems from the use of pulse-width-modulation (PWM) control signals for continuous-time dynamical systems, in that the controllers proportional, integral and derivative actions are converted into pulses by means of standard up-down digital counters and other digital logic devices. An ADPID eliminates the need for analog-digital and digital-analog conversion, which can be costly and may introduce error and delay into the system. In the proposed ADPID, the unaltered output from a pulse encoder attached to the systems output can be interpreted directly. After defining a pulse train to represent the desired output of the encoder, an error signal is formed then processed by the ADPID. The resulting ADPID output or control signal is in PWM format, and can be fed directly into the target system without digital-to-analog conversion. In addition to proposing an architecture for the ADPID, rules are presented to enable control engineers to design ADPIDs for a variety of applications.