Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar processing system must also be small and efficient. This thesis presents the design of the processing system for a small Frequency Modulated Continuous Wave (FMCW) phased array radar. The radar and processing is designed to be light-weight and low-power in order to fly onboard a UAV less than 25 kg in weight. The radar algorithms for this design include a parallelized Fast Fourier Transform (FFT), cross correlation, and beamforming. Target detection algorithms are also implemented. All of the computation is performed in real-time on a Xilinx Zynq 7010 System on Chip (SoC) processor utilizing both FPGA and CPU resources. The radar system (excluding antennas) has dimensions of 2.25 x 4 x 1.5 in3, weighs 120 g, and consumes 8 W of power of which the processing system occupies 2.6 W. The processing system performs over 652 million arithmetic operations per second and is capable of performing the full processing in real-time. The radar has also been tested in several scenarios both airborne on small UAVs as well as on the ground. Small UAVs have been detected to ranges of 350 m and larger aircraft up to 800 m. This thesis will describe the radar design architecture, the custom designed radar hardware, the FPGA based processing implementations, and conclude with an evaluation of the system's effectiveness and performance.

Abstract This thesis focuses on two important challenges in wireless downlink transmission: multi-user (MU) precoder design and scheduling of users over time, frequency, and spatial resources at any given instant. Data streams intended for different users are transmitted by a multiple-input multiple-output (MIMO) multi-antenna orthogonal frequency division multiplexing (OFDM) system. The transmit precoders are designed jointly across space-frequency resources to minimize the number of backlogged packets waiting at the coordinating base stations (BSs), thereby implicitly performing user scheduling. Then the problem of multicast beamformer design is considered wherein a subset of users belonging to a multicasting group are served by a common group-specific data. The design objective is to either minimize the transmit power for a guaranteed quality-of-service, or to maximize the minimum achievable rate among users for a given transmit power. Unlike existing techniques, the proposed design utilizes both the spatial and frequency resources jointly while designing multi-group beamformers. As an extension to coordinated precoding, the problem of beamformer design for cloud radio access network is considered wherein beamformers are designed centrally, quantized and sent along with data to the respective BSs via backhaul. Since the users can be served by multiple BSs, beamformer design becomes a nonconvex combinatorial problem. Unlike existing solutions, beamformer overhead is also included in the backhaul utilization along with the associated data. As the number of antennas increases, backhaul utilization is dominated by the beamformers. Thus, to reduce the overhead, two techniques are proposed: varying the quantization precision, and reducing the number of active antennas used for transmission. Finally, to reduce the complexity involved in the design of joint space- frequency approach, a two-step procedure is proposed, where a MU-MIMO scheduling algorithm is employed to find a subset of users for each scheduling block. The precoders are then designed only for the chosen users, thus reducing the complexity without compromising much on the throughput. In contrast to the null-space-based existing techniques, a low-complexity scheduling algorithm is proposed based on vector projections. The real-time performance of all the schedulers are evaluated by implementing them on both Xilinx ZYNQ-ZC702 system-on-chip (SoC) and TI TCI6636K2H multi-core SoC. / Tiivistelmä Tässä väitöskirjassa keskitytään kahteen tärkeään langattoman tiedonsiirron haasteeseen alalinkkilähetyksissä: usean käyttäjän (MU) esikooderisuunnitteluun ja käyttäjien skedulointiin aika-, taajuus- ja tilaresurssien yli. Eri käyttäjille tarkoitettuja datavirtoja lähetetään käyttämällä monitulo-monilähtötekniikkaa (MIMO) yhdistettynä monikantoaaltomodulointiin (OFDM). Lähettimien esikooderit suunnitellaan yhteisesti tila- ja taajuusresurssien yli, jotta keskenään yhteistoiminnallisten tukiasemien jonossa olevien pakettien määrää voitaisiin minimoida samalla kun tehdään epäsuorasti käyttäjien skedulointia. Tämän jälkeen työssä paneudutaan monilähetysten (multicast) keilanmuodostussuunnitteluun, jossa monilähetysryhmään kuuluvien käyttäjien alijoukolle lähetetään yhteistä ryhmäspesifistä dataa. Suunnittelun päämääränä on joko minimoida kokonaislähetysteho tietyllä palvelunlaatuvaatimuksella tai maksimoida pienin saavutettavissa oleva siirtonopeus käyttäjien joukossa tietyllä lähetysteholla. Toisin kuin olemassa olevat menetelmät, ehdotetussa mallissa käytetään yhteisesti sekä aika- että taajuusresursseja usean ryhmän keilanmuodostusta suunniteltaessa. Laajennuksena yhteistoiminnalliselle esikoodaukselle, väitöskirjassa käsitellään myös keilanmuodostusta pilvipohjaisessa radioliityntäverkkoarkkitehtuurissa. Keilanmuodostajat suunnitellaan keskitetysti, kvantisoidaan ja lähetetään datan mukana tukiasemille käyttäen runkoverkkoyhteyttä. Koska käyttäjiä voidaan palvella usealta tukiasemalta, keilanmuodostussuunnittelu muuttuu ei-konveksiksi kombinatoriseksi ongelmaksi. Toisin kuin olemassa olevissa ratkaisuissa, ehdotettu malli sisällyttää käyttäjien datan lisäksi keilanmuodostajien resursoinnin tarpeen runkoverkkoon. Tukiaseman antennien määrän lisääntyessä, keilanmuodostajien osuus runkoverkon käyttöasteesta kasvaa suureksi. Jotta keilanmuodostajien aiheuttamaa ylimääräistä tiedonsiirtotarvetta voitaisiin minimoida, esitellään kaksi tekniikkaa: kvantisointitarkkuuden muunteleminen sekä lähetykseen käytettävien aktiivisten antennien määrän vähentäminen. Lopuksi, jotta yhdistetyn tila-taajuussuunnittelun aiheuttamaa kompleksisuutta saataisiin vähennettyä, ehdotetaan kaksivaiheista menetelmää. MU-MIMO skedulointialgoritmin avulla etsitään ensin alijoukko käyttäjiä jokaiselle skedulointilohkolle. Esikooderit suunnitellaan vain valituille käyttäjille, mikä vähentää kompleksisuutta, heikentämättä suorituskykyä kuitenkaan olennaisesti. Poiketen nolla-avaruuteen perustuvista tekniikoista, esitetään yksinkertainen vektoriprojektioihin perustuva skeduleri. Kaikkien skedulerien reaaliaikasuorituskykyä on arvioitu toteuttamalla ne ohjelmoitavilla Xilinx ZYNQ-ZC702 system-on-chip (SoC) ja TI TCI6636K2H moniydinalustoilla.

More complex and intricate Computer Vision algorithms combined with higher resolution image streams put bigger and bigger demands on processing power. CPU clock frequencies are now pushing the limits of possible speeds, and have instead started growing in number of cores. Most Computer Vision algorithms' performance respond well to parallel solutions. Dividing the algorithm over 4-8 CPU cores can give a good speed-up, but using chips with Programmable Logic (PL) such as FPGA's can give even more. An interesting recent addition to the FPGA family is a System on Chip (SoC) that combines a CPU and an FPGA in one chip, such as the Zynq-7000 series from Xilinx. This tight integration between the Programmable Logic and Processing System (PS) opens up for designs where C programs can use the programmable logic to accelerate selected parts of the algorithm, while still behaving like a C program. On that subject, Xilinx has introduced a new High-Level Synthesis Tool (HLST) called Vivado HLS, which has the power to accelerate C code by synthesizing it to Hardware Description Language (HDL) code. This potentially bridges two otherwise very separate worlds; the ever popular OpenCV library and FPGAs. This thesis will focus on evaluating Vivado HLS from Xilinx primarily with image processing in mind for potential use on GIMME-2; a system with a Zynq-7020 SoC and two high resolution image sensors, tailored for stereo vision.

This project deals with computation of eigenvalues and eigenvectors of Hermitian positive-semidefinite complex square matrix of order 4. The target is an implementation of computation in language VHDL to field-programmable gate array of type Xilinx Zynq-7000. This master project deals with algorithms used for computation of eigenvalues and eigenvectors of positive-semidefinite symmetric real square and positive-semidefinite complex Hermitian matrix and the analysis of algorithms by AnalyzeAlgorithm program assembled for this purpose. The closing part of this project describes implementation of the computation into field-programmable gate array with use of IP core Xilinx® Floating-Point \linebreak Operator and SVAOptimalizer, SVAInterpreter and SVAToDSPCompiler programs.

FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histogram as a test case to investigate the efficiency of three different tools, HDL Coder in MATLAB, HDL Coder in Simulink and System Generator for DSP in comparison to the direct development of the same histogram in Vivado using Verilog. How to write and structure code in these tools for proper functionality was also examined. It has been found that all tools deliver an operation frequency comparable to a direct implementation in Verilog, decreased resource usage, a development time which decreased by 27% (HDL Coder in MATLAB), 45% (System Generator) and 64% (HDL Coder in Simulink) but at the cost of increased power consumption. Instructions for how to use all three tools has been collected and summarised. / I ingångssteget på ett mätsystem är det av intresse att använda en FPGA för att uppnå höga hastigheter på de oundvikliga datafiltrering och sorterings algoritmer som körs. Ett problem med FPGAer är att utvecklingen ställer höga krav på specifik kunskap gällande utvecklingsspråk och miljöer vilket för en person specialiserad inom t.ex. signalbehandling kan saknas helt. HLS är en metodik där högnivåspråk kan användas för digital design genom att nyttja ett verktyg för automatgenerering av kod. I detta arbete har utveckling av ett histogram använts som testfall för att utvärdera effektivitet samt designmetodik av tre olika HLS verktyg, HDL Coder till MATLAB, HDL Coder till Simulink och System Generator for DSP. Utvecklingen i dessa verktyg har jämförts mot utvecklingen av samma histogram i Vivado, där språket Verilog använts. Arbetets slutsater är att samtliga verktyg som testats leverar en arbetsfrekvens som är jämförbar med att skriva histogrammet direkt i Verilog, en minskad resursanvändning, utvecklingstid som minskat med 27% (HDL Coder i MATLAB), 45% (System Generator) och 64% (HDL Coder i Simulink) men med en ökad strömförbrukning. En sammanställning av instruktioner för utveckling med hjälp av verktygen har även gjorts.

Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications.

This work describes design and implementation of radar processor in FPGA. The theoretical part is focused on Doppler radar, principles of radar signal processing methods and target platform Xilinx Zynq. The next part describes design of radar processor including its individual components and the solution is implemented. FPGA components are written in VHDL language. In the end, the implementation is evaluated and possible continuation of this work is stated.

Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). The purpose of this degree project is to research and develop a proof of concept for in-house development of an image injection solution (IIS) on the IU in the HIL testing environment. A proof of concept could confirm that editing, customizing, and having full control of the IU is a possibility. This project was initiated by Volvo Cars to optimize the use of the HIL testing environment currently available, making the environment more changeable and controllable while the IIS remains a static system. The IU is an MPSoC/FPGA based design that uses primarily Xilinx hardware and software (Vivado/Vitis) to achieve the necessary requirements for image injection in the HIL testing environment. It consists of three stages in series: input, image processing, and output. The whole project was divided in three parts based on the three stages and carried out at Volvo Cars in cooperation by three students, respectively. The author of this thesis was responsible for the output stage, where the main goal was to find a solution for converting, preferably, AXI4 RAW12 image data into data on CSI2 format. This CSI2 data can then be used as input to serializers, which in turn transmit the data via fiber-optic cable on GMSL2 format to the VCU. Associated with the output stage, extensive simulations and hardware tests have been done on a preliminary solution that partially worked on the hardware, producing signals in parts of the design that could be read and analyzed. However, a final definite solution that fully functions on the hardware has not been found, because the work is at the initial phase of an advanced and very complex project. Presented in this thesis is: important theory regarding, for example, protocols CSI2, AXI4, GMSL2, etc., appropriate hardware selection for an IIS in HIL (FPGA, MPSoC, FMC, etc.), simulations of AXI4 and CSI2 signals, comparisons of those simulations with the hardware signals of an implemented design, and more. The outcome was heavily dependent on getting a certain hardware (TEF0010) to transmit the GMSL2 data. Since the wrong card was provided, this was the main problem that hindered the thesis from reaching a fully functioning implementation. However, these results provide a solid foundation for future work related to image injection in a HIL environment.