Les activités liées au développement d’objets connectés munis d’intelligence embarquée ont connu un essor considérable ces dernières années, en particulier pour les applications médicales. Dans ce contexte, une course effrénée s’est engagée entre les pionniers de l’IoT afin d’offrir des produits toujours plus performants. Smartphones, bracelets ou textile intelligent, tous intègrent un panel de capteurs multifonctionnels. Il est envisageable alors d’implémenter dans ces produits des solutions permettant de mesurer les signaux physiologiques en continu. En effet, ces signaux émis par le corps humain représentent une source riche d’informations que peut exploiter le corps médical pour le diagnostic ou la prévention d’une pathologie. Les maladies cardiovasculaires, étant la première cause de mortalité dans le monde, le diagnostic précoce de ces maladies est important et des solutions peuvent être apportées par les nouvelles technologies. Ainsi, les pathologies liées aux troubles du rythme cardiaque peuvent être décelées par une analyse inter-battements cardiaques en continu. En effet, l’analyse de la variabilité de la fréquence cardiaque représente un indicateur pertinent sur le fonctionnement cardiovasculaire. Or, cette pertinence dépend en grande partie de l’intelligibilité de l’information mesurée. La pertinence des algorithmes utilisés n’ayant pas été étudiée dans la littérature en fonction du niveau de bruit, la détection des battements cardiaques constitue donc un défi de taille lorsque celle-ci est effectuée en environnement non-maitrisé à partir de dispositifs embarqués et ce travail de thèse a essayé d’apporter des réponses concrètes à cette problématique. / Activities related to the development of connected objects with on-board intelligence have undergone considerable growth in recent years, especially for medical applications. In this context, a frantic race has begun between the pioneers of the IoT in order to offer ever moreefficient and intelligent products. Smartphones, wristbands or smart textiles all incorporate a panel of multifunctional sensors. According to the predictions of the Allied Market Research, the annual growth rate for sensors will reach 11.3% by 2022. The vital signs emitted by thehuman body represent a rich source of information that can be exploited by the medical corps for the diagnosis or prevention of a pathology of interest. Cardiovascular disease, being the second cause of death in the world, reminds us of the importance of a rigorous diagnosis.Pathologies related to heart rhythm disorders are generally detected by cardiac cross-heartbeat analysis. The detection of these beats is one of the most important axes of research in the field of electrocardiogram treatment. Indeed, the analysis of heart rate variability is a relevantindicator of cardiovascular functioning. This relevance depends, in large part, on the intelligibility of the measured information and the signal-to-noise ratio of the parameter of interest. The detection of heartbeats is a daunting challenge when it is carried out from onboarddevices especially in noisy environments.

Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degree of reconfigurability to accommodate rapid evolution in applications features. In addition, low power consumption requirement is also very stringent for many video applications. The conventional custom hardware implementations of video applications deliver high performance at low power consumption while the recent MPSoC implementations enable high degree of interoperability and are useful to support application evolution. In this thesis, we combine the best features of custom hardware and MPSoC approaches to design a Polymorphic ASIC. A Polymorphic ASIC is an integrated circuit designed to meet the requirements of several applications belonging to a particular domain. A polymorphic ASIC consists of a fabric of computation, storage and communication resources, using which applications are composed dynamically. Although different video applications differ widely in the internal de-tails of operation, at the heart of almost every video application is a video codec (encoder and decoder). The requirements of scalability, high performance and low power consumption are very stringent for video decoding. Therefore this thesis focuses mainly on the architectural design of a Polymorphic ASIC for video decoding. We present an unified software and hardware architecture (USHA) for Polymorphic ASIC. USHA is a tiled architecture which uses loosely coupled processor and hardware tiles that are software programmable and hardware reconfigurable respectively. The distinctive feature of Polymorphic ASIC is the static partitioning of the application and dynamic mapping of ap-plication processes onto the computational tiles. Depending on the application scenarios, a process may be mapped onto one of the hardware or processor tiles. Polymorphic ASIC incor-porates a network–on–chip (NoC) to achieve flexible communication across different tiles. Formulation of a programming framework for Polymorphic ASIC requires an implementation model that captures the structure of video decoder applications as well as the properties of the Polymorphic ASIC architecture. We derive an implementation model based on a combination of parametric polyhedral process networks, stream based functions and windowed dataflow models of computation. The implementation model leads to a process network oriented compilation flow that achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi–processor, semi hardware and full hardware configurations of a video decoder. The thesis also presents an application QoS aware scheduler that selects a decoder configuration that best meets the application performance requirements, thereby enabling dynamic performance scaling. The memory hierarchy of Polymorphic ASIC makes use of an application specific cache. Through a combined analysis of miss rate and external memory bandwidth, we show that the degradation in decoder performance due to memory stall cycles depends on the properties of the video being decoded as well as the behavior of the external memory interface. Based on this observation, we present the design of a reconfigurable 2–D cache architecture which can adjust its parameters in accordance with the characteristics of the video stream being decoded. We validate the Polymorphic ASIC using a proof–of–concept implementation on an FPGA. The performance of H.264 decoder on Polymorphic ASIC is evaluated for uniprocessor, multi processor, hardware accelerated and full hardware configurations. The scaling in performance delivered by these configurations shows that the Polymorphic ASIC enables the application to achieve super linear speedups [1]. The experimental results show that different implementations of a H.264 video decoder on the Polymorphic ASIC can deliver performance comparable to a wide spectrum of devices ranging from embedded processor like ARM 9 to MPSoCs like IBM Cell. We also present the energy consumption of various configurations of video decoders on Polymorphic ASIC and an application to configuration mapping aimed at minimizing the overall energy consumption of a Polymorphic ASIC.

Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degree of reconfigurability to accommodate rapid evolution in applications features. In addition, low power consumption requirement is also very stringent for many video applications. The conventional custom hardware implementations of video applications deliver high performance at low power consumption while the recent MPSoC implementations enable high degree of interoperability and are useful to support application evolution. In this thesis, we combine the best features of custom hardware and MPSoC approaches to design a Polymorphic ASIC. A Polymorphic ASIC is an integrated circuit designed to meet the requirements of several applications belonging to a particular domain. A polymorphic ASIC consists of a fabric of computation, storage and communication resources, using which applications are composed dynamically. Although different video applications differ widely in the internal de-tails of operation, at the heart of almost every video application is a video codec (encoder and decoder). The requirements of scalability, high performance and low power consumption are very stringent for video decoding. Therefore this thesis focuses mainly on the architectural design of a Polymorphic ASIC for video decoding. We present an unified software and hardware architecture (USHA) for Polymorphic ASIC. USHA is a tiled architecture which uses loosely coupled processor and hardware tiles that are software programmable and hardware reconfigurable respectively. The distinctive feature of Polymorphic ASIC is the static partitioning of the application and dynamic mapping of ap-plication processes onto the computational tiles. Depending on the application scenarios, a process may be mapped onto one of the hardware or processor tiles. Polymorphic ASIC incor-porates a network–on–chip (NoC) to achieve flexible communication across different tiles. Formulation of a programming framework for Polymorphic ASIC requires an implementation model that captures the structure of video decoder applications as well as the properties of the Polymorphic ASIC architecture. We derive an implementation model based on a combination of parametric polyhedral process networks, stream based functions and windowed dataflow models of computation. The implementation model leads to a process network oriented compilation flow that achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi–processor, semi hardware and full hardware configurations of a video decoder. The thesis also presents an application QoS aware scheduler that selects a decoder configuration that best meets the application performance requirements, thereby enabling dynamic performance scaling. The memory hierarchy of Polymorphic ASIC makes use of an application specific cache. Through a combined analysis of miss rate and external memory bandwidth, we show that the degradation in decoder performance due to memory stall cycles depends on the properties of the video being decoded as well as the behavior of the external memory interface. Based on this observation, we present the design of a reconfigurable 2–D cache architecture which can adjust its parameters in accordance with the characteristics of the video stream being decoded. We validate the Polymorphic ASIC using a proof–of–concept implementation on an FPGA. The performance of H.264 decoder on Polymorphic ASIC is evaluated for uniprocessor, multi processor, hardware accelerated and full hardware configurations. The scaling in performance delivered by these configurations shows that the Polymorphic ASIC enables the application to achieve super linear speedups [1]. The experimental results show that different implementations of a H.264 video decoder on the Polymorphic ASIC can deliver performance comparable to a wide spectrum of devices ranging from embedded processor like ARM 9 to MPSoCs like IBM Cell. We also present the energy consumption of various configurations of video decoders on Polymorphic ASIC and an application to configuration mapping aimed at minimizing the overall energy consumption of a Polymorphic ASIC.

La mesure de distance et la détection d'objets sont devenues essentielles dans de nombreux domaines tels que l'automobile ou la robotique, les applications médicales, les procédés industriels et agricoles, les systèmes de surveillance et de sécurité, etc. Dans le but d'améliorer les performances des dispositifs de télémétrie laser en terme de bruit et de diaphonie, une technique hétérodyne par mélange optoélectronique doit être utilisée. Par ailleurs, l'aspect système embarqué nécessite une réduction de l'encombrement et de la consommation à performances égales. L'intégration de mélangeurs optoélectroniques en technologie CMOS apporte donc une solution optimale à cette approche grâce à ses multiples avantages (intégration du circuit d'instrumentation sur la même puce, modèles bien connus, coût raisonnable, performances élevées,…). Ainsi cette thèse traitera de l'étude de mélangeurs optoélectroniques en technologie CMOS pour la télémétrie embarquée haute résolution. Le premier chapitre de ce manuscrit présente les diverses technique de mesure de distance par télémétrie laser par et justifie le choix de la télémétrie laser par déphasage ainsi que le gain en performances lié à l'hétérodynage. Le second chapitre décrit les mélangeurs électriques et optoélectroniques ainsi que les propriétés nécessaires à leur réalisation. Quelques photodétecteurs y sont présentés au vu de la possibilité de les utiliser en mélangeurs optoélectroniques et d'une intégration potentielle en technologie CMOS. Les principales contraintes liées à l'intégration en technologie CMOS de photocapteurs utilisables en mélangeurs optoélectroniques, sont exposés dans la troisième partie. Les travaux de conception et d'optimisation des structures ainsi que les phases de simulations et de test y sont détaillés. Enfin, pour valider expérimentalement les études précédentes, le dernier chapitre présente la conception d'une chaîne de mesure multivoies pour une tête de photoréception CMOS matricée pour un télémètre laser embarqué haute résolution. / Distance measurement and object detection has become essential in many fields such as automotive and robotics, medical applications, industrial processes and farming systems, surveillance and security, etc.. In order to improve the performance of laser ranging devices in terms of noise and crosstalk, an optoelectronic heterodyne technique of mixing should be used. Moreover, the aspect of embedded system requires a reduction in the size and power consumption for the same performance. The integration of optoelectronic mixers in CMOS technology will provide an optimal solution to this approach through its many advantages (integrated instrumentation circuit on the same chip, well-known models, reasonable cost, high performance, ...). Thus this thesis will focus on the study of optoelectronic mixers in CMOS technology for high resolution, embedded laser range finding systems. The first chapter of this thesis discusses the various technique of distance measurement by laser ranging and justifies the choice of phase shift technique and the gain in performance related to heterodyning. The second chapter describes the electrical and optoelectronic mixers and the properties needed to develop them. Some photodetectors are presented given the opportunity to use optoelectronic mixers and a potential integration with CMOS technology. The main constraints to the integration of CMOS photosensors used in optoelectronic mixers are set out in Part III. The work of design and optimization of structures and phases of simulations and testing are detailed. Finally, to experimentally confirm the earlier studies, the final chapter presents the design of a measuring head for a multichannel photoreceptor CMOS for a high resolution laser range finder.

L'exploration du système solaire et l'étude de l'univers lointain sont encore sources de découvertes et de mystère pour la communauté scientifique et pour l’humanité en général. Ces observations sont actuellement principalement basées sur la mesure d’ions et de particules in-situ qui constituent ces milieux. Les instruments d’observation intègrent des détecteurs spatiaux, utilisés pour convertir l'énergie des particules en charges électriques mesurables. Ces derniers sont étroitement liés à leur électronique analogique ou Analog-Front-End (AFE) et cette combinaison forme des chaines astrophysiques de détection appelées « sensor heads ». Depuis quelques années, la volonté d’améliorer les résolutions spatiale et spectrale des détecteurs nécessite la conception d’une électronique intégrée multivoies. Ainsi, une électronique spatiale de type Application Specific Integrated Circuit (ASIC) doit être développée. Cela permet d’une part de s’adapter au mieux à chaque détecteur pour en optimiser les performances ; et d’autre part de bénéficier des multiples avantages inhérents à l’utilisation d’une technologie CMOS : diminuer les dimensions et les temps de transit des signaux, intégration multifonctions, réduction des coûts pour une fabrication de masse et effets parasites étudiés et bien connus. Cependant les contraintes spatiales exigent une qualification draconienne du circuit. En effet, ces environnent radiatifs peuvent endommager les systèmes électroniques embarqués à bord des missions spatiales. Grâce à la réduction des dimensions, il ne semble plus opportun aujourd’hui d’utiliser des technologies dédiées au spatial (type SOI ou biCMOS spécifiques) mais plutôt de mettre en œuvre des techniques de durcissement par design (RHBD) sur des technologies standards qui sont moins onéreuses et plus performantes. L’objectif de cette thèse est la conception de nouvelles chaînes d’instrumentations intégrées multivoies pour le spatial. Ce travail, co-financé par le CNES et le CNRS, s’est inscrit dans le cadre d’un projet soutenu par le Réseau Thématique de Recherche Avancée Sciences et Technologies pour l’Aéronautique et l’Espace (RTRA STAE) entre 2008 et 2011, intitulé CASA (Chaines AStrophysiques et leur instrumentation Associée). Au cours de cette thèse nous avons conçu 2 ASICs associés à 2 types de détecteurs spatiaux bien distincts. Le premier permet de compter les électrons en sortie d’une microchannel plate (MCP) tandis que le deuxième permet de quantifier le niveau d’énergie perdu par les e- en pénétrant dans un SC. L’étude de ces différents détecteurs doit d’abord être faite afin de les modéliser pour une parfaite adéquation avec leur électronique de détection. Ensuite, une optimisation des chaînes de conversion en vitesse, bruit et consommation est réalisée. Enfin, une méthodologie de savoir faire au niveau du traitement des informations doit être développée pour pérenniser l’expérience emmagasinée durant ces travaux. / The solar system exploration and study of the distant universe are still sources of discovery and mystery to the scientific community and for humanity in general. These observations are currently mainly based on the measurement of ions and particles in-situ forming these environments. The observation instruments incorporate spatial sensors, used to convert particles energy into electrical charges measurable. These are closely related to their electronic analog or Analog-Front-End (AFE) and the combination form chains astrophysical detection called "sensor heads". In recent years, the desire to improve the spatial and spectral resolution detectors requires the design of a multichannel integrated electronics. Thus, a spatial-type electronic Application Specific Integrated Circuit (ASIC) should be developed. This allows one hand to best adapt to each detector to optimize performance, and on the other hand to benefit from multiples advantages inherent in the use of CMOS technology: reducing the size and transit time signals, multi-function integration, cost reduction for mass production and interference effects studied and well known. However, the spatial constraints require a drastic qualification of the circuit. Indeed, the surrounding radiation can damage electronic systems on board the space missions. By reducing the size, it seems more appropriate today to use technologies for the space (or BiCMOS SOI specific) but rather to implement hardening design techniques (RHBD) on standard technologies that are less expensive and more efficient. The objective of this thesis is the design of new integrated multi-channel instrumentation for space. This work, co-funded by CNES and CNRS, has registered as part of a project supported by the Advanced Research Thematic Network Science and Technology for Aeronautics and Space (RTRA STAE) between 2008 and 2011, called CASA (Channels Astrophysics and their associated instrumentation). In this thesis we have designed two ASICs associated with two types of distinct space detectors. The first is used to count the electrons at the output of a MicroChannel Plate (MCP) and the second quantifies the amount of energy lost by e- by entering in a SC. The study of these different sensors must first be made to model them for a perfect match with their detection electronics. Then the chain optimization in conversion speed, noise and consumption is achieved. Finally, a methodology of knowledge in the processing of information must be developed to sustain the experience stored in this work.

Le sujet de thèse propose une nouvelle génération de réseaux de capteur sans fil base sur impulse radio ultra wide band (IR-UWB) reconfigurable suivant l'application souhaitée et à très basse consommation. La consommation énergétique d’un système de communication sans fil est la contrainte majeure pour le déploiement d’un réseau de capteurs sans fil autonome. Les travaux de recherche présente dans cette thèse ont menés au développement d’un émetteur-récepteur à très faible consommation d’énergie pour les réseaux de capteurs sans fil autonome pour des applications de structural Heath monitoring dans des domaines aéronautique. Une description est faite pour les différents types de technologie de communication sans fil pour la surveillance des structures (SHM). Nous avons détaillé la communication sans fil ultra large bande (UWB) en présentant la technique de communication sans fil UWB par impulsion avec les avantages qu’elle offre pour notre application. Une présentation est faite de l’architecture de l’émetteur-récepteur IR-UWB conçu en détaillant le design complet avec l’intégration de la solution proposée clock-gating pour un système à une grande efficacité énergétique avec une implémentation et validation d’un prototype sur une plateforme FPGA. Une description de la conception et la fabrication d’un système sur puce ASIC de notre design d’émetteur-récepteur IR-UWB avec la technologie CMOS 65nm de st microélectronique et les avantages qu’il offre que ça soit en terme d’efficacité énergétique ou de taille de système. / This Ph.D. Subject proposes the design of a new generation of wireless sensor networks (WSN) based on impulse radio ultra-wide band (IR-UWB), reconfigurable upon the application, reliable and ultra-low power. Applications like structure health monitoring of aerospace structures or portable smart sensing systems for human protection can be targeted. These industrial applications impose very demanding specifications for the wireless communication protocol (in some cases, new services are needed like: localization, clock synchronization, real-time transmission, etc) on one side, and for the circuit design, on the other side, as the ultra-low power circuits are needed. Energy efficiency is the major driver in today development of the wireless sensor networks. We chose impulse radio ultra-wideband (IR-UWB) technique for our developments. IR-UWB is a very promising technique able to respond to the wireless communication protocol constraints and to energy efficiency constraints.! The objective of this Ph.D. will be to design an ultra-low power IR-UWB transceiver. IR-UWB signal processing techniques has to be study and innovator solution has to be proposed for the implementation of the IR-UWB transceiver. The first prototype will be developed on FPGA boards (and/or USRP boards) and the final IR-UWB transceiver will be an ASIC in CMOS technology. The design of an ultra-low power consumption of the CMOS transceiver will be a major concern. Modern ultra-low power circuit techniques from the nanometrics CMOS design kits will be used. MAC layer adapted to the demands of the application and working on IR-UWB physical layer will be also studied and designed. A microprocessor integration on the chip for power management of the different parts (sensor, communication, computing, energy harvesting) of the system can also be studied. This work will be based on the previous research results obtained in our team in the case of static WSN. This work will take plac! e in the highly stimulating and competitive environment of a E! uropean project.

Extreme Universe Space Observatory on Japanese Experiment Module (JEM-EUSO) est conçu comme l’expérience de rayons cosmiques de prochaine génération pour observer les particules hautement énergétiques au-dessus de 10²⁰ eV. Le projet est mené par RIKEN et soutenu par une collaboration de plus de 200 membres provenant de 13 pays. Cet observatoire, sous la forme d'un télescope fluorescent, sera arrimé à la Station Spatiale internationale (ISS) pour un lancement prévu en 2017. En observant les gerbes atmosphériques produites dans la troposphère, à une altitude de 400 km, cet observatoire de rayons cosmique offrira une grande surface de détection, qui est au moins 100 fois supérieur que le plus grand détecteur de rayons cosmiques jamais construit. La surface focale de JEM-EUSO sera équipée d'environ 5000 unités de photomultiplicateur multianode 8x8 pixels (MAPMT). Un circuit intégré (ASIC), connu sous le nom SPACIROC, a été proposé pour la lecture du MAPMT. Cet ASIC de 64 voies propose des fonctionnalités comme le comptage de photons, la mesure des charges et le transfert de données à haute vitesse. Par-dessus tout, cet ASIC doit peu consommé afin de respecter la contrainte de puissance de JEM-EUSO. Réalisé en utilisant la technologie AMS Silicium-Germanium (SiGe) 0,35 µm, cet ASIC intègre 64 canaux de comptage de photons rapides (Photon Counting). La résolution de temps pour le comptage de photons est de 30 ns, ce qui permettra d’atteindre la valeur maximale comptage qui est de l'ordre de 10⁷ photons / s. Le système de mesure de charge est basé sur le Time-Over-Threshold qui offre 8 canaux de mesure. Chaque canal de mesure est une somme des 8 pixels du MAPMT et il est prévu que ce système est capable de mesurer jusqu'à 200 pC. La partie numérique fonctionne en continu et gère la conversion des données de chaque voie des blocs de Photon Counting et Time-Over-Threshold. Les données numériques sont transmises par l'intermédiaire de liaisons parallèles dédiées et ces opérations sont effectuées pendant une fenêtre de communication ou « Gate Time Unit » (GTU) de fréquence 400 kHz. Le taux de transfert des données d’ASIC avoisine les 200 Mbps ou 576 bits / GTU. La dissipation de puissance est strictement inférieure à 1 mW par canal ou 64 mW pour l'ASIC. Le premier prototype de SPACIROC a été envoyé pour fabrication en Mars 2010 au Centre Multi Projet (CMP). Des puces nues et packagés ont été reçues en Octobre 2010, ce qui a débuté la phase de caractérisation de cet ASIC. Après une phase de test réussie, des puces SPACIROC ont été intégrés dans l'électronique frontale d'un instrument pour détecter les sursauts gamma - Ultra Fast Flash Observatoire (UFFO) qui va être lancé en 2013. Vers la fin de l'année 2012, des cartes électroniques frontales conçues autour des puces SPACIROC ont été fabriqués pour le projet EUSO-Balloon. Ce projet de vol en ballon stratosphérique à une altitude de 40 km servira comme le démonstrateur technologique et l'ingénierie d'un instrument miniaturisé JEM-EUSO. La deuxième génération de cet ASIC a été envoyée à la fonderie en Décembre 2011. Ce second prototype, SPACIROC2, a été testé à partir de mai 2012. Les principales améliorations sont les suivantes: la consommation d'énergie a été revue à la baisse, ainsi que l'amélioration de la résolution temporelle de Photon Counting et l'extension de la gamme dynamique pour le module Time-Over-Threshold. Les mesures en cours ont montré que SPACIROC2 présente un bon comportement général et apporte des améliorations par rapport à son prédécesseur. / Extreme Universe Space Observatory on Japanese Experiment Module (JEM-EUSO) is conceived as the next generation cosmic rays experiment for observing the highly energetic particles above 5.10¹⁹ eV. The project is lead by RIKEN and supported by an active collaboration of more than 200 members from 13 countries. This observatory, in the shape of a wide field-of-view UV telescope, will be attached to the International Space Station (ISS) for a planned launch in 2017. Observing the Air Showers generated in troposphere from an altitude of 400 km, this space based cosmic rays experiment will offer a very large instantaneous detection surface, which is at least 100 times bigger than the largest land based cosmic rays observatory. The detection surface of JEM-EUSO will be equipped with around 5000 units of 8x8 pixels Multianode Photomultiplier (MAPMT). A radiation hardened mixed signal application-specific integrated circuit (ASIC), known as SPACIROC, has been proposed for reading out the MAPMT. This ASIC features 64-channel analog inputs, fast photon counting capabilities, charge measurements and high-speed data transfer. Above all, the power dissipation of this ASIC is required to be very low in order to comply with the strict power budget of JEM-EUSO. By taking the advantages of high speed AMS 0.35 µm Silicon-Germanium (SiGe) process, this ASIC integrates 64 fast Photon Counting channels. The photon counting time resolution is 30 ns, which allows the theoretical counting rate in the order of 10⁷ photons/s. The charge measurement system is based on Time-Over-Threshold which offers 8 measurement channels. Each measurement channel is composed of 8 pixels of the MAPMT and it is expected that this system will measure up to 200 pC. The digital part is then required to operate continuously and handles data conversion of each Photon Counting and Time-Over-Threshold channel. For the first version of this ASIC, one channel measurement channel for the dynode is also available. The digital data are transmitted via dedicated parallel communication links and within the defined Gate Time Unit (GTU) of 400 kHz frequency. The ASIC data output rate is in the vicinity of 200 Mbps or 576 bits/GTU. The power dissipation is kept strictly below 1 mW per channel or 64 mW for the ASIC. The first prototype of SPACIROC was sent for tapeout in March 2010 through Centre Multi Projet (CMP) prototyping services. The packaged ASICs and bare dies have been received in October 2010 which marked the characterization phase of this chip. After successful testing phase, SPACIROC chips were integrated into the front-end electronics of an instrument pathfinder for detecting the gamma ray bursts – Ultra Fast Flash Observatory (UFFO) which is foreseen to be launched in 2013. Towards the end of 2012, front-end board designed around SPACIROC chips have been fabricated for the EUSO-Balloon project. This balloon borne project will serve as a technical and engineering demonstrator of a fully miniaturized JEM-EUSO instrument which will be flown to the stratosphere at the altitude of 40 km. The second tapeout of this ASIC was done in December 2011. This second prototype, SPACIROC2, was tested from May 2012. The main improvements are as follows: lower power consumption due to better power management, enhancement in Photon Counting time resolution and extension the Time-Over-Threshold maximum input rate. The ongoing tests have shown that SPACIROC2 exhibits a good overall behavior and improvement compared to its predecessor.

One of the open questions of artificial computer vision is how to produce good internal representations of the visual world. What sort of internal representation would allow an artificial vision system to detect and classify objects into categories, independently of pose, scale, illumination, conformation, and clutter ? More interestingly, how could an artificial vision system {em learn} appropriate internal representations automatically, the way animals and humans seem to learn by simply looking at the world ? Another related question is that of computational tractability, and more precisely that of computational efficiency. Given a good visual representation, how efficiently can it be trained, and used to encode new sensorial data. Efficiency has several dimensions: power requirements, processing speed, and memory usage. In this thesis I present three new contributions to the field of computer vision:(1) a multiscale deep convolutional network architecture to easily capture long-distance relationships between input variables in image data, (2) a tree-based algorithm to efficiently explore multiple segmentation candidates, to produce maximally confident semantic segmentations of images,(3) a custom dataflow computer architecture optimized for the computation of convolutional networks, and similarly dense image processing models. All three contributions were produced with the common goal of getting us closer to real-time image understanding. Scene parsing consists in labeling each pixel in an image with the category of the object it belongs to. In the first part of this thesis, I propose a method that uses a multiscale convolutional network trained from raw pixels to extract dense feature vectors that encode regions of multiple sizes centered on each pixel. The method alleviates the need for engineered features. In parallel to feature extraction, a tree of segments is computed from a graph of pixel dissimilarities. The feature vectors associated with the segments covered by each node in the tree are aggregated and fed to a classifier which produces an estimate of the distribution of object categories contained in the segment. A subset of tree nodes that cover the image are then selected so as to maximize the average "purity" of the class distributions, hence maximizing the overall likelihood that each segment contains a single object (...) / One of the open questions of artificial computer vision is how to produce good internal representations of the visual world. What sort of internal representation would allow an artificial vision system to detect and classify objects into categories, independently of pose, scale, illumination, conformation, and clutter ? More interestingly, how could an artificial vision system {em learn} appropriate internal representations automatically, the way animals and humans seem to learn by simply looking at the world ? Another related question is that of computational tractability, and more precisely that of computational efficiency. Given a good visual representation, how efficiently can it be trained, and used to encode new sensorial data. Efficiency has several dimensions: power requirements, processing speed, and memory usage. In this thesis I present three new contributions to the field of computer vision:(1) a multiscale deep convolutional network architecture to easily capture long-distance relationships between input variables in image data, (2) a tree-based algorithm to efficiently explore multiple segmentation candidates, to produce maximally confident semantic segmentations of images,(3) a custom dataflow computer architecture optimized for the computation of convolutional networks, and similarly dense image processing models. All three contributions were produced with the common goal of getting us closer to real-time image understanding. Scene parsing consists in labeling each pixel in an image with the category of the object it belongs to. In the first part of this thesis, I propose a method that uses a multiscale convolutional network trained from raw pixels to extract dense feature vectors that encode regions of multiple sizes centered on each pixel. The method alleviates the need for engineered features. In parallel to feature extraction, a tree of segments is computed from a graph of pixel dissimilarities. The feature vectors associated with the segments covered by each node in the tree are aggregated and fed to a classifier which produces an estimate of the distribution of object categories contained in the segment. A subset of tree nodes that cover the image are then selected so as to maximize the average "purity" of the class distributions, hence maximizing the overall likelihood that each segment contains a single object. The system yields record accuracies on several public benchmarks. The computation of convolutional networks, and related models heavily relies on a set of basic operators that are particularly fit for dedicated hardware implementations. In the second part of this thesis I introduce a scalable dataflow hardware architecture optimized for the computation of general-purpose vision algorithms, neuFlow, and a dataflow compiler, luaFlow, that transforms high-level flow-graph representations of these algorithms into machine code for neuFlow. This system was designed with the goal of providing real-time detection, categorization and localization of objects in complex scenes, while consuming 10 Watts when implemented on a Xilinx Virtex 6 FPGA platform, or about ten times less than a laptop computer, and producing speedups of up to 100 times in real-world applications (results from 2011)

Les interfaces cerveau-machine (ICM) permettent de contrôler un appareil électronique grâce aux signaux cérébraux. Plusieurs méthodes de mesure de ces signaux, invasives ou non, peuvent être utilisées. L'électro-encéphalographie (EEG) est la méthode non-invasive la plus étudiée car elle propose une bonne résolution temporelle et le matériel nécessaire est bien moins volumineux que les systèmes de mesure des champs magnétiques.L'EEG a cependant une faible résolution spatiale, ce qui limite les performances des ICM utilisant cette méthode de mesure. Ce souci de résolution spatiale peut être réglé en utilisant le problème inverse de l'EEG, qui permet de passer des potentiels mesurés en surface à une distribution volumique des sources de courant dans le cerveau. Le principal verrou de cette technique est le temps nécessaire (plusieurs heures) pour calculer avec une station de travail la matrice permettant de résoudre leproblème inverse. Dans le cadre de cette thèse, nous avons étudié les solutions actuelles pour accélérer matériellement la conception de cette matrice. Nous avons ainsi proposé, conçu et testé une architecture électronique dédiée à ces traitements pour ICM. Les premiers résultats démontrent que notre solution permet de passer de plusieurs heures de calcul sur une station de travail à quelques minutes sur circuit reconfigurable. Cette accélération des traitements d'imagerie par EEG facilitera grandement la recherche sur l'utilisation du problème inverse et ouvrira ainsi de nouvelles perspectives pour le domaine de l'ICM. / Brain-Computer Interfaces (BCI) are systems that use brain activity to control an external device. Various techniques can be used to collect the neural signals. The measurement can be invasive ornon-invasive. Electroencephalography (EEG) is the most studied non-invasive method. Indeed, EEG offers a fine temporal resolution and ease of use but its spatial resolution limits the performances of BCI based on EEG. The spatial resolution of EEG can be improved by solving the EEG inverse problem, which allows to determine the distribution of electrical sources in the brain from EEG. Currently, the main difficulty is the time needed(several hours) to compute the matrix which is used to solve the EEG inverse problem. This document describes the proposed solution to provide a hardware acceleration of the matrix computation. A dedicated electronic architecture has been implemented and tested. First results show that the proposed architecture divides the calculation time by a factor of 60 on a programmable circuit. This acceleration opens up new perspectives for EEG BCI.

La maladie de Parkinson est la seconde maladie neuro-dégénérative la plus fréquente à travers le monde. Dans ce contexte, le projet de recherche associé à cette thèse vise à améliorer le traitement symptomatique de la maladie de Parkinson, par le développement de procédés de stimulation cérébrale profonde adaptative. Le travail de cette thèse repose sur la conception d’un ASIC d’enregistrement et de traitement de signaux neuronaux, répondant à divers enjeux :un traitement continu et en temps réel focalisé sur des bandes spécifiques très basses-fréquences et largement configurables. L’objectif est d’utiliser l’information traitée pour le contrôle et la génération d’un signal de stimulation. Cet ASIC a été développé, caractérisé électroniquement et utilisé dans un contexte in vivo. Un système en boucle fermée a été réalisé à partir de cet ASIC, se montrant fonctionnel. Ces validations expérimentales in vivo ouvrent de nombreuses possibilités d’investigation du concept de stimulation cérébrale en boucle fermée. / Parkinson’s disease is the second most common neurodegenerative diseases throughout theworld. In this context, the research project associated with this thesis is to improve the symptomatictreatment of Parkinson’s disease through the development process of deep brain stimulationadaptive. The work of this thesis is based on the design of an ASIC for recording andprocessing of neural signals, in response to a variety of issues : ongoing treatment and real-timefocus on specific bands of very low-frequency and highly configurable. The goal is to use theprocessed information to the control and generation of a stimulation signal. This ASIC wasdeveloped, characterized and used electronically in a context in vivo. A closed-loop system wasmade from the ASIC, showing functional. These in vivo validations open up many possibilitiesfor investigation of the concept of closed-loop brain stimulation.