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Protecting digital circuits against hold time violations due to process variationsNeuberger, Gustavo January 2007 (has links)
Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.
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Desenvolvimento de defasadores baseados em MEMS e linhas de transmissão de ondas lentas para aplicações em 60 GHz. / Development of phase shifters based on shielded CPW and MEMS for 60 GHz.Franz Sebastian Bedoya Llano 28 November 2017 (has links)
Este trabalho, desenvolvido junto ao Grupo de Novos Materiais e Dispositivos (GNMD) pertencente ao Laboratório de Microeletrônica (LME) da Universidade de São Paulo, apresenta a modelagem de um defasador passivo miniaturizado com baixas perdas para aplicações em ondas milimétricas (mmW-milimeter waves). Este defasador é baseado em um conceito inovador utilizando sistemas micro-eletromecânicos (MEMS) distribuídos e linhas de transmissão coplanares de ondas lentas. Este conceito é proposto no projeto Jovem Pesquisador FAPESP (Processo no. 2011/18167-3), ao qual este projeto está vinculado. A defasagem neste tipo de dispositivo é conseguida pela liberação das fitas da camada de blindagem de uma linha de transmissão tipo S-CPW (Shielded-Coplanar Waveguide). As fitas liberadas podem ser movimentadas eletrostaticamente, o que praticamente não consome energia. Este projeto pretende projetar um defasador para fabricação com a tecnologia do Laboratório de Microeletrônica da Escola Politécnica da Universidade de São Paulo. Adicionalmente, este trabalho apresenta resultados experimentais de um processo de fabricação IN-HOUSE baseado na metodologia de integração por flip-chip. A tecnologia de integração implementada é baseada na soldagem de um chip sobre um substrato, no qual são construídos uma nova geração de pilares de cobre finos, cujo espaçamento entre pilares é menor que 100 ?m. Essa redução nas dimensões pode ser usada com a nova geração de dispositivos de comunicações na faixa das mmW. Em termos de fabricação, foram obtidos pilares de cobre altamente miniaturizados com uma altura significativa e uniforme que permite a integração com o chip. Além do mais, os resultados obtidos representam avanços significativos no processo de fabricação que será usado como tecnologia de integração híbrida em um interposer baseado em substrato de alumina nanoporosa (MnM-Metallic Nanowire Membrane). Esse interposer desempenha um papel indispensável no GNMD, já que atualmente estão sendo estudadas suas propriedades elétricas e já foram construídos dispositivos sobre o substrato com resultados promissores. / This work, performed at the New Materials and Devices Group (GNMD) of the Microelectronics Laboratory of the Polytechnic School of the University of São Paulo, presents the modeling of a miniaturized passive phase shifter with low losses for applications in millimeter waves. It is based on an innovated concept, which uses distributed MEMS phase shifters and slow-wave coplanar wave guides. Such concept is proposed under the FAPESP Youth Researcher project (Process number 2011/18167-3). The phase shifter on this kind of device is achieved by releasing the shielding layer of the Shielded-Coplanar Waveguide. The released ribbons are electrostatically displaced, which does not consume energy. The aim of this project is to design a phase shifter for fabrication with the technology available at the Microelectronics Laboratory. Additionally, this work presents experimental results of a flip-chip fabrication process. This technology is based on next generation of fine pitch copper pillar bumping, with pillar pitch of less than 100 ?m that support next generation of communication devices at the millimeter wave frequency range. From the fabrication point-of-view, highly miniaturized copper pillars with appropriate thicknesses were obtained. Furthermore, the results obtained represent a significant advance in the fabrication process that will be used as a hybrid integration technology on an interposer based on a nanoporous alumina substrate (MnM-Metallic Nanowire Membrane).
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Estudo da difusão e tunelamento planares para a equação de Dirac em presença de potenciais eletrostáticos / Study of planar diffusion and tunneling for the Dirac equation in presence of electrostatic potentialsMaia, Gabriel Gulak, 1988- 19 May 2006 (has links)
Orientadores: Stefano De Leo, Marcelo Moraes Guzzo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Física Gleb Wataghin / Made available in DSpace on 2018-08-23T16:45:38Z (GMT). No. of bitstreams: 1
Maia_GabrielGulak_M.pdf: 1857100 bytes, checksum: 8af9898714b92a166704c01eafe1b9fa (MD5)
Previous issue date: 2013 / Resumo: A interação de elétrons com barreiras de potencial é um problema bem conhecido da teoria quântica não-relativística de Schrödinger. O tratamento intrinsecamente relativístico do sistema, entretanto, por meio da teoria de Dirac, nos revela diferentes aspectos não fornecidos pela teoria precedente. Por exemplo, uma vez que a equação de Dirac contém naturalmente os graus de liberdade de spin, quatro coeficientes são necessários para descrever o processo e assim o fenômeno da inversão de spin, também chamado spin flip, surge. Com o objetivo de introduzir o formalismo teórico e a notação sobre a qual se sustenta este trabalho, o primeiro capítulo é dedicado a uma breve revisão da equação de Dirac, discutindo-se as propriedades de suas matrizes, a equação de continuidade e obtendo-se suas soluções livres. No capítulo 2 o sistema de interesse, a interação planar de partículas de Dirac com barreiras de potencial eletrostático, é apresentado e são destacados os aspectos que o diferenciam de seu equivalente não-relativístico. São definidos os potenciais escalar e eletrostático e as zonas cinemáticas estabelecidas para os casos unidimensional e bidimensional. O terceiro capítulo é reservado à obtenção dos coeficientes de reflexão e transmissão com e sem spin flip para partículas de Dirac difundindo planarmente através de uma barreira quadrada de potencial eletrostático. Este objetivo é alcançado através de dois métodos distintos de interpretações complementares: O método de degraus e o cálculo de barreira. Coeficientes não-nulos são obtidos para todos os casos, exceto para a transmissão através da barreira com inversão de spin, contrastando com o fato de que todos os degraus componentes da barreira apresentam coeficientes associados diferentes de zero. No quarto capítulo analisa-se o spin das partículas incidentes e o efeito da barreira sobre o spin das partículas refletidas. Ainda que o limite para baixas velocidades seja sempre 1/2, como esperado, em regimes relativísticos encontra-se uma dependência do valor médio deste operador com a energia e o ângulo de incidência no potencial. No quinto capítulo o formalismo de pacote de ondas é desenvolvido e a coerência dos pacotes em relação 'a barreira de potencial investigada, mostrando que a probabilidade de transmissão torna-se constante conforme a largura da barreira aumenta, o que caracteriza o regime incoerente de partículas. Ao fim do capítulo são derivadas as expressões para o spin incidente, refletido e transmitido nesse formalismo. Por fim, o sexto capítulo é reservado ao estudo introdutório do valor médio de autoestados do operador de spin através do formalismo desenvolvido no capítulo anterior como primeira mostra das possibilidades de trabalhos futuros. Mostrado que se o bispinor incidente não for um autoestado do Hamiltoniano de Dirac uma dependência temporal é verificada no valor médio / Abstract: The interaction of electrons with potential barriers is a well-known problem of the Schr¨odinger¿s non-relativistic quantum theory. The intrinsically relativistic treatment of the problem, however, through the Dirac¿s theory, reveals us different aspects, do not provided by the preceding theory. For instance, since the Dirac equation naturally contains the spinorial degree of freedom, four coefficients are needed in order to describe the process and so the spin flip phenomenon emerges. To introduce the theoretical formalism and the notation upon which this work is sustained, the first chapter is devoted to a short review of the Dirac equation, discussing the properties of its matrices, the continuity equation and obtaining its free solutions. Chapter 2 presents the system of interest, the planar interaction of Dirac particles with electrostatic potential barriers. It also highlights the aspects that differentiate this system from its non-relativistic analogue. The scalar and electrostatic potentials are defined and the kinematic zones established for the one-dimensional and the two-dimensional cases. The third chapter is reserved for obtaining the spin flip and spin conserving transmission and reflection coefficients for Dirac particles diffusing two-dimensionally through a square electrostatic potential barrier. This goal is achieved by means of two distinct methods of complementary interpretations: The barrier calculation and the steps calculation. Non-zero coefficients are obtained in all the cases except for the spin flip transmission, contrasting with the fact that no coefficient of the individual steps that compose the barrier is null. In the fourth chapter the incident particles¿ spin is analysed as well as the effect of the barrier on the spin of the reflected particles. As expected the low velocities limits gives us a spin value of 1/2 but in relativistic regime there is a dependence of the spin with the energy and the incidence angle into the potential. In the fifth chapter the wave packet formalism is developed and the packets¿ coherence is investigated, showing that the transmission probability becomes constant as the barrier width becomes greater, characterizing the incoherence of the particle limit. At the end of the chapter the expressions for the incident, reflected and transmitted spin in the new formalism are derived. Finally, the sixth chapter is reserved to the introductory study of mean values of the spin operator eigenstates through the formalism developed in the previous chapter as an example of possibilities for future investigations. It is shown that if the incident bispinor is not a Dirac Hamiltonian eigenstate there is a time dependence in the expected value. Key-words: Relativistic Quantum Mechanics, potential barriers, wave-packets / Mestrado / Física / Mestre em Física
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Design užitkového vozidla / Design of commercial vehiclePaclt, Martin January 2011 (has links)
The master thesis deals with design of a commercial vehicle for urban use. Thesis has complex solution. A small size vehicle uses the hybrid technology to drive with a combination of electric motors in wheels and the Wankel engine. Thesis gives some innovative solutions of daily required functions. A sliding door can be operated by a legs. A flip roof allows enlarging the commercial space. A swiveling front and rear axle for better maneuverability in the city. The main aim of the design is to remove the front mask of the vehicle.
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Numerical modeling of a slotted flip bucket spillway system – The Shibuya Hydropower Project. / Numerisk modellering av ett skidbacksutskov i Shibuya vattenkraftsystem.Axelsson, Johan, Knutsson, Roger January 2011 (has links)
CFD is today a big part of the design process in hydraulic engineering and is more economical and time efficient than traditional scale models. But, there are still issues concerning the agreement with scale models in large and complex geometries. In this degree project a high head, five channeled, slotted flip bucket spillway system is analyzed with the CFD software FLUENT and compared with existing scale model results. The sought hydraulic parameters in each channel were the discharge capacity, the pressure distribution and the throw distance from the flip buckets. The discharge capacity and pressure distribution was practically equal for all five channels and only the throw distance from Channel 1 deviated from the others. The agreement with data from the scale model is quite low. The biggest error sources behind the bad agreement may depend on the lack of computational power which led to bad choice of cell size, model delimitations and simplifications. CFD models can easily be built up by people without experience in hydraulics which can lead to fatal errors when building up the model and interpreting results. Hence, long experience in CFD or verification of the numerical results with several different hydraulic parameters is the only way to guarantee qualitative results from CFD modeling.
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Resiliency Mechanisms for In-Memory Column StoresKolditz, Till 15 February 2019 (has links)
The key objective of database systems is to reliably manage data, while high query throughput and low query latency are core requirements. To date, database research activities mostly concentrated on the second part. However, due to the constant shrinking of transistor feature sizes, integrated circuits become more and more unreliable and transient hardware errors in the form of multi-bit flips become more and more prominent. In a more recent study (2013), in a large high-performance cluster with around 8500 nodes, a failure rate of 40 FIT per DRAM device was measured. For their system, this means that every 10 hours there occurs a single- or multi-bit flip, which is unacceptably high for enterprise and HPC scenarios. Causes can be cosmic rays, heat, or electrical crosstalk, with the latter being exploited actively through the RowHammer attack. It was shown that memory cells are more prone to bit flips than logic gates and several surveys found multi-bit flip events in main memory modules of today's data centers. Due to the shift towards in-memory data management systems, where all business related data and query intermediate results are kept solely in fast main memory, such systems are in great danger to deliver corrupt results to their users. Hardware techniques can not be scaled to compensate the exponentially increasing error rates. In other domains, there is an increasing interest in software-based solutions to this problem, but these proposed methods come along with huge runtime and/or storage overheads. These are unacceptable for in-memory data management systems.
In this thesis, we investigate how to integrate bit flip detection mechanisms into in-memory data management systems. To achieve this goal, we first build an understanding of bit flip detection techniques and select two error codes, AN codes and XOR checksums, suitable to the requirements of in-memory data management systems. The most important requirement is effectiveness of the codes to detect bit flips. We meet this goal through AN codes, which exhibit better and adaptable error detection capabilities than those found in today's hardware. The second most important goal is efficiency in terms of coding latency. We meet this by introducing a fundamental performance improvements to AN codes, and by vectorizing both chosen codes' operations. We integrate bit flip detection mechanisms into the lowest storage layer and the query processing layer in such a way that the remaining data management system and the user can stay oblivious of any error detection. This includes both base columns and pointer-heavy index structures such as the ubiquitous B-Tree. Additionally, our approach allows adaptable, on-the-fly bit flip detection during query processing, with only very little impact on query latency. AN coding allows to recode intermediate results with virtually no performance penalty. We support our claims by providing exhaustive runtime and throughput measurements throughout the whole thesis and with an end-to-end evaluation using the Star Schema Benchmark. To the best of our knowledge, we are the first to present such holistic and fast bit flip detection in a large software infrastructure such as in-memory data management systems. Finally, most of the source code fragments used to obtain the results in this thesis are open source and freely available.:1 INTRODUCTION
1.1 Contributions of this Thesis
1.2 Outline
2 PROBLEM DESCRIPTION AND RELATED WORK
2.1 Reliable Data Management on Reliable Hardware
2.2 The Shift Towards Unreliable Hardware
2.3 Hardware-Based Mitigation of Bit Flips
2.4 Data Management System Requirements
2.5 Software-Based Techniques For Handling Bit Flips
2.5.1 Operating System-Level Techniques
2.5.2 Compiler-Level Techniques
2.5.3 Application-Level Techniques
2.6 Summary and Conclusions
3 ANALYSIS OF CODING TECHNIQUES
3.1 Selection of Error Codes
3.1.1 Hamming Coding
3.1.2 XOR Checksums
3.1.3 AN Coding
3.1.4 Summary and Conclusions
3.2 Probabilities of Silent Data Corruption
3.2.1 Probabilities of Hamming Codes
3.2.2 Probabilities of XOR Checksums
3.2.3 Probabilities of AN Codes
3.2.4 Concrete Error Models
3.2.5 Summary and Conclusions
3.3 Throughput Considerations
3.3.1 Test Systems Descriptions
3.3.2 Vectorizing Hamming Coding
3.3.3 Vectorizing XOR Checksums
3.3.4 Vectorizing AN Coding
3.3.5 Summary and Conclusions
3.4 Comparison of Error Codes
3.4.1 Effectiveness
3.4.2 Efficiency
3.4.3 Runtime Adaptability
3.5 Performance Optimizations for AN Coding
3.5.1 The Modular Multiplicative Inverse
3.5.2 Faster Softening
3.5.3 Faster Error Detection
3.5.4 Comparison to Original AN Coding
3.5.5 The Multiplicative Inverse Anomaly
3.6 Summary
4 BIT FLIP DETECTING STORAGE
4.1 Column Store Architecture
4.1.1 Logical Data Types
4.1.2 Storage Model
4.1.3 Data Representation
4.1.4 Data Layout
4.1.5 Tree Index Structures
4.1.6 Summary
4.2 Hardened Data Storage
4.2.1 Hardened Physical Data Types
4.2.2 Hardened Lightweight Compression
4.2.3 Hardened Data Layout
4.2.4 UDI Operations
4.2.5 Summary and Conclusions
4.3 Hardened Tree Index Structures
4.3.1 B-Tree Verification Techniques
4.3.2 Justification For Further Techniques
4.3.3 The Error Detecting B-Tree
4.4 Summary
5 BIT FLIP DETECTING QUERY PROCESSING
5.1 Column Store Query Processing
5.2 Bit Flip Detection Opportunities
5.2.1 Early Onetime Detection
5.2.2 Late Onetime Detection
5.2.3 Continuous Detection
5.2.4 Miscellaneous Processing Aspects
5.2.5 Summary and Conclusions
5.3 Hardened Intermediate Results
5.3.1 Materialization of Hardened Intermediates
5.3.2 Hardened Bitmaps
5.4 Summary
6 END-TO-END EVALUATION
6.1 Prototype Implementation
6.1.1 AHEAD Architecture
6.1.2 Diversity of Physical Operators
6.1.3 One Concrete Operator Realization
6.1.4 Summary and Conclusions
6.2 Performance of Individual Operators
6.2.1 Selection on One Predicate
6.2.2 Selection on Two Predicates
6.2.3 Join Operators
6.2.4 Grouping and Aggregation
6.2.5 Delta Operator
6.2.6 Summary and Conclusions
6.3 Star Schema Benchmark Queries
6.3.1 Query Runtimes
6.3.2 Improvements Through Vectorization
6.3.3 Storage Overhead
6.3.4 Summary and Conclusions
6.4 Error Detecting B-Tree
6.4.1 Single Key Lookup
6.4.2 Key Value-Pair Insertion
6.5 Summary
7 SUMMARY AND CONCLUSIONS
7.1 Future Work
A APPENDIX
A.1 List of Golden As
A.2 More on Hamming Coding
A.2.1 Code examples
A.2.2 Vectorization
BIBLIOGRAPHY
LIST OF FIGURES
LIST OF TABLES
LIST OF LISTINGS
LIST OF ACRONYMS
LIST OF SYMBOLS
LIST OF DEFINITIONS
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Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-DomesZhao, Peng 12 March 2013 (has links)
No description available.
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Flip-flops ópticos basados en interferómetros Mach-Zehnder activos con realimentaciónClavero Galindo, Raquel 07 May 2008 (has links)
El constante aumento de la capacidad de transmisión de la fibra óptica ha provocado que se estén llevando a cabo numerosos estudios centrados en el procesado óptico de la información digital a alta velocidad. Para poder realizar complejas operaciones de procesado óptico se requiere una memoria óptica de bajo consumo, alta velocidad y que sea integrable. Puesto que no existe el equivalente de las memorias RAM en el domino óptico, surge la necesidad de implementar dispositivos capaces de almacenar información durante un periodo de tiempo indeterminado. Una de las soluciones más atractivas para la implementación de estos sistemas de almacenamiento es el flip-flop óptico. Este dispositivo puede trabajar en dos estados de funcionamiento entre los que se conmuta empleando señales ópticas de control pulsadas.
Entre todas las tecnologías utilizadas en el procesado óptico de la señal destaca el interferómetro Mach-Zehnder basado en el amplificador óptico de semiconductor (SOA-MZI) por su versatilidad y posibilidad de integración.
En esta tesis se propone una arquitectura para implementar un flip-flop óptico basada en un SOA-MZI con un bucle de realimentación. Este dispositivo presenta un comportamiento biestable bajo determinadas condiciones. Sus principales ventajas son una menor complejidad (menor consumo de potencia), velocidad de conmutación y capacidad de integración. Asimismo, se ha desarrollado un modelo teórico para el SOA-MZI con realimentación a partir de las ecuaciones básicas que gobiernan el comportamiento del SOA. Este modelo ha permitido estudiar las características estáticas y dinámicas del sistema.
Finalmente, se han propuesto dos nuevas aplicaciones para la arquitectura del SOA-MZI con realimentación. La primera de ellas consiste en un conmutador espacial 1x2 controlado ópticamente. Es la primera vez que se presenta una configuración que implemente esta funcionalidad en un único bloque. En segundo lugar se propone utilizar el flip-flop junto con una puerta / Clavero Galindo, R. (2007). Flip-flops ópticos basados en interferómetros Mach-Zehnder activos con realimentación [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1958
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Defect-Mediated Trafficking across Cell Membranes: Insights from in Silico ModelingGurtovenko, Andrey A., Anwar, Jamshed, Vattulainen, I. January 2010 (has links)
No / Review article. No abstract.
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UV Magnetic Plasmons in Cobalt NanoparticlesBhatta, Hari Lal 05 1900 (has links)
The main goals of this research were to fabricate magnetic cobalt nanoparticles and study their structural, crystal structure, optical, and magnetic properties. Cobalt nanoparticles with average particle size 8.7 nm were fabricated by the method of high temperature reduction of cobalt salt utilizing trioctylphosphine as a surfactant, oleic acid as a stabilizer, and lithium triethylborohydride as a reducing reagent. Energy-dispersive X-ray spectroscopy (EDX) analysis confirmed the formation of cobalt nanoparticles. High resolution transmission electron microscopy images show that Co NPs form both HCP and FCC crystal structure. The blocking temperature of 7.6 nm Co NPs is 189 K. Above the blocking temperature, Co NPs are single domain and hence showed superparamagnetic behavior. Below the blocking temperature, Co NPs are ferromagnetic. Cobalt nanoparticles with a single-domain crystal structure support a sharp plasmon resonance at 280 nm. Iron nanoparticles with average particle size 4.8 nm were fabricated using chemical reduction method show plasmon resonance at 266 nm. Iron nanoparticles are ferromagnetic at 6 K and superparamagnetic at 300 K.
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