Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

This dissertation investigates the intersection between music, gender, religion, and state agencies in the war against HIV /AIDS in Tanzania. The dissertation explores how music, gender and sexuality, religion, and state agencies impact one another in the creative process of musical and dramatic performances that address the education and prevention of HIV/AIDS. The ethnographic data, which focuses on musical and dramatic performance groups in Bukoba Urban and Rural Districts in Kagera Region, and Dar es Salaam Region, was collected from September 2008–May 2009. The dissertation views performance from multiple perspectives: as an avenue for the production of diverse types of knowledge such as musical, biomedical, religious, and localized or indigenous knowledge about healing in the context of HIV/AIDS; as a space in which gender and religious ideologies and identities are displayed and contested; and finally, as the space in which the manifestations of negotiations of power relations take place. The dissertation shows that health is at the center of music and dramatic performances as they are concerned with the maintenance of individual and community health. By doing so, performances serve as the hub of the social agency in preventing ill health and in restoring the well-being of the individual and communities at large. With regard to music, gender, and sexuality, the dissertation demonstrates that music performance is not only considered an avenue that provides one of the best contexts for observing and understanding the gender structure of any society. Performance is also a space for public discourse on sexuality in the context of HIV/AIDS. The state and religious ideology affect the creative process by either attempting to control meanings or by preventing certain performance. However, such attempts are not always successful. Finally, the dissertation demonstrates that performance is more than space for message-oriented or crowd-attracting activity but serves as a site upon which readings of the social transformation of gender roles through performance can take place. / text

This doctoral thesis contains three empirical research papers that center on the topics of private equity and the role of advisors in mergers and acquisitions. "Your Former Employees Matter: Private Equity Firms and Their Financial Advisors” is a study of how social networks that are formed by previous employment relations affect private equity firms’choice of financial advisors. A financial advisor is more likely to advice on a transaction if a former employee is one of the private equity professionals who constitute the deal team for the particular transaction. In turn, information and deals are sourced to private equity firms from sell-side financial advisors within the previous employment network. "Dual Role Advisors and Conflicts of Interest” focuses on the potential conflicts of interest that may arise when an advisor to a firm targeted in a merger or acquisition is simultaneously involved in financing the bidder. Overall, the results suggest that investment banks in these situations may not have fulfilled their obligation of obtaining the highest possible price on behalf of the seller. "Private Equity Firms and Quick Flip Sales” examines the particulars of quick flip investments and three hypotheses that may explain their prevalence. Private equity firms typically are long term investors, but occasionally exits take place in less than 18 months. Results point to that such quick flips may partly be due to conflicting interests between the limited and general partners. / <p>Diss. Stockholm : Handelshögskolan, 2010. Sammanfattning jämte 3 uppsatser</p>

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d'entretien de type Colpitts,la mise en forme et jusqu'à l'adaptation du signal à sa charge d'utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s'orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del'architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l'avons reportée par flip chip sur une interfacespécifique pour

The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material. Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges. The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The xvi thermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.

Because of the tremendous amount of media streaming, video calling and high definition TV and gaming, the biggest challenge for the wireless industry is the increasing demand of high data rates. Utilization of mm-wave frequencies is an attractive option to meet this high demand. Recent advances in low cost semiconductor technologies allow realization of low-cost on-chip RF front-ends in the high millimeter wave (mm-wave) frequencies, making it possible to realize compact systems for these application areas. Although integrated circuits (ICs) are one of the main building blocks of a mm-wave system, in order to realize a fully functional wireless system, cost-effective antenna design and packaging are two important pre-conditions. Researchers have investigated and reported low-cost electronics packaging up to 100 GHz to a great extent on ceramic substrates, but mm-wave packaging above 100 GHz is relatively less explored, particularly on organic substrates. This Ph.D. dissertation demonstrates the design and development of microwave and mm-wave on-chip and on-package antennas and organically packaged components and modules ranging from 20 GHz to 170 GHz. The focus of this research was to design and develop mm-wave components and modules on LCP, to investigate the viability of this organic substrate and development of fabrication techniques in the K- (18-26.5 GHz), V- (50 to 70 GHz), W- (75 to 110 GHz), and D- (110 to 170 GHz) bands. Additionally, a demonstration of a micro-machined on-chip antenna has also been presented. This dissertation is divided in three parts: (1) characterization of liquid crystal polymer from 110 to 170 GHz. (2) development of highly radiation efficient on-chip and AiP antennas, and (3) development of mm-wave modules with the integration of antennas.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

Made available in DSpace on 2014-06-11T19:26:56Z (GMT). No. of bitstreams: 0 Previous issue date: 2006-03-03Bitstream added on 2014-06-13T20:27:28Z : No. of bitstreams: 1 bronzi_ma_me_sjrp.pdf: 904425 bytes, checksum: 2344eb35a112034c2f1741b2e229f1ec (MD5) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / Estudamos intersecções homoclínicas de variedades estável e instável de pontos peródicos. Toda intersecção homoclínica produz um comportamento curioso na dinâmiôa. Nosso modelo de tal fenômeno é a famosa ferradura de Smale, a qual é um conjunto hiperbólico para um difeomorfismo. Além disso, estudamos dinâmica não hiperbólica cuja perda de hiperbolicidade é divido à tangências homoclínicas. Elas tem um papel central na teoria de sistemas dinâmicos. O desdobramento de uma tangência homoclínica produz dinâmicas muito interessantes. Neste trabalho estudamos a criação de cascatas de bifurcações de duplicação de período e um esquema de renormalização para uma tangência homoclínica. / We study homoclinic intersection of stable and unstable manifolds of periodic points. Every homoclinic intersection produce a intricate behavior of the dynamics. Our model of such phenomena is the so called Smalesþs horseshoe, which is a hyperbolic set for a di eomorphism. We also study non hyperbolic dynamics whose lack of hyperbolicity is due to homoclinic tangencies. They play a central role in the theory of dynamical systems. The unfolding of a homoclinic tangency produce many interesting dynamics. In this work we study creation of cascade of period doubling bifurcations and a renormalization scheme for a homoclinic tangency.

abstract: The space environment comprises cosmic ray particles, heavy ions and high energy electrons and protons. Microelectronic circuits used in space applications such as satellites and space stations are prone to upsets induced by these particles. With transistor dimensions shrinking due to continued scaling, terrestrial integrated circuits are also increasingly susceptible to radiation upsets. Hence radiation hardening is a requirement for microelectronic circuits used in both space and terrestrial applications. This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques. A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS. A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection. Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015