4 Abstract Senescence is a specific cell state distinquished by cessation of cell division and proliferation and changes in gene expression. Normal cells enter senescence after distinct number of cell divisions or in case of an unrepairable damage. Senescence in cancer cells can be induced by subliminal stress as sublethal treatment with certain drugs. Senescent cancer cells persist in the tissue and may secrete a number of factors and nutrients affecting surrounding cells. Senescence can thus change the response of cancer cells to various apoptogens during cancer therapy. In this study, we focused on the elucidation of presumed differences between normal proliferating and senescent cancer cells in their response to selected apoptogens. Implementing bromodeoxyuridine (BrdU)-mediated replication stress in cancer cells derived from pancreatic (PANC-1) or mesothelioma (H28) tumors, we efficiently forced these cells to acquire senescent phenotype. We document that these senescent cells gain higher resistance to combined TRAIL and homoharringtonine (HHT) treatment and enhance sensitivity to other apoptogens such as FasL, camptothecin and mVES. These cells also showed increased expression of anti-apoptotic protein c-FLIP in senescent cells and changes in the expression of some Bcl-2 family proteins....

Im Zentrum dieser Arbeit standen ramanspektroskopische Untersuchungen der elektronischen spin-flip-Übergänge an semimagnetischen (Zn,Mn)Se Proben. Hierbei wurden sowohl Quantentrogstrukturen untersucht als auch volumenartige Proben. Ziel der Forschung war dabei, ein tieferes Verständnis der Wechselwirkungen der magnetischen Ionen mit den Leitungsbandelektronen der Materialien zu gewinnen. Im Hinblick auf mögliche zukünftige spin-basierte Bauelemente lag das Hauptaugenmerk auf dem Einfluss von n-Dotierung bis zu sehr hohen Konzentration. Hierfür standen verschiedene Probenreihen mit unterschiedlichen Dotierungskonzentrationen zur Verfügung. / In the present doctoral thesis, spin flip Raman studies of semimagnetic (Zn,Mn)Se samples were in the focus of interest. Quantum wells as well as bulk-like materials were investigated. The main goal was a better understanding of the exchange interaction behaviour of heavily n-doped semimagnetic samples. The influence of doping on the exchange interaction is of special relevance with regard to spintronics applications. Several series of high quality MBE-grown (Zn,Mn)Se -samples samples were available.

The impressive evolution of modern high-performance microprocessors have resulted in chips with over one billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, three of the main challenges to overcome in order for continuing CMOS technology scaling are; growing standby power dissipation, increasing variations in process parameters, and increasing power dissipation due to growing clock load and circuit complexity. This thesis addresses all three of these future scaling challenges with the overall focus on reducing the total clock-power for low-power, multi-GHz VLSI circuits. Power-dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation. This makes novel power reduction techniques crucial in future VLSI design. This thesis describes a new energy-recovering clocking technique aimed at reducing the total chip clock-power. The proposed technique consumes 2.3x lower clock-power compared to conventional clocking at a clock frequency of 1.56 GHz. Apart from increasing power dissipation due to leakage also the robustness constraints for circuits are impacted by the increasing leakage. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance. / Report code: LiU-TEK-LIC-2006:21.

A extrêmement hautes fréquences, les applications électroniques vont être confrontées à des challenges liés à la réduction des dimensions et la compacité des systèmes. Les limites physiques des matériaux conventionnels étant atteintes, de nouvelles alternatives sont nécessaires dans le domaine du nano-packaging. De nouveaux matériaux ont été étudiés pour remplacer les matériaux conventionnels. Parmi eux, le nanotube de carbone démontre une excellente conductivité électrique et thermique ainsi qu’une résistance physique extraordinaire. Il est donc un candidat de choix pour des applications comme les interconnexions, l’évacuation de chaleur, le blindage électromagnétique ou encore le renforcement structurel. Autant de points capitaux pour le nano-packaging moderne. Dans ce manuscrit, les nanotubes de carbone vont être étudiés en profondeur pour réaffirmer leurs propriétés électroniques et thermiques hors du commun. Nous nous concentrerons ensuite sur l’étude de deux types d’interconnexions à base de nanotubes de carbone : des interconnexions à base de plot en nanotubes de carbone utilisant la technologie Flip-Chip et des interconnexions sans-fil à base de monopole composé de nanotubes de carbone. Enfin, nous étudierons la possibilité de créer des composants passifs Radio-Fréquence à l’aide de structures en nanotubes de carbone. De nouvelles méthodes de fabrication des structures en CNT ont été utilisées au cours de ces travaux de thèse afin d’obtenir une compatibilité avec les technologies CMOS. / At extremely high frequency, electronic applications will have to challenge problems born from the size reduction and compactification of the systems. Physical limits of conventional materials will be reached and so new alternatives are necessary in the nano-packaging field. New materials have been studied to replace conventional materials. Among them, carbon nanotubes have shown extremely high electrical and thermal conductivity as well as extraordinary physical resistance. And so carbon nanotubes are a good candidate for applications such as interconnects, thermal management, electromagnetic shielding or structural reinforcement. All of those applications are capital for modern nano-packaging. In this manuscript, carbon nanotubes will be studied in depths to demonstrate again their incredible electronic and thermal properties. We will then focus on the study of two types of carbon nanotubes based interconnects: carbon nanotubes bumps based interconnects for Flip-Chip applications and wireless interconnects based on carbon nanotubes monopole antenna. Finally, we will study the possibility of creating passive RF components using carbon nanotubes structures. New ways of fabricating the carbon nanotubes structure were used in order to get a fabrication process of the prototype completely compatible with CMOS technologies.

Ces travaux de recherche se rapportent à l'étude de transistors HEMTs en Nitrure de Gallium pour l'amplification de puissance micro-onde. Une étude des caractéristique des matériaux grand gap et plus particulièrement du GaN est réaliséé afin de mettre en exergue l'adéquation de leurs propriétés pour les applications de puissance hyperfréquence telle que l'amplification large bande. Dans ce contexte, des résultats de caractérisations et modélisations électriques de composants passifs et actifs sont présentés. Les composants passifs dédiés aux conceptions de circuits MMIC sont décrits et différentes méthodes d'optimisation que ce soit au niveau électrique ou électromagnétique sont explicitées. Les modèles non linéaires de transistors impliqués dans nos conceptions sont de même détaillés. Le fruit de ces travaux concerne la conception d'amplificateurs distribués de puissance large bande à base de cellules cascode de HEMTs GaN, l'un étant reportés en flip-chip sur un substrat d'AlN, le second en technologie MMIC. La version MMIC permet d'atteindre 6.3W sur la bande 4-18GHz à 2dB de compression. Ces résultats révèlent les fortes potetialités attendues des composants HEMTs GaN.

Les réaliseurs, ou arbres de Schnyder, ont été introduits par Walter Schnyder à la fin des années 80 pour caractériser les graphes planaires, puis pour dessiner ces mêmes graphes sur des grilles $(n-2)\times(n-2)$.<br>Dans ce document nous proposons dans un premier temps une extension du théorème de Wagner aux réaliseurs, qui nous permet d'établir une relation entre le nombre de feuilles et le nombre de faces tricolores d'un réaliseur.<br>Ensuite, à l'aide d'une bijection entre les réaliseurs et les paires de chemins de Dyck qui ne se coupent pas, nous énumérons les réaliseurs. Un algorithme de génération aléatoire de $p$ chemins de Dyck ne se coupant pas, est également présenté. Il permet en outre de générer aléatoirement des réaliseurs en temps linéaire.<br>Puis nous montrons que grâce aux réaliseurs, il est possible de dessiner, à l'aide de lignes brisées des graphes planaires sur des grilles de largeur et de surface optimales.<br>Enfin, nous proposons une généralisation des réaliseurs minimaux aux graphes planaires connexes : les arbres recouvrants bien-ordonnés. Grâce à cette généralisation ainsi qu'à une méthode de triangulation adaptée nous proposons un algorithme de codage des graphes planaires à $n$ sommets en $5,007n$ bits.

The focus in this thesis is on the calculations of an empirical null distributionfor likelihood ratio tests testing either separable or double separable covariancematrix structures versus an unstructured covariance matrix. These calculationshave been performed for various dimensions and sample sizes, and are comparedwith the asymptotic χ2-distribution that is commonly used as an approximative distribution. Tests of separable structures are of particular interest in cases when data iscollected such that more than one relation between the components of the observationis suspected. For instance, if there are both a spatial and a temporalaspect, a hypothesis of two covariance matrices, one for each aspect, is reasonable.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). Next-generation high-density packaging applications would necessitate a new base substrate material to achieve ultra-fine pitch solder-joint reliability and multiple layers of fine-line wiring at low cost. The NEMI 2000 roadmap defines the need for 4-8 layers of 5-10 m wiring for future system boards. The 2003 ITRS roadmap calls for organic substrates with less than 100-m area-array pitch in the package or board by year 2010. Solder-joint reliability at such fine-pitch is a matter of concern for the industry. Use of underfills reduces thermal stresses but increases cost and, in addition, their dispensing becomes increasingly more complicated with the shorter gaps required for future interconnects. Therefore, there is a pronounced need to evaluate board materials with CTE close to that of Si for reliable flip-chip on board without underfill. Recently, a novel manufacturing process (using polymeric precursor) has been demonstrated to yield boards that have the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (~250 GPa) and Si-matched CTE (~2.5 ppm/㩠of ceramics. This work reports the evaluation of novel SiC-based ceramic composite board material for ultra-fine pitch solder-joint reliability without underfill and multilayer support. FE models were generated to model the behavior of flip-chips assembled without underfill and subjected to accelerated thermal cycling. These models were used to calculate solder-joint strains which have a strong direct influence on fatigue life of the solder. Multilayer structures were also simulated for thermal shock testing so as to assess via strains for microvia reliability. Via-pad misregistration was derived from the models and compared for different boards. Experiments were done to assemble flip-chips on boards without underfill followed by thermal shock testing so as to get the number of cycles to failure. To assess microvia reliability, 2 layer structures containing vias of different diameters were fabricated and subjected to thermal cycling. Via-pad misalignment was also studied experimentally. Modeling and experimental results were corroborated so as to evaluate thermomechanical suitability of C-SiC for high-density packaging requirements.

Low-density parity-check (LDPC) codes are a subclass of linear block codes. These codes have parity-check matrices in which the ratio of the non-zero elements to all elements is low. This property is exploited in defining low complexity decoding algorithms. Low-density parity-check codes have good distance properties and error correction capability near Shannon limits. In this thesis, the sum-product and the bit-flip decoding algorithms for low-density parity-check codes are implemented on Intel Pentium M 1,86 GHz processor using the software called MATLAB. Simulations for the two decoding algorithms are made over additive white gaussian noise (AWGN) channel changing the code parameters like the information rate, the blocklength of the code and the column weight of the parity-check matrix. Performance comparison of the two decoding algorithms are made according to these simulation results. As expected, the sum-product algorithm, which is based on soft-decision decoding, outperforms the bit-flip algorithm, which depends on hard-decision decoding. Our simulations show that the performance of LDPC codes improves with increasing blocklength and number of iterations for both decoding algorithms. Since the sum-product algorithm has lower error-floor characteristics, increasing the number of iterations is more effective for the sum-product decoder compared to the bit-flip decoder. By having better BER performance for lower information rates, the bit-flip algorithm performs according to the expectations / however, the performance of the sum-product decoder deteriorates for information rates below 0.5 instead of improving. By irregular construction of LDPC codes, a performance improvement is observed especially for low SNR values.