<p>MurA catalyzes the first committed step of peptidoglycan biosynthesis and it is the target of the antibiotic fosfomycin. Due to a Cys-to-Asp substitution in the active site, MurAs from a number of pathogenic bacteria, including <em>Mycobacterium tuberculosis</em> and <em>Borrelia burgdorferi</em> (Lyme disease), are fosfomycin resistant. His-tagged <em>Borrelia burgdorferi</em> MurA (Bb_MurA) and its D116C mutant have been successfully expressed, purified and characterized. The <em>k</em>_cat value of wild-type Bb_MurA was 0.74 ± 0.01 s^-1. The D116C mutant’s <em>k</em>_cat decreased by 25-fold and was fosfomycin sensitive. The pH profiles of <em>k</em>_cat for both Bb_MurA and its mutant were characterized. There was little difference in p<em>K</em>_a1 values, but the p<em>K</em>_a2 value shifted from 7.4 ± 0.2 in wild-type enzyme to a value >11 in the mutant. This demonstrated that the p<em>K</em>_a2 of 7.4 was due to D116, and that it must be protonated for activity. Fosfomycin inactivation of Bb_MurA_H6(D116C) was time-dependent and only proceeded in the presence of UDP-GlcNAc. The dissociation constant, <em>K</em>_i, was 5.7 ± 0.4 µM and rate of covalent modification, <em>k</em>_inact, was 0.021 ± 0.003 s^-1.</p> <p>DAHP synthase catalyzes the first committed step in the shikimate pathway, and its catalysis has been proposed to proceed through two oxacarbenium ion intermediates. Pyruvate oxime, glyoxylate oxime and 4-imidazolecarboxylic acid have been evaluated as inhibitors of DAHP synthase. In the presence of glycerol 3-phosphate, the fitted <em>K</em>_i values of pyruvate oxime and glyoxylate oxime were 7.6 (± 0.9) × 10^-5 M and 7.4 (± 1.7) × 10^-5 M, respectively. 4-Imidazolecarboxylic acid’s inhibition was cooperative, and its binding was competitive with respect to PEP, and uncompetitive with respect to E4P. Its equilibrium dissociation constant was 3.0 (± 0.2) × 10^-3 M.</p> / Master of Science (MSc)

L’intégration des oscillateurs dans les microcontrôleurs est aujourd’hui un enjeu industriel majeur suscitant une forte concurrence entre les principaux acteurs du marché. En effet, les oscillateurs sinusoïdaux sont des circuits indispensables, et sont majoritairement basés sur l’utilisation d’un résonateur à quartz ou MEMS externe. De plus en plus d’investigations sont menées afin d’intégrer des dispositifs résonants dans les boîtiers et éviter ainsi toutes les contraintes extérieures limitant les performances de l’oscillateur. En ce sens, nous avons étudié dans ce travail le comportement électrique, et notamment inductif, des liaisons filaires permettant de connecter une puce à son boîtier de protection. L’avantage d’utiliser ce composant passif est principalement son faible coût. Ce composant a été caractérisé en utilisant plusieurs méthodologies de modélisations et de mesures sur une large plage fréquentielle. Cette étude propose un modèle permettant aux concepteurs d’utiliser une caractéristique électrique équivalente dans une technologie CMOS standard. L’intégration du composant dans une cellule résonante est démontrée au sein d’un prototype. / Nowadays, the integration of oscillators into microcontrollers is a major industrial challenge which involves a large competition between the main actors of this market. Indeed, sine wave oscillators are essential circuits, and are fore the most part based on external crystal or MEMs resonators. More and more investigations are carried out in order to integrate the resonant structure into the package, and avoid all external constraints able to restrict the performances of the oscillator. With this in mind, we studied in this work the electrical behavior, in particular the inductive behavior of bond wires which are electrical connections between a die and its package. The main advantage to use this type of component is its low cost of manufacturing. This passive component has been characterized using several measurement tools on a wide range of frequencies. A RLC model has been presented, allowing analogue designers to use an electrical equivalent circuit in standard CMOS technology. The integration of the passive component in a resonant cell has been demonstrated in a prototype.

Ce manuscrit porte sur l’analyse, les méthodes de conception et la recherche de nouvelles structures de sources de courant, en se focalisant principalement sur les miroirs de courant, source la plus élémentaire. Le dépassement des limites actuelles pour l’optimisation du compromis vitesse-précision-consommation est l’objectif majeur des travaux présentés.La première partie est consacrée à l’étude de l’origine de ces limites et dresse l’état de l'art des structures de miroir de courant CMOS. Sont ensuite étudiées plus en détails, les possibilités offertes par les miroirs à entrée active. Une des premières contributions de nos travaux de recherche a été de proposer un formalisme dédié à l’étude et à l’implémentation de ce type de miroir, suivi de propositions d’amélioration à coût minimum de la topologie classique.Le développement d’une nouvelle approche de conception utilisant un principe de rétroaction non-linéaire en mode courant constitue la contribution majeure de cette thèse. La rétroaction est implémentée grâce à un convoyeur de courant de seconde génération dédié, très faible consommation et conçu pour avoir un comportement volontairement non-linéaire. Couplée avec des techniques classiques de régulation cascode pour une copie en courant de haute-précision, cette topologie constitue une source de courant élémentaire compétitive pour la réalisation de systèmes à haut niveau de performance.L'approche est mise en œuvre puis validée par la conception, en technologie CMOS 180nm, de deux circuits dédiés à la génération des courants dans les puces de stimulation neurale. L’ensemble des résultats obtenus dans ces dernières études démontre, qu’il est possible de dépasser les limites actuelles du compromis vitesse-précision-consommation, en se basant sur la stratégie de conception et les nouvelles topologies de miroirs à entrée active proposées. / The work presented in this manuscript involves analysis, design methods and search for improved structures of current sources, with main focus on the current mirrors, the most elementary current source. The main objective of our research was to outperform the present limitations in terms of speed, power and accuracy that exists in CMOS current mirror design.In the first part of the manuscript, we investigate on the origin of these limitations and present a literature review of popular and recent advanced current mirror structures. Then follow a deeper analysis of active-input current mirror capabilities. The first scientific contributions were, the development of analytical tools dedicated to the implementation of the standard active-input topology, supported by two solutions for dynamic range and stability improvements at minimal costs.The proposition of a novel design approach, relying on a power-efficient speed boosting technique based on current-mode non-linear control loops, constitutes the major contribution of the work presented in this manuscript. The feedback circuit is implemented using a custom low-power current conveyor (CCII), built to be intentionally non-linear. Coupled with classical regulated cascode structures required for high-precision current copy, this enhanced active-input current mirror topology forms a new competitive elementary current source to the design of high-performance systems.The approach is validated and illustrated with the realization of two circuits in 180 nm CMOS technology. Cores of the circuits are two examples of output stages dedicated to neural stimulation chips. Finally, Results of the last studies have demonstrated that, thanks to the design strategy and the new active-input current mirror topologies proposed, it is actually possible to outperform the present limit of the speed-power-accuracy trade-off.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

Ce travail de thèse porte sur le développement d’une méthodologie efficace pour la conception analogique, des algorithmes et des outils correspondants qui peuvent être utilisés dans la conception dynamique de fonctions linéaires à temps continu. L’objectif principal est d’assurer que les performances pour un système complet peuvent être rapidement investiguées, mais avec une précision comparable aux évaluations au niveau transistor.Une première direction de recherche a impliqué le développement de la méthodologie de conception basée sur le processus d'optimisation automatique de cellules au niveau transistor et la synthèse de macro-modèles analogiques de haut niveau dans certains environnements comme Mathworks - Simulink, VHDL-AMS ou Verilog-A. Le processus d'extraction des macro-modèles se base sur un ensemble complet d'analyses (DC, AC, transitoire, paramétrique, Balance Harmonique) qui sont effectuées sur les schémas analogiques conçues à partir d’une technologie spécifique. Ensuite, l'extraction et le calcul d'une multitude de facteurs de mérite assure que les modèles comprennent les caractéristiques de bas niveau et peuvent être directement régénéré au cours de l'optimisation.L'algorithme d'optimisation utilise une méthode bayésienne, où l'espace d’évaluation est créé à partir d'un modèle de substitution (krigeage dans ce cas), et la sélection est effectuée en utilisant le critère d’amélioration (Expected Improvement - EI) sujet à des contraintes. Un outil de conception a été développé (SIMECT), qui a été intégré comme une boîte à outils Matlab, employant les algorithmes d’extraction des macro-modèles et d'optimisation automatique. / The aim of this thesis is to establish an efficient analog design methodology, the algorithms and the corresponding design tools which can be employed in the dynamic conception of linear continuous-time (CT) functions. The purpose is to assure that the performance figures for a complete system can be rapidly investigated, but with comparable accuracy to the transistor-level evaluations. A first research direction implied the development of the novel design methodology based on the automatic optimization process of transistor-level cells using a modified Bayesian Kriging approach and the synthesis of robust high-level analog behavioral models in environments like Mathworks – Simulink, VHDL-AMS or Verilog-A.The macro-model extraction process involves a complete set of analyses (DC, AC, transient, parametric, Harmonic Balance) which are performed on the analog schematics implemented on a specific technology process. Then, the extraction and calculus of a multitude of figures of merit assures that the models include the low-level characteristics and can be directly regenerated during the optimization process.The optimization algorithm uses a Bayesian method, where the evaluation space is created by the means of a Kriging surrogate model, and the selection is effectuated by using the expected improvement (EI) criterion subject to constraints.A conception tool was developed (SIMECT), which was integrated as a Matlab toolbox, including all the macro-models extraction and automatic optimization techniques.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

abstract: The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task. The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

Les fluctuations électriques des composants sont une limitation à la miniaturisation des circuits. Malgré des procédés de fabrications en continuelle évolution, les variations des caractéristiques électriques dues au désappariement entre deux dispositifs limitent les performances des circuits. Concernant les applications à faible consommation, ces fluctuations locales peuvent devenir très critiques. Dans le contexte du développement d’une technologie CMOS 90nm avec mémoire Flash embarquée pour des applications basse consommation, l’appariement de transistors MOS est étudié. Une analyse de l’impact du dopage de grille des transistors NMOS est menée. L’étude se focalise sur l’appariement en tension des paires différentielles polarisées dans la zone de fonctionnement sous le seuil. Il est démontré que cet appariement peut être dégradé à cause de l’effet « hump », c'est-à-dire la présence de transistors parasites en bord d’active. Un macro-modèle permettant aux concepteurs de modéliser cet effet est présenté. Il est étudié au niveau composant, au niveau circuit et en température. Enfin, une étude de la dégradation de l’appariement des transistors MOS sous stress porteurs chauds est réalisée, validant un modèle de dégradation. Des transistors octogonaux sont proposés pour supprimer l’effet « hump » et donnent d’excellents résultats en termes d’appariement ainsi qu’en fiabilité. / Electrical fluctuations of devices limit chip miniaturization. Despite manufacturing processes in continuous evolution, circuit performances are limited by electrical characteristics variations due to mismatch between two devices. Concerning low power applications, local fluctuations can become very critical. In the context of development of a 90nm CMOS technology with Embedded Flash memory for low power applications, MOS transistors matching is studied. A study of NMOS transistors gate doping impact is conducted. Study focuses on voltage matching of differential pairs biased under threshold. It is demonstrated that this matching can be degraded due to « hump » effect, meaning presence of parasitic devices on active edge. A macro-model allowing designers to model this effect is presented. It is studied at device level, circuit level and for different temperatures. Finally, a degradation study of MOS transistors mismatch under Hot Carriers Injection stress is performed, validating a degradation model. Octagonal devices are proposed to suppress « hump » effect and give good results in terms of matching as well as reliability.

A la différence de la conception numérique, la conception analogique souffre d’un réel retard au niveau de la solution logicielle qui permet une conception à la fois rapide et fiable. Le dimensionnement de circuits analogiques exige en effet un nombre assez élevé de simulations et de vérifications et dépend beaucoup de l’expertise du concepteur. Pour pallier à ce retard, des outils de conception automatique basés sur des algorithmes d’optimisation locale et globale sont développés. Ces outils restent encore immatures car ils n’offrent que des réponses partielles aux questions du dimensionnement, alors que l’obtention d’un dimensionnement optimal d’un circuit analogique en un temps raisonnable reste toujours un enjeu majeur. La réduction du temps de conception de circuits analogiques intégrés nécessite la mise en place de méthodologies permettant une conception systématique et automatisable sur certaines étapes. Dans le cadre de cette thèse, nous avons travaillé suivant trois approches. Il s’agit d’abord de l’approche méthodologique. A ce niveau nous préconisons une approche hiérarchique descendante « top-down ». Cette dernière consiste à partitionner le système à dimensionner en sous blocs de fonctions élémentaires dont les spécifications sont directement héritées des spécifications du niveau système. Ensuite, nous avons cherché à réduire le temps de conception à travers l’exploration de solutions optimales à l’aide des algorithmes hybrides. Nous avons cherché à profiter de la rapidité de la recherche globale et de la précision de la recherche locale. L’intérêt des algorithmes de recherche hybride réside dans le fait qu’ils permettent d’effectuer une exploration efficace de l’espace de conception du circuit sans avoir besoin d’une connaissance préalable d’un dimensionnement initial. Ce qui peut être très intéressant pour un concepteur débutant. Enfin, nous avons travaillé sur l’accélération du temps des simulations en proposant l’utilisation des méta-modèles. Ceux-ci présentent un temps de simulation beaucoup plus réduit que celui des simulations des modèles électriques. Les méta-modèles sont obtenus automatiquement depuis une extraction des résultats des simulations électriques. / Contrary to digital design, analog design suffers from a real delay in the software solution that enables fast and reliable design. In this PhD, three approaches are proposed. The first is the methodological approach. At this level we recommend a "top-down" hierarchical approach. It consists of partitioning the system to size into sub-blocks of elementary functions whose specifications are directly inherited from the system level specification. Next, we aimed to reduce design time through the exploration of optimal solutions using hybrid algorithms. We attempted to take advantage of the rapid global search and local search accuracy. The interest of hybrid search algorithms is that they allow to conduct effective exploration of the design space of the circuit without the need for prior knowledge of an initial design. This can be very useful for a beginner designer. Finally, we worked on the acceleration of time simulations proposing the use of meta-models which present a more reduced time than electrical simulation models. Meta-models are obtained automatically from extracting results of electrical simulations.