Este trabajo se centra en los amplificadores de muy bajo ruido y micro-consumo de potencia, tomando como ejemplo la detección de señales nerviosas (ENG) para su aplicación en dispositivos implantables. Si bien el ancho de banda de las señales médicas es reducido, como son en muchos casos de amplitud extremadamente pequeña, la principal dificultad para el diseño de circuitos será el bajo ruido combinado con micro o nano-consumo de potencia. En efecto, existe una relación de compromiso conocida entre ruido a la entrada y consumo de corriente en un amplificador que el diseñador debe optimizar. Este trabajo esencialmente intenta responder la pregunta: ¿cómo aprovechar al máximo la energía disponible en la batería de un implante para alimentar un amplificador de muy bajo ruido? A lo largo de esta tesis se presentarán técnicas innovadoras de circuito para aprovechar mejor la energía disponible. En primer lugar, se analiza el uso de los espejos activos como sustitución de los espejos de corriente de dos transistores tradicionales. Se estudiaron analíticamente y mediante simulaciones las ventajas y desventajas; luego se diseñó, fabricó y caracterizó un espejo de corriente activo que funciona como fuente de corriente de 10μA con menos de 100mV de caída de voltaje en una tecnología de 0.6μm. En segundo lugar, se presenta la idea de reutilización de corriente apilando sucesivos pares diferenciales como forma de aprovechar todo el rango de tensión de la batería en un circuito analógico. Se demuestra en forma analítica y con medidas sobre un circuito fabricado, que la técnica es extremadamente eficiente en el compromiso entre consumo de corriente y ruido. Se diseñó, fabricó, y caracterizó un amplificador para señales ENG que apila doce pares diferenciales de entrada funcionando con una batería de 3.6V (nominales), con un consumo total de 16.5μA y una ganancia en la banda pasante de ≈80dB. Tiene un ancho de banda de 4kHz y el ruido medido a la entrada de 4.5nV/Hz1/2@1kHz y 330nVrms en la banda de interés. El amplificador tiene un NEF medido de 0.84, incluso considerando el consumo de todos los circuitos auxiliares, lo cual parece ser el primer amplificador reportado con un NEF<1. Finalmente, se estudia un conversor DC-DC inductivo de microconsumo como otra alternativa para reducir el consumo de corriente de la batería en circuitos analógicos. Se diseñó, fabricó y caracterizó un conversor DC-DC inductivo del tipo step-down, que reduce el voltaje de 3.6V a 0.6V para un consumo de 36μW. Este conversor podría alimentar un solo par diferencial complementario (un NMOS y un PMOS apilados) con seis veces más corriente, en sustitución de los seis pares diferenciales complementarios apilados previamente. / This work focuses on electronic amplifiers with very low noise and micro/nano power consumption. We selected an amplifier for the detection of nerve signals (ENG) in implantable medical devices as a case study. While the bandwidth of medical signals is relatively low, as the signals are generally of extremely low amplitude, the main challenge for the circuit designer is to achieve low noise combined with low power consumption. Indeed, there is a well-known relationship between noise at the amplifier’s input and electrical current consumption of the amplifier. In this work, we evaluated how to power a low noise amplifier using the maximum amount of available energy from an implantable device’s battery. Throughout this thesis, we present novel circuit techniques to better utilize the available energy. Firstly, we analyzed the use of active mirrors instead of traditional two transistor current mirrors. We studied the advantages and disadvantages of active mirrors analytically and with simulations. We designed, fabricated and tested an active mirror that works as a 10μA current source with less than 100mV voltage drop in a 0.6μm technology. Secondly, we introduced the idea of reusing current by stacking differential pairs, to better utilize the voltage range of the battery. This topology is shown to be extremely efficient in the trade-off between current consumption and generated noise. We designed, fabricated and tested an amplifier for ENG signals that stacks twelve differential pairs and works with a 3.6V (nominal) battery, consumes 16.5μA and has a gain of ≈80dB in the passing band. The amplifier has a bandwidth of 4kHz, and a measured noise of 4.5nV/Hz1/2@1kHz and 330nVrms in the band of interest. The amplifier has a measured NEF of 0.84 even considering the consumption of all the auxiliary circuits, which makes it, to the best of our knowledge, the first amplifier reported with an NEF<1. Finally, we studied inductive DC-DC converters with micro-consumption as an alternative way to reduce consumption without introducing extra noise. We designed, fabricated and tested a step-down inductive DC-DC converter, that reduces voltage from 3.6V to 0.6V for a 36μW load. This converter could power one complementary differential pair (only one stacked PMOS and NMOS differential pair) with six times the electrical current, and could be used instead of the six complementary differential pairs used previously.

La nueva generación de sistemas de comunicaciones digitales demanda conversores analógico-digital (ADC) de muy alta velocidad que sólo pueden ser realizados en base una arquitectura paralela de conversores temporalmente intercalados (TI-ADC). Un TI-ADC consiste en un arreglo de M ADC en paralelo que son coordinados por M fases de reloj. Como resultado, se obtiene una tasa de frecuencia de muestreo global (Fs) igual a M veces la tasa de muestreo individual de cada ADC. Sin embargo, debido a los desapareamientos entre los transistores dentro de los circuitos integrados, los canales de los TI-ADC pueden mostrar diferencias en sus diversos parámetros esenciales (por ej. desajustes de offset, ganancia y fases de muestreo). Estos desajustes pueden ser detectados y calibrados, sin embargo, el desajuste entre las fases de muestreo presenta un gran desafío en su detección y por ello representa un tema abierto de investigación. En esta Tesis se propone una nueva técnica para la detección y calibración del desajuste entre las fases de muestreo en TI-ADC para receptores digitales de fibra óptica de 40/100 Gb/s. Además, la técnica propuesta puede detectar y corregir el desapareamiento de tiempo de propagación (time-skew) entre los canales en cuadratura (I/Q) que se presenta en los receptores ópticos coherentes. Asimismo, el método de ajuste puede extenderse a otros tipos de receptores digitales que utilicen TI-ADC. La técnica propuesta se demuestra efectiva y simple ya que evita el agregado de circuitos adicionales y aprovecha la información disponible dentro del procesador digital de señales del receptor. Por otro lado, el otro aporte fundamental de la Tesis es la verificación y demostración experimental del método de calibración para TI-ADC. Para ello se diseñó un chip de TI-ADC de 2 GS/s y 6-bits que implementa 8 canales temporalmente intercalados y un total de 16 conversores de aproximaciones sucesivas asíncronicos. El diseño incorpora múltiples capacidades de calibración, incluyendo celdas de retardo programable que permiten controlar las fases del conversor. El chip se fabricó en una tecnología CMOS de 0.13μm, siendo este el primer chip en ser diseñado y enviado a fabricar desde la FCEFyNUniversidad Nacional de Córdoba. Se realizaron las mediciones del conversor y el resto de los bloques, demostrando una correcta operación según sus especificaciones de diseño. A partir de este conversor prototipo se desarrolló una plataforma de hardware y software dedicada que permitió emular un sistema de comunicaciones para la verificación de la propuesta de calibración. Finalmente la Tesis presenta diferentes ejemplos experimentales de calibración, demostrando que la técnica puede mitigar correctamente los efectos de los desajustes entre fases del conversor sobre el desempeño del receptor. / The new generation of digital communications systems demand for very high-speed analog-to-digital converters (ADC) that can be only realized with parallel architectures like time-interleaved ADC (TI-ADC). A TI-ADC includes an array of M parallel ADCs that are managed by M clock phases. As a result, the overall sampling rate (Fs) is M times the rate of each individual ADC. However, due to mismatch between transistors in integrated circuits, the channels of a TI-ADC may show differences in their essential parameters (eg. offset, gain and sampling phase mismatches). These mismatches can be detected and calibrated, however, the sampling phase mismatch detection presents a great challenge and therefore, it is an open research topic. This Thesis proposes a novel technique for detection and calibration of sampling phase mismatch in TI-ADC used for digital receivers. The technique is specially suitable for 40/100 Gb/s fiber optic receivers. However the technique can be extended to any other digital receiver that requires TI-ADC phase calibration. In addition, the proposed technique can detect and correct the time-skew error between quadrature (I/Q) channels that is typically found in optical coherent receivers. The technique proves to be effective and simple as it avoids additional circuitry and it takes advantage of the information available in the receiver digital signal processor. On the other hand, the other main contribution of this Thesis is the experimental demonstration and verification of TI-ADC calibration method. For this propose, a 2 GS/s and 6-bits TI-ADC was designed. The chip consists of 8 interleaved channels and 16 asynchronous successive approximations registers ADC. The design also includes multiple calibration capabilities, including programmable delay cells that can control each phase independently. The chip was fabricated in a 0.13μm CMOS technology process and it was the first chip to be designed and sent for manufacture from FCEFyN-Universidad Nacional de Córdoba. Measurements of prototype have demonstrated a correct operation according to its specifications. Then, based on the prototype TI-ADC and a dedicated hard-soft platform, a communications system could be emulated for experimental calibration proposes. At the end of the Thesis, several experimental calibrations examples are showed. With these measurements it can be demonstrated that the calibration method can successfully mitigate the sampling phase mismatch effects over the receiver.

The increasing capabilities of multimedia appliances demand arithmetic circuits with higher speed and reasonable power dissipation. A common technique to attain those goals is synchronous pipelining, which increases the throughput of a circuit at the expense of longer latency, and it is therefore suitable where throughput takes priority over latency. Two synchronous pipelining approaches, conventional pipelining and wave pipelining, are commonly employed. Conventional pipelining uses registers to divide the circuit into shorter paths and synchronize among sub-blocks, while wave pipelining uses the delay of combinational elements to perform those tasks. As wave pipelining does not introduce additional registers, in principle, it can attain a higher throughput and lower power consumption. However, its throughput is limited by delay variations, while delay balancing often leads to increased power dissipation. This dissertation proposes a hybrid pipelining method called HyPipe, which divides the circuit into sub-blocks using conventional pipelining, and applies wave pipelining to each sub-block. Each sub-block is derived from a single base circuit, leading to a better delay balance and greater throughput than with heterogeneous circuits. Another requirement for wave pipelining to achieve high speed is short signal rise and fall times. Since CMOS wide-NAND and wide-NOR gates exhibit long rise and fall times and large delay variations, they should be decomposed. We show that the straightforward decomposition using alternating levels of NAND and NOR gates results in large delay variations. Therefore, we propose a new decomposition method using only one gate type. Our method reduces delay variations by up to 39%, and it is appropriate for wave pipelining based on standard-cells or sea-of-gates. We laid out a 4x4 HyPipe multiplier as a proof of concept and performed a post-layout SPICE simulation. The multiplier achieves a throughput of 4.17 billion multiplications per second or a clock period of 2.52 four-load inverter delays, which is almost twice the speed of any existing multiplier in the open literature. When the supply voltage is reduced to 1.2 V from 1.8 V, its power consumption is reduced from 76.2 mW to 18.2 mW while performing 2.33 billion multiplications per second. / Ph. D.

Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits. / Master of Science

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed. / Master of Science

Quantum technologies are at the forefront of scientific advancements, with the potential to profoundly alter our lives. These quantum applications depend on a consistent, large-scale supply of qubits to realize their potential and achieve quantum advantage. The development of practical quantum technologies is currently hindered by the absence of a scalable quantum platform. Integrated silicon photonics, realized within state-of-the-art CMOS foundries, emerges as a promising solution to this challenge, enabling a scalable quantum source of light via the monolithic integration of thousands of photonic components alongside complex control electronics. In this dissertation I introduce a scalable implementation of the electronic-photonic quantum source of light on chip. This system can be used as a fundamental block in more complex systems used to realize quantum computing, communication, or sensing. The physical realization of our quantum light source on chip is derived strictly from the first principles, while accounting for the imperfections associated with the manufacturing variability observed in CMOS foundries. By designing all critical elements of our system to offer active control over their frequency spectrum, we reinforce the system against all sources of technical noise and enable a long-term stable operation. This document details our comprehensive design approach and validates the scalability and functionality of our electronic-photonic quantum light source through experimental demonstrations. Additionally, I present a theoretical design of a classical passive device that can achieve unprecedented laser linewidth narrowing at high efficiency. Through utilization of resonators defined by guiding material with a strong chi(2) nonlinearity and Q-engineering, we predict that the optical parametric oscillation (OPO) can efficiently convert the input laser light into two output waves, while all the laser noise is transferred in one of the output waves. I present analytical expression relating the conversion efficiency of the OPO process to the achieved linewidth narrowing, while taking into the account the underlying material platform and the quality of the optical resonator. This part of my research opens new avenues for precision laser applications, enhancing the prospects for simpler and inexpensive low-noise lasers. / 2026-09-11T00:00:00Z

This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by being capable of removing 185 W/cm2 before the junction temperatures active elements exceed 85°C. To examine the heat transfer characteristics of this proposed on-chip cooler, different channel geometries were simulated using computational fluid dynamics. The channel designs were simulated using 20°C water at different flow rates to achieve a laminar flow regime with Reynolds numbers ranging from 200 to 500. The steady state simulations were performed using a heat flux of 100 W/cm2. Simulation results were verified using fabricated test chips. A micro-fin geometry showed to have the highest heat transfer capability and lowest simulated substrate temperatures. While operating with a Reynolds number of 400, a Nusselt number per input energy (Nu/Q) of 0.24 W-1 was achieved. The micro-fin geometry is also capable of cooling a substrate with a heat flux of 100W/cm2 to 45ºC with a Reynolds number of 525. These channels also have a lower thermal resistance compared to external heat sinks because there is no heat spreader or thermal interface material layer. / Master of Science

Um das Entdeckungspotential des Large Hadron Colliders auszunutzen, wird er beginnend 2024 zum High Luminosity Large Hadron Collider ausgebaut. Neue Detektorherausforderungen entstehen durch die höhere instantane Luminosität und den höheren Teilchenfluss. Der neue ATLAS Inner Tracker wird den aktuellen Spurdetektor ersetzen, um mit diesen Herausforderungen umzugehen. Es gibt viele Pixeldetektortechnologien zur Teilchenspurerkennung, jedoch muss ihre Eignung für den ATLAS Inner Tracker untersucht werden. Aktive Hochspannungs-CMOS-Sensoren, die in industriellen Prozessen produziert werden, bieten eine schnelle Auslese und Strahlenhärte. In dieser Arbeit wird der HV2FEI4v2-Sensor, der kapazitiv mit dem ATLAS-FE-I4-Auslesechip gekoppelt ist, dahingehend charakterisiert, ob er für eine Verwendung in einer der äußeren Lagen des ATLAS Inner Tracker geeignet ist. Schlüsselgrößen des Prototypens, wie die Treffereffizienz und die Subpixelentschlüsselung, werden untersucht. Der frühe HV2FEI4v2-Prototyp zeigt vielversprechende Ergebnisse, die als Ausgangspunkt für weitere Entwicklungen dienen. Aktive CMOS-Sensoren stellen einen möglichen Kandidaten für einen kosteneffizienten Detektor für den High Luminosity Large Hadron Collider.

L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire dans la diminution de la fiabilité des composants électroniques aussi bien dans l’environnement radiatif spatial que terrestre. Cette étude porte sur la modélisation des mécanismes physiques qui conduisent à ces aléas logiques (en anglais "Soft Errors"). Ces modèles sont utilisés dans une plateforme de simulation,appelée TIARA (Tool suIte for rAdiation Reliability Assessment), qui a été développée dans le cadre de cette thèse. Cet outil est capable de prédire la sensibilité de nombreuses architectures de circuits (SRAM,Flip-Flop, etc.) dans différents environnements radiatifs et sous différentes conditions de test (alimentation, altitude, etc.) Cette plateforme a été amplement validée grâce à la comparaison avec des mesures expérimentales effectuées sur différents circuits de test fabriqués par STMicroelectronics. La plateforme TIARA a ensuite été utilisée pour la conception de circuits durcis aux radiations et a permis de participer à la compréhension des mécanismes des aléas logiques jusqu’au noeud technologique 20nm. / Aggressive integrated circuit density increase and power supply scaling have propelled Single Event Effects to the forefront of reliability concerns in ground-based and space-bound electronic systems. This study focuses on modeling of Single Event physical phenomena. To enable performing reliability assessment, a complete simulation platform named Tool suIte for rAdiation Reliability Assessment (TIARA) has been developed that allows performing sensitivity prediction of different digital circuits (SRAM, Flip-Flops, etc.) in different radiation environments and at different operating conditions (power supply voltage,altitude, etc.) TIARA has been extensively validated with experimental data for space and terrestrial radiation environments using different test vehicles manufactured by STMicroelectronics. Finally, the platform has been used during rad-hard digital circuits design and to provide insights into radiation-induced upset mechanisms down to CMOS 20nm technological node.

Ces travaux s'inscrivent dans un contexte où les contraintes vis-à-vis des décharges électrostatiques sont de plus en plus fortes, les circuits de protection sont un problème récurrent pour les circuits fonctionnant à hautes fréquences. La capacité parasite des composants de protection limite fortement la transmission du signal et peut perturber fortement le fonctionnement normal d'un circuit. Les travaux présentés dans ce mémoire font suite à une volonté de fournir aux concepteurs de circuits fonctionnant aux fréquences millimétriques un circuit de protection robuste présentant de faibles pertes en transmission, avec des dimensions très petites et fonctionnant sur une très large bande de fréquences, allant du courant continu à 100 GHz. Pour cela, une étude approfondie des lignes de transmission et des composants de protection a été réalisée à l'aide de simulations électromagnétiques et de circuits. Placés et fragmentées le long de ces lignes de transmission, les composants de protection ont été optimisés afin de perturber le moins possible la transmission du signal, tout en gardant une forte robustesse face aux décharges électrostatiques. Cette stratégie de protection a été réalisée et validée en technologies CMOS avancées par des mesures fréquentielles, électriques et de courant de fuite. / Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, the lithography dimension shrink make electrostatic discharges (ESD) issues become more significant. Specific ESD protection devices are embedded in RFICs to avoid any damage. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of RFICs. ESD protection size dimensions are also an issue for the protection of RFICs, in order to avoid a significant increase in production costs. This work focuses on a broadband ESD solution (DC-100 GHz) able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies. Thanks to the signal transmission properties of coplanar / microstrip lines, a broadband ESD solution is achieved by implementing ESD components under a transmission line. The silicon proved structure is broadband; it can be used in any RF circuits and fulfill ESD target. The physical dimensions also enable easy on-chip integration.