L'activité de recherche scientifique effectuée dans le cadre de mon doctorat de sciences s'est déroulée dans le secteur de la conception de circuits intégrés radiofréquences pour des systèmes ultra-wideband (UWB) et aux ondes millimétriques, et s'est articulée comme suit: (i) circuits intégrés radiofréquences pour émetteur-récepteurbasse puissance pour réseaux locaux wireless; (ii) radar UWB complètement intégré pour la surveillance cardio-pulmonaire en technologie 90nm CMOS; (iii) amplificateurs faible bruit (LNA) à 60 GHz en technologie standard 65nm CMOS. / The research activity carried out during this PhD consists on the design of radio- frequency integrated circuits, for ultra-wideband (UWB) and millimeter-wave sys- tems, and covers the following topics: (i) radio-frequency integrated circuits for low-power transceivers for wireless local networks; (ii) fully integrated UWB radar for cardio-pulmonary monitoring in 90nm CMOS technology; (iii) 60-GHz low noise amplifer (LNA) in 65nm CMOS technology.

Cette thèse porte sur les défis techniques et technologiques dans la conception des architectures mobiles d'émission « tout numérique » reconfigurables fonctionnant dans les bandes cellulaires pour les standards GSM, W-CDMA, HSUPA et LTE. Avec l'évolution constante des besoins en communication, les terminaux mobiles doivent être en mesure de couvrir différents standards à partir d'une même architecture, en fonction des bandes de fréquences libres, du débit et des contraintes spectrales. Dans un but de réduction des coûts, de consommation et d'une plus grande intégration, de nouvelles architectures dites multistandards se sont développées permettant à un seul émetteur d'adresser chaque standard au lieu de paralléliser plusieurs architectures radio chacune dédiée à un standard particulier. Depuis plusieurs années ont émergé des technologies nanométriques telles que le CMOS 90nm ou 65nm, ouvrant la voie à une plus grande numérisation des blocs fonctionnels des architectures jusqu'alors analogiques. Dans cette étude, nous identifions les évolutions possibles entre « monde analogique » et « monde numérique » permettant de déplacer la limite de la bande de base jusqu'à l'amplificateur de puissance. Plusieurs architectures ont été étudiées avec des degrés de numérisation progressifs jusqu'à atteindre l'architecture « tout numérique » englobant une partie de l'amplification de puissance. Un travail approfondi sur l'étude des différents standards cellulaires mené conjointement avec l'implémentation et la simulation de ces architectures, a permis d'identifier les différents verrous technologiques et fonctionnels dans le développement d'architectures « tout numérique ». Les contraintes de pollution spectrale des raies de sur-échantillonnage sont apparues comme dimensionnantes. Pour chaque bande de chaque standard, ces contraintes ont été évaluées, afin de définir une méthode d'optimisation des fréquences de sur-échantillonnage. Cependant un filtrage externe reste nécessaire. Une deuxième étape nous a amené à identifier et concevoir une technique de filtrage passe bande reconfigurable pour les bandes cellulaires de 1710 à 1980MHz avec au moins 60MHz de largeur de bande afin d'adresser le standard LTE, et 23dB d'atténuation à 390MHz du centre de la bande pour adresser le pire cas de filtrage (bandes 1, 3 et 10 en W-CDMA). Nous avons alors conçu et implémenté un filtre reconfigurable à inductances actives, afin de garantir reconfigurabilité et très faibles pertes d'insertion. Cette thèse a donc permis à partir d'une problématique actuelle et au travers d'une démarche d'identification des limites des architectures « tout numérique », de proposer un prototype de filtre adapté. Ce filtre a été conçu en CMOS 65nm, réalisé et mesuré, les performances sont conformes aux exigences requises / This thesis addresses the technical and technological challenges in the design of “all digital” reconfigurable mobile architectures operating cellular standard bands (GSM, WCDMA, HSUPA and LTE). With the ever-changing communication needs, mobile devices must be able to address different standards from a common architecture depending on free frequency bands, data rate and spectral constraints. In order to reduce costs, consumption and to obtain a greater integration, new architectures were developed and called multi-standard allowing a single transmitter to transmit each standard instead of parallelizing several radio architectures each dedicated to a particular standard. For several years nanoscale technologies such as 90nm or 65nm CMOS have emerged, clearing the way to replace analog functional blocks by greater digital functional blocks. In this study, we identify possible changes between "analog world" and "digital world" to move the digital boundary from the baseband to power amplifier. Several architectures have been studied with progressive digitization degrees to meet "all digital" architecture, comprising part of the power amplifier. Extensive work on the study of different cellular standards conducted jointly with the implementation and simulation of these architectures, let us identified the different technological and functional locks in the development of "all digital" architectures. Oversampling spurious constraints have emerged as dimensioning. For each band of each standard, these constraints were evaluated to define an optimization method of over-sampling frequency. However an external filter is required. A second step led us to identify and design a reconfigurable bandpass filtering technique for cellular bands from 1710 to 1980MHz with at least 60MHz of bandwidth in order to address the LTE, and 23dB attenuation at 390MHz from the center of the filter to address the most constringent filtering cases (bands 1, 3 and 10 in W-CDMA). We then designed and implemented a reconfigurable filter based on active inductors to ensure reconfigurability and very low insertion loss. This thesis permit from an actual architecture system issue and through a process to identify limitations of “all digital” architectures, to propose an adapted filtering solution. This filter was designed in 65nm CMOS, implemented. Measured performance is consistent with requirements

Les étiquettes d'identification radiofréquence passifs (RFID) sont des systèmes télé-communiquant dont l'approvisionnement en énergie se fait via les ondes électromagnétiques. De plus en plus présents dans notre environnement (passeport, badge d'accès, gestion de stock), ils ont l'avantage d'avoir une durée de vie presque infinie, et ne consomment de l'énergie que lorsqu'ils sont sollicités. Par ailleurs, leur moyen de communiquer, sans fil, permet de les utiliser dans des endroits difficiles d'accès pour des lecteurs optiques type code à barre. Toutefois, la portée de tels systèmes est limitée par l'efficacité de la récupération de l'énergie provenant des ondes. Dans ce cadre, l'augmentation de la portée des étiquettes RFID, notamment pour les applications de logistique est un élément primordial.Sont présentés dans cette thèse différents moyens d'augmenter cette portée notamment grâce à l'amélioration des blocs de récupération d'énergie ou l'adaptation d'impédance, tout en respectant des contraintes liées au coût du système. La première partie se focalise sur la réduction des pertes du bloc de récupération d'énergie par l'optimisation du layout. Une architecture à haut rendement à transistor polarisé est ensuite proposée. Pour finir, l'impact de la rétro-modulation et de l'adaptation d'impédance en fréquence sur la récupération d'énergie sont étudiés et améliorés. / The passive radio frequency identification tags (RFID) systems communicate with a remote power supply thanks to electromagnetic waves. Increasingly present in our environment (biometric passport, inventory management), they present the advantage to have an almost infinite lifetime, and consume energy only when they are solicited. Moreover, because it is a wireless way to communicate, it is possible to use these systems places inaccessible to optical drives type bar code. However, the range of such systems is limited by the efficiency of the recovery of energy from waves. In this context, increasing the range of RFID tags, especially for logistics applications is essential.In this these, different ways to increase the range are studied. The first part focuses on the reduction of losses on the rectifying circuitry thanks to layout optimization. An high performances architecture with transistor biased is then proposed. Finally, the impact of backscattering and impedance matching on the energy recovery are studied and improved.

Os estados emaranhados da luz são de grande importância para protocolos de comunicação quântica. Uma das principais fontes que vem sendo estudada no Laboratório de Manipulação Coerente de Átomos e Luz - LMCAL é o oscilador paramétrico ótico (OPO) no qual, através de processos paramétricos não lineares de segunda e terceira ordem (x(2) e x(3)), são produzidos feixes intensos que apresentam correlações quânticas. Recentemente, o LMCAL vem explorando o processo de mistura de quatro ondas (fenômeno derivado da susceptibilidade de terceira ordem x(3)) como fonte geradora de feixes emaranhados. Inicialmente, foi realizado a partir de células de rubídio e agora, em colaboração com o grupo de pesquisa da Profa. Michal Lipson da Universidade de Columbia, em chips de nitreto de silício (Si3N4); permitindo assim possibilidades de modulação ultra-rápida, confinamento de luz em volumes muito reduzidos, além da ótica não-linear do OPO. O presente projeto visa estudar as propriedades quânticas da luz nos OPOs em chips de silício, permitindo que sistemas muito eficientes em informação clássica possam ser usados também para implementação de protocolos de informação quântica. / Entangled States of light beams are of great importance for quantum communication protocols. One of the most relevant source of such states which is being studied at the Laboratory of Coherent Manipulation of Atoms and Light - LMCAL (in portuguese) is the Optical Parametric Oscillator (OPO) which through second and third order nonlinear parametric processes (x(2) and x(3)) produces intense fields that have quantum correlations. Recently, LMCAL is exploring four-wave mixing (FWM), a third-order nonlinear parametric process, as a source of entangled beams. Initially, on rubidium cells and now, in collaboration with Prof. Michal Lipson from the Columbia University, on silicon nitride (Si3N4) chips; opening a new avenue for ultrafast modulation, light confinement in reduced light volumes, as well as the nonlinear optics of the OPO. This project is intended to study quantum properties of light of on-chip OPOs in order to achieve the integration of these highly efficient devices for implementations of quantum information protocols.

Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados. / This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.

Des capteurs MEMS variés peuvent être fabriqués dans une technologie CMOS standard associée à une ou plusieurs étapes de gravure supplémentaires. Dans ce contexte, le micro-usinage du substrat par la face avant permet la fabrication de capteurs résistifs bas coût, basés sur des effets piezorésistifs ou thermiques, mais non optimaux en terme de bruit et de consommation. Cependant, au lieu d'envisager une optimisation technologique du procédé, ce travail s'est plutôt concentré sur le design du capteur et de son interface électronique afin d'améliorer les performances ci-dessus. L'objet de cette thèse est un accéléromètre convectif 3 axes basé sur une topologie initialement prévue pour des mesures suivant 2 axes, dans le plan de la puce, et utilisant une mesure de température différentielle. La mesure de l'accélération dans la direction perpendiculaire au plan de la puce, sans ajouter de structure supplémentaire, est donc étudiée ainsi que l'interface électronique associée. L'originalité de la mesure suivant ce 3ème axe réside dans la mesure de la température de mode commun de la structure existante. Cette étude est réalisée par l'intermédiaire de modélisations multi-physiques et électriques du capteur, de la conception et de la simulation de l'interface électronique et enfin de la caractérisation d'un prototype complet. / In the field of MEMS, various sensors can be manufactured using a standard CMOS technology and subsequent etching techniques. In this context, The Front-Side Bulk Micromachining (FSBM) approach allows the fabrication of low-cost resistive transducers based on either piezoresistive or thermal effects. Nevertheless, such fabrication method leads to non-optimized devices in terms of noise and power consumption. Instead of constraining fabrication technology, and in order to keep fabrication costs as low as possible, this work focuses on sensor design and electronic interfaces to address both issues. In this thesis, the device under study is a 3-axis CMOS thermal accelerometer. The sensor is based on a topology that was primarily introduced for 2-axis measurements only (in-plane acceleration, xy), using differential voltage across sensing thermistors. This work addresses the overall sensing performance by using dedicated front-end electronic and also investigates an opportunity to measure out-of-plane acceleration without the requirement of an additional device. The third axis (z) is provided by measuring a shift in the common-mode temperature, which is clearly an original approach. The study is carried out by means of both physical and electrical modeling of the transducer, electronic design and simulation, and prototype characterization.

The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.

Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

De nos jours, les caméras sont de plus en plus utilisées lors de missions spatiales ou en centrale nucléaire pour des missions d'observations (civiles ou militaires) et de surveillance (vérification du déploiement de panneaux solaires, opérations extravéhiculaires, accident nucléaire, site de stockage). L'environnement spatial, les réacteurs civils nucléaires ou les lieux de stockage de déchets radioactifs sont des milieux radiatifs qui peuvent très fortement perturber les composants électroniques et les systèmes. Dans ces environnements, les rayonnements ionisants dégradent les paramètres électriques des composants électroniques. La dose totale ionisante conduit à l'apparition d'un nombre significatif de charges dans les oxydes des matériaux constituant les composants électroniques, modifiant leurs propriétés électriques. Il en résulte qu'une exposition à la dose totale ionisante peut entraîner une défaillance partielle ou totale d'un composant voire d'un système électronique embarqué.Dans le cadre de cette thèse, nous proposons une méthode de régénération pour guérir les paramètres électriques dégradés par la dose totale ionisante de composants électroniques soumis aux rayonnements ionisants. Cette méthode consiste à appliquer des cycles de recuit isothermes à un composant électronique. Dans un premier temps, cette méthode est appliquée sur des transistors MOS, et une étude est menée sur l'impact des différents paramètres clés du recuit (polarisation, température, durée de recuit, pas en dose entre chaque recuit). Dans un second temps, nous nous intéressons à des composants plus intégrés et plus récents tels que des capteurs d'images de type CMOS APS. Nous montrons expérimentalement l'impact d'un recuit sur ce type de composant et enfin, nous adaptons la méthode de régénération pour l'appliquer à ces capteurs APS afin d'augmenter leur durée de vie. / Nowadays, cameras are more and more used in space missions or nuclear plant for observation (civil or military) and monitoring missions (checking the deployment of solar panels, extravehicular operations, nuclear accident, and area storage). The space environment, nuclear reactors or radioactive waste storage areas are radiative environments that can greatly disturb electronic components and systems. In these environments, ionizing radiation degrades the electrical parameters of electronic components. The total ionizing dose induces significant charge build-up in oxides, degrading the electrical properties of the materials of electronic devices. That can result in the loss of functionality of the entire electronic system.In this thesis, we propose a regeneration method to recover the electrical parameters degraded by total ionizing dose of electronic components subjected to ionizing radiation. In this method isothermal annealing cycles are applied to electronic devices. In a first step, this method is applied on MOS transistors, and a study is conducted on the impact of various key parameters of annealing (bias, annealing temperature, annealing time, dose step between each annealing). In a second step, we focus on components more integrated and newer such as CMOS APS image sensors. We experiment what is the impact of annealing on this type of component and finally, the regeneration method is modified to be suitable on these APS sensors to increase their lifetime.

Depuis près d'un demi-siècle, l'industrie de la microélectronique a prospéré grâce à la miniaturisation des transistors Si CMOS. Cependant, la course à la miniaturisation se heurtera dans les prochaines années à des barrières physiques incontournables. Ainsi, de nombreux travaux technologiques sont en cours de réalisation sur les technologies émergentes et avancées. Ces technologies, notamment le graphène et la CMOS FD-SOI, représentent de grandes opportunités dans le domaine de la microélectronique, et notamment pour la conception de circuits radiofréquences et millimétriques. En outre, avec l'évolution croissante des objets et services connectés, les chercheurs travaillent intensivement sur les systèmes sans fil de cinquième génération (5G). La demande de débit de donnés et le besoin de spectre ont motivé l'utilisation de fréquences millimétriques. Par conséquent, la recherche 5G est confrontée par un ensemble de défis. L'un des défis majeurs de la 5G est la réduction de la consommation d'énergie. En fait, l'efficacité énergétique est directement liée à la fiabilité et au coût des systèmes de communication. L'amplificateur de puissance est l’élément le plus consommateur d'énergie, et l'un des blocs les plus critiques des émetteurs-récepteurs radio. Ainsi, la recherche dans ce domaine est cruciale pour les systèmes de communication de la prochaine génération. Par conséquent, l'objectif de cette thèse est d'étudier et de concevoir des amplificateurs de puissance sur les technologies émergentes et avancées pour les applications 5G. / For nearly half a century, the microelectronics industry has flourished based on the scaling of the silicon CMOS transistor technology. However, the race to transistor miniaturization encounters inevitable physical barriers. Thus, many technological works are under way for the realization of future transistors on emerging and advanced technologies. These technologies, notably the graphene and the CMOS FD-SOI, represent great opportunities for research in the fields of microelectronics, and especially for the design of radiofrequency and millimeter circuits. Besides, with the rising evolution of wireless devices and services, researchers are intensively working on the fifth generation (5G) wireless systems. The demand for high speed data and the need for more spectrum, have motivated the use of millimeter wave carrier frequencies. Therefore, the 5G research is faced with an evolving set of challenges. One of the major challenges of the next generation communication technology is reducing energy consumption. In fact, the power efficiency is directly related to the reliability and cost of the communication systems. It is widely known that the radiofrequency power amplifier is the most power consuming component in the radio transceivers, and is also one of the most critical building blocks in radio front-end. Therefore, research in this area is crucial for next generation communication systems. Consequently, the objective of this thesis is to study and design power amplifiers on emerging and advanced technologies for 5G applications.