Ce sujet de thèse a pour objectif principal la conception de protection contre les décharges électrostatiques (ESD) en technologie silicium avancée sur isolant film mince (FDSOI) avec la compatibilité substrat massif. Ceci suppose une caractérisation ESD des dispositifs élémentaires déjà existants et une conception complète de nouveaux dispositifs sur technologie FDSOI. Ces caractérisations se feront, soit en collaboration avec les équipes de caractérisation ESD présents à STMicroelectronics-Crolles, soit directement par le doctorant grâce au banc de test ESD présent dans le laboratoire pour les développements plus en amont si besoin. La caractérisation fine des mécanismes physiques et des performances des composants sera menée à IMEP qui dispose des équipements adéquats (bancs de mesures en basse et haute température, bruit, pompage de charge, etc) et d’une compétence scientifique incontournable. Il sera ensuite nécessaire d’effectuer des choix de stratégies de protection ESD en fonction des applications et des circuits visés par les équipes de STMicroelectronics. On gardera à l’esprit la notion de fiabilité dès la conception de la protection. Une des stratégies envisagée pour la réalisation de protections ESD compatibles avec des films ultra-minces est l’intégration de ces dispositifs sur substrats hybrides. En effet, il a été démontré chez STMicroelectronics en partenariat avec le LETI qu’il était possible de co-intégrer à partir d’un substrat SOI des dispositifs FDSOI ainsi que des dispositifs bulk. Ceci est rendu possible au moyen d’un réticule supplémentaire qui permet de venir retirer le film de silicium et l’oxyde enterré aux endroits voulus. Ainsi la protection ESD est similaire à celle réalisée sur silicium massif mais avec des implantations compatibles avec des dispositifs à film mince. Les dispositifs sont donc sensiblement différents de ceux réalisés sur bulk et nécessitent une caractérisation approfondie afin de les optimiser au mieux. Une approche ambitieuse vise à concevoir des composants SOI inédits, utilisables pour la protection ESD. Ce volet du travail sera en autre effectué sous la responsabilité de l’IMEP qui a récemment inventé et publié plusieurs types de transistors révolutionnaires : Z2-FET, TFET et BET-FET [12-14].Les études se feront sur des dispositifs silicium sur isolant issus des technologies de fabrication STMicroelectronics. Pour ce faire, il sera nécessaire d’appréhender les techniques de fabrication. Dans ce cadre, une simulation des processus de fabrication est envisagée sous la chaîne d’outil ISE-TCAD en C20nm et technologies futures. Tout d’abord ceci permettra d’embrasser l’ensemble des possibilités inhérentes à la création de nouveaux composants dans la technologie considérée et ensuite cette étude préliminaire fournira des structures de simulation pour les configurations ESD. Parallèlement, les outils TCAD de simulation physique du semi-conducteur à gap indirect type silicium seront mis à profit pour étudier plus précisément le comportement du composant élémentaire de protection ESD. Ces éléments peuvent être par exemple de type : diode, ggNMOS, Tr BIMOS, SCR ou SCR, T2, Beta-matrice, PPP… La synergie avec l’IMEP est essentielle pour l’identification et l’analyse des mécanismes physiques gouvernant le fonctionnement des dispositifs. Notamment, l’objectif principal est d’intégrer la protection ESD dans son application finale et d’évaluer son efficacité et son dimensionnement par l’intermédiaire de paramètres géométriques par exemple. Il sera également possible de réaliser des simulations mixtes afin de mieux tenir compte des effets 3D de la structure (effet de coins, dépolarisation de substrat) et de connaître l’influence des circuits de déclenchement associés à cette protection. L’optimisation de l’implantation de la protection ESD sera alors envisageable au regard des résultats de simulation. On se place ici dans le cadre d’une démarche de Co-Design de protection ESD. / "The thesis main objective is the design of protection againstelectrostatic discharge (ESD), for deep submicron (DSM)state-of-the-art fully depleted silicon-on-insulator technology (FDSOI).This requires the ESD characterization of existing elementary devicesand design of new FDSOI devices. The detailed characterization of thephysical mechanisms and device performance will be conducted at IMEPwhich has adequate facilities and scientific competence in this field.It will then be necessary to make choices for ESD protectionstrategies based on circuit applications by STMicroelectronics. Anambitious approach aims to develop novel SOI components used for ESDprotection. This part of the work will be performed under theresponsibility of IMEP as it has has recently invented and publishedseveral types of revolutionary transistors Z 2-FET, TFET andBET-FET. It will be necessary to understand the fabrication processtechnology of STMicroelectronics. In this framework, 3D simulation ofthe technology will be performed on TCAD software for 28nm FDSOI andfuture technologies. Physical simulation, with TCAD tools of thesemiconductor will be used to study more precisely the behavior of theelementary devices of ESD protection. Collaboration with the IMEP isessential for the identification and analysis of the physicalmechanisms governing device operation.In particular, the main objective is to integrate ESD protection andevaluate its effectiveness and design. It will also be possible toperform mixed-mode simulation to better analyse the effects of the 3Dstructure (corner effects, depolarization of substrate) and evaluatethe influence of trigger circuits associated with this protection.Optimizing the implementation of ESD protection will then be possible.Having studied from a theoretical point of view and numericalsimulation, ESD protection cells and trigger circuits associated withthe ESD protection strategy, qualification on silicon will be applied.This will be done by a test vehicle in the chosen SOI technology, andelectrical characterization of the structures and protection networkswill follow. Finally, the ESD performance will be analyzed to provideoptimization of the design and the choice of ESD protection strategybased on targeted applications."

Le nombre d'objets connectés utilisés quotidiennement ne cesse d'augmenter. Ces objets manipulent et stockent toute sorte de données personnelles et confidentielles. La contrainte de la sécurité devient alors importante pour la conception des systèmes sur puce (SoCs) destinés à des applications grand public. Et, dans un contexte de plus en plus exigeant en termes de performances et agressif en termes de coûts d'intégration et de développement, il est important de trouver des solutions de sécurisation des SoCs adaptées. Aussi, bien que la sécurité matérielle soit souvent envisagée d'un point de vue numérique, les SoCs actuels sont la plupart du temps mixtes. Les travaux présentés dans ce manuscrit s'intéressent alors à la sécurisation des circuits analogiques composant ces systèmes mixtes. Pour protéger au mieux un système quel qu'il soit, il est avant tout nécessaire d'en connaitre les vulnérabilités. Pour cela, une méthodologie d'analyse des vulnérabilités dédiée aux circuits analogiques a été développée. Ainsi, les contremesures adéquates peuvent être développées avant que le système ne soit complètement conçu. La sécurité du système est alors améliorée sans augmenter considérablement le temps de conception de celui-ci. L'analyse d'un système analogique largement utilisé dans les SoCs actuels et composé de nombreux sous-circuits a permis d'identifier les attaques en faute par Stimulation Photoélectrique Laser (SPL) , et par variation de la tension d'alimentation, comme présentant un risque important pour le système. Mais, a aussi mis en avant certaines difficultés. En effet, les circuits analogiques, contrairement aux circuits numériques, sont sensibles aux fautes paramétriques. Aussi, les nombreuses interconnections entre les différents sous-circuits rendent l'analyse de la propagation des fautes difficile. Pour cela, des simulations du système au niveau transistors sont nécessaires. Ces simulations étant coûteuses en temps, la modélisation des circuits analogiques pour l'analyse des effets des attaques par variations de la tension d'alimentation a été étudiée. Les modèles développés pour cette analyse doivent respecter différentes contraintes spécifiques. L'application de ces contraintes à la modélisation d'un circuit analogique concret a montré que les modèles pouvaient être utilisés pour identifier les formes d'attaques pouvant compromettre la sécurité du circuit. En revanche, l'étude n'a pas permis de déterminer le temps gagné par l'utilisation de modèles. Après avoir identifié les deux types d'attaques précédents et analysé leurs effets sur les circuits analogiques, la problématique de la protection des circuits a été abordée. Les contremesures existantes ont été comparées et évaluées. Pour les compléter, des circuits analogiques de détection d'attaques laser et d'attaques en tension actives ont été conçus en tenant compte des fortes contraintes de coûts et des différentes problématiques présentes au niveau d'un SoC. Les tests électriques de ces détecteurs en technologie CMOS 28nm FD-SOI ont prouvé leur efficacité. Finalement, ce travail présente les différentes étapes de la sécurisation d'un circuit analogique, de l'analyse des vulnérabilités à la conception de contremesures, en passant par la modélisation des attaques et de leurs effets, dans le contexte d'applications mixtes et à bas coût. / With the development of the Internet of things, the number of connected devices is in constant increase. These objects use a large amount of data including personal credentials. Therefore, security has become a major constraint for System on Chips (SoCs) designers. Moreover, in a context more and more aggressive in terms of performances and time to market, it is important to find low cost security solutions. Although the hardware security is often treated from a digital point of view, almost every SoCs is also using analog and mixed IP. Thus, this work presents different steps to improve the security of analog IPs, from vulnerability analysis to countermeasures design validation, and behavioral modeling in the context of mixed signals and low cost applications. To protect any system, the first requirement is to know its vulnerabilities. To do so, a vulnerability analysis methodology dedicated to analog circuit has been developed. Using the results of this analysis, countermeasures can be designed during the development of the circuit and not at the end. The circuit security is thus improved without dramatically increasing its cost in terms of design time. The analysis of a clock system generator, an analog IP widely used in current SoCs and composed with various sub-circuits, has shown fault attacks using Laser Photoelectric Stimulation (LPS) or supply voltage glitches as important threats. After having identified the 2 previous attacks types as major threats, their effects on analog circuits are analyzed. Existing countermeasures are then compared and evaluated for the protection of analog IPs. To complete these solutions, two analog detectors have been designed to detect laser and supply voltage glitch attacks considering SoCs level constraints. Electrical test of these detectors processed on CMOS 28nm FD-SOI technology proved their efficiency. Theoretical vulnerability analysis has shown some difficulties. Indeed, analog circuits are sensitive to numerous parametrical faults. Also, the high interconnection of various sub-circuits makes the faults propagation analysis quite difficult. To help this analysis, electrical simulations at transistor level are necessary. These simulations are quite long and, so the behavioral modeling of analog circuits to help the analysis of supply voltage glitch attack effects has been studied. To do so, the developed models must be developed according different constraints presented in this report and applied to the behavioral modeling of a real analog circuit. This illustration proved that behavioral models can be used to help to identify which attack shapes are the most likely to induce faults in the circuit.

L’évolution des performances des dispositifs microélectroniques se heurte aux limites de la miniaturisation. Les contraintes mécaniques constituent un levier potentiel pour dépasser ces limitations. Il est cependant indispensable de bien maitriser leur génération et de connaitre leur influence sur le transport dans le canal. L’objectif de cette thèse vise à étudier l’évolution de la contrainte mécanique en technologie CMOS et son influence sur le transport électronique dans des technologies sub-20nm réalistes. Ce travail s’appuie sur des simulations mécaniques bidimensionnelles. Différentes architectures TriGate et FDSOI sont alors étudiées. Les contraintes obtenues sont comparées à des mesures issues de la diffraction électronique. Plusieurs méthodes de caractérisation électrique et d’extraction de paramètres de transistor MOS sont utilisées. Parmi elles figurent notamment la technique de l’extraction de la mobilité par magnétorésistance. Nous analysons les variations de mobilité en fonction des dimensions et de leur impact sur la contrainte mécanique. Enfin nous utilisons la simulation TCAD pour explorer le potentiel de nouvelles briques technologiques innovantes en voie de développement pour des générations ultérieures. Parmi elles, citons l’intégration des zones fortement contraintes par des source-drains en SiGe à fort pourcentage en germanium ou l’impact des relaxations introduites par l’utilisation des grilles sacrificielles au cours de la fabrication. Dans cette perspective, des simulations électriques basées sur une approche piézo-résistive deviennent indispensables. / In microelectronic, the device's performance evolution is limited by the down-scaling. The mechanical stresses are a potential mobility booster to overcome these limitations. However it is essential to properly control their process integration and to understand their influence on channel transport. The aim of this thesis is to study the mechanical stress evolution in CMOS technology and its impact on electronic transport in sub-20nm realistic technologies. This work is based on bidimensional mechanical simulations. Different architectures FDSOI and TriGate are then studied. The simulated stress maps are compared to experimental characterization from electron diffraction. Several methods of electrical characterization and extraction of MOS transistor are used, especially the magnetoresistance technique. We analyze the mechanical stress impact on the mobility variations according to geometrical dimensions. Finally, we use the TCAD simulation in order to explore the potential of new innovative devices under development for future generations. Among them, the integration of high germanium concentration in source-drain regions or the impact of relaxations induced by dummy gates in process flow. In this perspective, electrical simulations based on piezoresistive approach become essential.

Ces dernières décennies ont vu l'émergence des microsystèmes électromécaniques (MEMS) grâce notamment aux techniques de fabrication employées dans l'élaboration des transistors. L'utilisation de différentes propriétés physiques (électroniques, mécaniques, optiques par exemple) a permis la construction d'un large panel de capteurs miniaturisés. Résultant de la miniaturisation sub-micrométrique des MEMS, les nanosystèmes électromécaniques (NEMS) constituent un tout nouveau type d'objet permettant d'adresser des applications nécessitant un très haut niveau de sensibilité et de résolution, comme la détection de gaz, la spectrométrie de masse ou la reconnaissance de molécules faisant traditionnellement appel à des machines très volumineuses. L'utilisation de ces NEMS requiert cependant un circuit électronique CMOS afin de lire et d'exploiter le signal en sortie de résonateur et servant également à la mise en place d'une boucle oscillante (boucle à verrouillage de phase ou boucle auto oscillante par exemple), architecture idéale pour la détection de masse en temps réel. L'intégration du circuit CMOS avec les résonateurs NEMS constitue un aspect critique quant à la fabrication de capteurs de haute performance. La solution optimale consiste à intégrer de manière monolithique ces deux parties sur la même puce, permettant ainsi de réduire la dimension du capteur et d'améliorer la transmission du signal électrique entre les résonateurs et le circuit CMOS. Cette thèse propose dans un premier temps d'analyser l'intérêt de cette co-intégration du point de vue électrique. Dans un second temps, cette thèse portera sur le développement d'une approche originale visant à co-intégrer de manière monolithique les nano résonateurs au-dessus du circuit CMOS et des interconnexions. La dernière partie portera sur le design d'un détecteur de masse composé d'un réseau compact de NEMS co-intégré CMOS. / During these last decades, Very Large Scale Integration (VLSI) techniques, well developed for transistors, have been used for the Micro ElectroMechanical Systems (MEMS) devices. Thanks to the combination of different physical properties (such as electronic, mechanical, optical etc.) the fabrication of various kinds of miniaturized sensors has been made possible. The sub-µm downscaling of MEMS has allowed the emergence of a new kind of devices called NEMS (for Nano ElectroMechanical Systems) and the possible use of the electromechanical systems in specific applications in which a high level of sensitivity and resolution is necessary, such as gas sensing, mass spectrometry and molecules recognition, to replace traditional bulky machines. Nevertheless, the use of these NEMS requires a CMOS electronic to enhance NEMS resonators readout and to implement closed-loop oscillators (e.g. phase-locked loop or self-oscillating loop) that provide real-time mass measurements. The integration of the electronic circuit with the resonators is a critical aspect for the fabrication of high performance sensors. The best way consists in monolithically processing these two parts on the same die allowing a size reduction of the sensor and an optimal signal transmission between the NEMS resonators and the CMOS circuit. In a first time, this thesis proposes to analyze the interest of this co integration from an electrical point of view. In a second time, this thesis deals with the development of a 3D co integration in which the nano resonators are fabricated above the CMOS circuit and the interconnections. The final part is focused on the layout design considerations for the implementation of a compact mass sensor based on a NEMS array co integrated with a CMOS.

Les mémoires résistives non volatiles à bases d'oxydes métalliques suscitent un intérêt croissant chez les industriels. Plus particulièrement, les mémoires non volatiles à base d'oxydes (OxRRAM) offrent des temps de programmation et d'accès très court, une faible consommation énergétique, un coût par bit très concurrentiel et une facilité de co-intégration dans le back-end avec du CMOS avancé. Ce travail de thèse a pour objectif le développement d'une mémoire OxRRAM facilement intégrable dans une technologie de fabrication CMOS avancée afin de montrer les avantages en vue de leur application dans des SoC. Une première étape fut la fabrication et l'analyse des cellules mémoires OxRRAM intégrant différents oxydes métalliques afin de choisir la solution la plus adaptée à être intégrée dans une technologie CMOS 65nm et 28nm. Des techniques de mesures dédiées ont été mises en place afin d'établir l'impact du diélectrique sur le fonctionnement de la mémoire OxRRAM en termes de polarisation, de temps de programmation, de courant de programmation et de mécanismes de transition. Des études statistiques et de fiabilité des différents états du point mémoire ont été aussi réalisées. La modélisation associée a permis de mieux comprendre les mécanismes de vieillissements et prédire des lois de durée de vie sous champ et en température des état écrit et effacé de la cellule OxRRAM. Les données expérimentales obtenues sur les cellules ont ensuite permis de concevoir et d'optimiser un circuit d'évaluation statistique de 16 Kbit en technologie CMOS 28nm en tenant compte de toutes les contraintes de design analogique. / Oxide-based Resistive Random Acces Memories (OxRRAM) are nowadays considered among the most promising solutions for future generation of low-cost embedded non-volatile memories. The advantages of these memories are the scalability, low power consumption, high speed, complementary metal oxide semiconductor technology (CMOS) compatibility and ease of fabrication (the memory cell consisting of a Metal–Insulator– Metal (MIM) structure integrated in the back-end-of-line, plus an addressing element, i.e. a transistor or a diode) . The potential applications range from consumer – communications to automotive – industrial. This work deals with the development of an OxRRAM demonstrator into an advanced CMOS technology for System on Chip (SoC) application. We discuss the impact of different dielectrics materials (Ta2O5, ZrO2 and HfO2) and electrodes (Pt, Ti, TiN) on the memory performances and reliability in order to choose the best couple dielectric/electrode. We focus on the understanding of the memory switching physics that is involved in the programming of OxRRAM bit-cells. The failure and transition mechanism are presented for lifetime prediction. Some methodologies are presented in this PhD thesis for the optimization of the OxRRAM bit-cell performances and sizes according to a targeted Mutliple Time Programmable (MTP) memory application. We developed analog block systems to control and address the OxRRAM bit-cell taking to account the bipolar switching characteristics of the devices. Finally, these solutions are to be validated using a 1-kb OxRRAM demonstrator yet designed and fabricated in a logic 28-nm node CMOS technology. Keywords: Oxide Resistive memory (OxRRAM), High-k, MIM, CMOS, Characterization, Reliability, Modeling, Analog Design, Simulation.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

Ce travail de thèse étudie les moyens d’étendre les zones de charge d’espace des photodiodes PN d’un imageur CMOS afin d’améliorer la collection des charges photogénérées dans le silicium, en particulier dans le proche infra-rouge. Deux possibilités sont abordées : l’augmentation de la tension de polarisation des photodiodes et la diminution du dopage du silicium. Dans un premier temps, une étude théorique articulée autour de modèles analytiques et de simulations TCAD montre les difficultés technologiques pour parvenir à une augmentation de polarisation des photodiodes, ainsi que les conséquences de l’utilisation de substrats résistifs sur les éléments de l’imageur et sur ses performances. Ces simulations permettent de définir les éléments influençant l’extension de la charge d’espace d’un pixel. Sur la base de cette étude, un imageur CMOS à pixel 3T a été développé et fabriqué sur substrat float-zone très fortement résistif afin de valider les observations théoriques. La caractérisation de ce composant confirme la dépendance de la zone dépeuplée à la conception du pixel. Elle démontre également la corrélation entre l’extension des zones dépeuplées et les performances électro-optiques. Des règles de conception sont définies permettant d’optimiser les performances tout en limitant les courants de fuite entre pixels. / This work investigates solutions to extend the space charge region in CMOS image sensors in order to enhance the photo-generatedcharge collection from near-infraredradiations. Photodiode bias increase and low doped silicon substrate are proposed for this study. A theoretical analysis based on analytical model and TCAD simulations shows technological difficulties for photodiode bias in crease and the consequences of using high-resistivity silicon substrates on the imager performances. Space charge region dependency on the pixel design is assessed through simulations. A 3T pixel CMOS image sensor was developed and fabricated on a high resistivity float-zone silicon. Sensor characterization confirms space charge region dependency on the pixel design and the correlation between its extension and electro-optical performances. Design rules are defined to optimize electro-optical performances while limiting punchthrough current in the pixels array.

Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas. / Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.

The increasing complexity of digital circuits forces the use of new technologies. New technologies have the advantage of reducing the circuit size and power consumption coupled with operation speed increasement. Most of signal processing operations migrated to the digital domain, thus, basic blocks like AD converters are needed in mixed-signal systems. Analog-todigital converters based on Sigma-Delta (ΣΔ) modulators stand out among the existing architectures because they cover a wide range of applications. The most common implementation of ΣΔ modulators in CMOS technology is based in switched-capacitor technique (SC), mainly due to its high performance and excellent linearity. However, the continuous reduction in the transistor physical dimensions requires a proportional reduction in the supply voltage levels, making difficult the design of analog circuits with conventional topologies. To overcome this problem, design techniques to analog circuits compatible with these new technologies were developed. This is the case of the technique known as switched-current (SI), which uses samples in the current domain to represent the signal information. This work presents the design of a switched-current Sigma-Delta modulator (SI-ΣΔM) using an architecture oriented to low-distortion applications. The architecture s main characteristic is the reduced sensitivity to integrator nonlinearities, leading to a significant increase in the signal-to-noise ratio (SNR) and dynamic range (DR) values, moreover, it permits the design of high-order modulators intrinsically stable. To demonstrate and verify the performance of the used strategy, based on a combination of circuit techniques and topology, a cascade 2-2 SI-ΣΔM was designed in a CMOS XFAB XC06 technology. Postlayout simulations show that the SNR reaches a maximum value of 80 dB and a dynamic range of approximately 87 dB, implying an effective resolution of 14.15 bits considering 20 kHz bandwidth. The prototype was sent to manufacturing and will be subject to laboratory tests when it returns. / A crescente complexidade dos circuitos digitais força o uso de novas tecnologias de fabricação. A mudança para tecnologias mais avançadas tem como vantagem a redução do tamanho do circuito e a diminuição do consumo de energia aliados ao aumento da velocidade de operação. Grande parte das operações envolvendo processamento de sinais migraram para o domínio digital, portanto, blocos básicos como conversores AD são necessários em sistemas de sinal misto. Conversores AD com base em moduladores do tipo Sigma-Delta (ΣΔ) destacam-se entre as arquiteturas existentes por cobrir uma ampla gama de aplicações. A implementação mais usual de moduladores ΣΔ em tecnologia CMOS baseia-se na técnica de capacitor-chaveado (SC), devido, principalmente, à sua elevada performance e excelente linearidade. Entretanto, a contínua redução das dimensões físicas dos transistores tem exigido uma redução proporcional dos níveis de tensão de alimentação, dificultando o projeto de circuitos analógicos com topologias convencionais. Para contornar este problema, técnicas de projeto de circuitos analógicos compatíveis com essas novas tecnologias foram desenvolvidas. Este é o caso da técnica conhecida como corrente chaveada (SI), que utiliza amostras sob a forma de corrente para a representação de sinais. Neste trabalho é apresentado o projeto de um modulador ΣΔ em modo corrente (SI-ΣΔM) empregando uma arquitetura orientada à aplicações de baixa distorção. Esta arquitetura tem como principal característica a reduzida sensibilidade às não-linearidades do integrador, conduzindo a uma significante melhora no valor da relação sinal-ruído (SNR) e faixa de excursão dinâmica (DR), além de permitir a concepção de moduladores ΣΔ de elevada ordem intrinsecamente estáveis. Para demonstrar e comprovar a performance da estratégia empregada, baseada na combinação de técnicas de circuito e de topologia, projetou-se um modulador SI-ΣΔ cascata 2-2 na tecnologia XFAB CMOS XC06. Simulações elétricas pós-layout revelam que o SNR atinge um valor máximo de 80 dB e uma faixa dinâmica de aproximadamente 87 dB, inferindo uma resolução efetiva de 14,15 bits considerando uma banda de interesse de 20 kHz. Por fim, o protótipo desenvolvido foi enviado para fabricação e será alvo de testes em laboratório quando retornar.