O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

Cette étude évalue le potentiel, comme détecteur de rayons X, des capteurs à pixel CMOS conçus pour la trajectométrie des particules chargée. Nous démontrons l’intérêt de la construction d’une image par comptage de photons uniques pour la définition de celle-ci. Un dispositif exploitant une source X est développé pour mesurer la résolution spatiale sur l’impact des photons. Une simulation complète sous GEANT4 montre que le système permet d’estimer cette résolution avec une incertitude de 2 µm. L’application du protocole caractérise la détection directe des rayons X de basse énergie (< 10 keV) par un capteur CMOS avec une résolution de 52 lp/mm. Une méthode de détection indirecte, couplant un cristal de CsI(Tl) finement segmenté au capteur CMOS, est employée pour les énergies supérieures à 10 keV. La résolution spatiale dans ces conditions atteint 15 lp/mm. Une simulation détaillée explique cette performance limitée par les caractéristiques d’émission de lumière du cristal employé. / This work investigates the potential application of CMOS pixel sensors, designed for particle tracking, for the detection of X rays. We explain how the image definition can be improved exploiting the single photon counting technique. An experimental system, based on an X ray source, is developed to measure the single point resolution of photons. Thanks to a full GEANT4 simulation of the device, the evaluation uncertainty is predicted to be 2 µm. We apply our method to the direct detection of low energy (< 10 keV) X rays by a CMOS pixel to measure a spatial resolution of 52 lp/mm. For higher energies, an hybrid device, coupling a CSi(Tl) highly segmented crystal with a CMOS sensor, is used. The spatial resolution reaches in this case 15 lp/mm. A detailed simulation study demonstrated that this limited performance is related to the characteristics of the light emitted by the crystal.

Depuis plus d'un demi-siècle, le monde de la microélectronique est rythmé par une course à la miniaturisation de son élément central, le transistor MOS, dans le but d'améliorer la densité d'intégration, les performances et le coût des circuits électroniques intégrés. Depuis plusieurs générations technologiques maintenant, la simple réduction des dimensions du transistor n'est plus suffisante et de nouveaux modules technologiques (utilisation de la contrainte, empilement de grille high-k/métal…) ont du être mis en place. Cependant, le transistor MOS conventionnel, même optimisé, ne suffira bientôt plus à répondre aux attentes toujours plus élevées des nouvelles technologies. De nouvelles architectures doivent alors être envisagées pour épauler puis, à terme, remplacer la technologie BULK. Dans ce contexte, cette thèse porte sur l'étude, la fabrication et la caractérisation électrique des architectures à film mince que sont le SOI localisé (ou LSOI) et le double grille planaire à grille enrobante (ou GAA). Les résultats obtenus mettent ainsi en évidence l'intérêt de ces dispositifs qui permettent une réduction du courant de fuite (et donc de la consommation), un excellent contrôle des effets électrostatiques et fonctionnent sans dopage canal (faible variabilité) tout en proposant de très bonnes performances statiques. L'impact d'une orientation de substrat (110) sur les propriétés de transport dans les transistors LSOI est également étudié. Ce travail de thèse garde comme ligne de mire la réalisation d'une plateforme basse consommation complète, impliquant une éventuelle intégration hybride avec des dispositifs BULK et la possibilité d'offrir plusieurs niveaux de tension de seuil, le tout sur une même puce. / For more than 50 years, microelectronic industry is driven by a race to the miniaturisation of its central element, the MOS transistor, to improve the integration density, the performances and the cost of the electronic integrated circuits. Since the adoption of 100nm node, the only reduction of the dimensions of the transistor is no more sufficient and new technological modules (use of strain, high-k/metal gatestack…) have been introduced. However, conventional MOSFET, even opimized, will soon be unable to reach the specifications, always higher, of new technologies. Then, new structures should be considered to help and, finally, to replace the BULK technology. In this context, the work concerns the study, the fabrication and the electrical characterization of the thin film devices : Localized-SOI (LSOI) and planar gate-all-around (GAA). The obtained resultats point out the interest of such devices which allow the reduction of the leakage current (and thus the consumption), an excellent control of electrostatics and are able to work with an undoped channel while offering very good static performances. Impact of (110) substrates on transport properties in LSOI transistors is also studied. This work focuses on the integration of a full low-power platform, what induces the possibility of an hybrid integration with BULK devices and to offer several threshold voltages, everything on the same chip.

Le traitement d’images classique est basé sur l’évaluation des données délivrées par un système à basede capteur de vision sous forme d’images. L’information lumineuse captée est extraiteséquentiellement de chaque élément photosensible (pixel) de la matrice avec un certain cadencementet à fréquence fixe. Ces données, une fois mémorisées, forment une matrice de données qui estréactualisée de manière exhaustive à l’arrivée de chaque nouvelle image. De fait, Pour des capteurs àforte résolution, le volume de données à gérer est extrêmement important. De plus, le système neprend pas en compte le fait que l’information stockée ai changé ou non par rapport à l’imageprécédente. Cette probabilité est, en effet, assez importante. Ceci nous mène donc, selon « l’activité »de la scène filmée à un haut niveau de redondances temporelles. De même, la méthode de lectureusuelle ne prend pas en compte le fait que le pixel en phase de lecture a la même valeur ou non que lepixel voisin lu juste avant. Cela rajoute aux redondances temporelles un taux de redondances spatialesplus ou moins élevé selon le spectre de fréquences spatiales de la scène filmée. Dans cette thèse, nousavons développé plusieurs solutions qui visent contrôler le flot de données en sortie de l’imageur enessayant de réduire les redondances spatiales et temporelles des pixels. Les contraintes de simplicité etd’« intelligence » des techniques de lecture développées font la différence entre ce que nousprésentons et ce qui a été publié dans la littérature. En effet, les travaux présentés dans l’état de l’artproposent des solutions à cette problématique, qui en général, exigent de gros sacrifices en terme desurface du pixel, vu qu’elles implémentent des fonctions électroniques complexes in situ.Les principes de fonctionnement, les émulations sous MATLAB, la conception et les simulationsélectriques ainsi que les résultats expérimentaux des techniques proposées sont présentés en détailsdans ce manuscrit. / The classical image processing is based on the evaluation of data delivered by a vision sensor systemas images. The captured light information is extracted sequentially from each photosensitive element(pixel) of the matrix with a fixed frequency called frame rate. These data, once stored, form a matrixof data that is entirely updated at the acquisition of each new image. Therefore, for high resolutionimagers, the data flow is huge. Moreover, the conventional systems do not take into account the factthat the stored data have changed or not compared to the previously acquired image. Indeed, there is ahigh probability that this information is not changed. Therefore, this leads, depending on the "activity"of the filmed scene, to a high level of temporal redundancies. Similarly, the usual scanning methodsdo not take into account that the read pixel has or not the same value of his neighbor pixel read oncebefore. This adds to the temporal redundancies, spatial redundancies rate that depends on the spatialfrequency spectrum of the scene. In this thesis, we have developed several solutions that aim to controlthe output data flow from the imager trying to reduce both spatial and temporal pixels redundancies. Aconstraint of simplicity and "Smartness" of the developed readout techniques makes the differencebetween what we present and what has been published in the literature. Indeed, the works presented inthe literature suggest several solutions to this problem, but in general, these solutions require largesacrifices in terms of pixel area, since they implement complex electronic functions in situ.The operating principles, the emulation in MATLAB, the electrical design and simulations and theexperimental results of the proposed techniques are explained in detail in this manuscript

Ce travail de recherche vise à concevoir un système de vision à faible consommation d'énergie pour les réseaux de capteurs sans fil. L'imageur en question doit respecter les contraintes spécifiques des applications multimédias pour les réseaux de capteurs de vision sans fil. En effet, de par sa nature, une application multimédia impose un traitement intensif au niveau du noeud et un nombre considérable de paquets à échanger à travers le lien radio, et par conséquent beaucoup d'énergie à consommer. Une solution évidente pour diminuer la quantité de données transmise, et donc la durée de vie du réseau, est de compresser les images avant de les transmettre. Néanmoins, les contraintes strictes des noeuds du réseau rendent inefficace en pratique l'exécution des algorithmes de compression standards (JPEG, JPEG2000, MJPEG, MPEG, H264, etc.). Le système de vision à concevoir doit donc intégrer des techniques de compression d'image à la fois efficaces et à faible complexité. Une attention particulière doit être prise en compte en vue de satisfaire au mieux le compromis "Consommation énergétique - Qualité de Service (QoS)". / This research aims to develop a vision system with low energy consumption for Wireless Sensor Networks (WSNs). The imager in question must meet the specific requirements of multimedia applications for Wireless Vision Sensor Networks. Indeed, a multimedia application requires intensive computation at the node and a considerable number of packets to be exchanged through the transceiver, and therefore consumes a lot of energy. An obvious solution to reduce the amount of transmitted data is to compress the images before sending them over WSN nodes. However, the severe constraints of nodes make ineffective in practice the implementation of standard compression algorithms (JPEG, JPEG2000, MJPEG, MPEG, H264, etc.). Desired vision system must integrate image compression techniques that are both effective and with low-complexity. Particular attention should be taken into consideration in order to best satisfy the compromise "Energy Consumption - Quality of Service (QoS)".

L’architecture FDSOI (silicium sur isolant totalement déserté) permet une amélioration significative du comportement électrostatique des transistors MOSFETs pour les technologies avancées et est employée industriellement à partir du noeud 28 nm.L’implémentation de protections contre les décharges électrostatiques (ESD pour« Electro Static Discharge ») dans ces technologies reste un défi. Alors que l’approche standard repose sur l’hybridation du substrat SOI (gravure de l’oxyde enterré : BOX)permettant de fabriquer des dispositifs de puissance verticaux, nous nous intéressons ici à des structures dans lesquelles la conduction s’effectue latéralement, dans le film de silicium. Dans ces travaux, des approches alternatives utilisant des dispositifs innovants(Z²-FET et BBC-T) sont proposées. Leurs caractéristiques statiques, quasi-statiques et transitoires sont étudiées, par le biais de simulations TCAD et de caractérisations électriques. / FDSOI architecture (Fully Depleted Silicon On Insulator) allows a significantimprovement of the electrostatic behavior of the MOSFETs transistors for the advancedtechnologies. It is industrially employed from the 28 nm node. However, theimplementation of ESD (Electrostatic Discharges) protections in these technologies isstill a challenge. While the standard approach relies on SOI substrate hybridization (byetching the BOX (buried oxide)), allowing to fabricate vertical power devices, we focushere on structures where the current flows laterally, in the silicon film. In this work,alternative approaches using innovative devices (Z²-FET and BBC-T) are proposed. Theirstatic, quasi-static and transient characteristics are studied in detail, with TCADsimulations and electrical characterizations.

Cette thèse porte sur l'élaboration et la caractérisation des grilles métalliques en TiN, aluminium et lanthane pour les technologies CMOS gate-first à base d'oxyde high-k HfSiON. L'effet de l'épaisseur et de la composition des dépôts métalliques a été caractérisé sur les paramètres de la technologie 32/28nm. Ces résultats ont été reliés à une variation de travail de sortie au vide du TiN, à des dipôles induits par l'Al et le La à l'interface HfSiON/SiON et à leur diminution aux petites épaisseurs de SiON (roll-off). Nous avons montré que l'aluminium déposé sous forme métallique dans le TiN cause une diminution de son travail de sortie, opposée au faible dipôle positif induit par l'Al. Nous avons évalué l'influence du roll-off pour ces différents métaux et mis en évidence pour la première fois sa forte dépendance avec l'épaisseur de lanthane déposée. Le développement de procédés de dépôt de TiN, Al, La a permis d'accroître les bénéfices de ces matériaux pour la technologie CMOS 32/28nm. / This thesis is about the manufacturing and the characterization of TiN, aluminum and lanthanum metal gate for high-k based 32/28nm CMOS technologies. The effect of metal gate layer thickness and composition has been characterized on 32/28nm technology parameters. These results have been related to a change in the TiN vacuum work function, to Al- and La- induced dipoles at the HfSiON/SiON interface or their lowering on thin SiON (roll-off). We have shown that metallic aluminum introduced in the TiN metal gate causes a work function lowering, opposed to the weak Al-induced dipole. We have evaluated the roll-off influence for theses different metals. For the first time we report the strong roll-off dependence with the deposited lanthanum thickness. Newly developed TiN, Al, La deposition processes have brought benefits for the CMOS 32/28nm technology

Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2010-08-30Bitstream added on 2014-06-13T19:27:59Z : No. of bitstreams: 1 pereira_mva_me_ilha.pdf: 1675496 bytes, checksum: e8bfb14cdd90155eb3c43096d4c160df (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Este trabalho apresenta um Oscilador Controlado por Corrente (CCO) com configuração em anel usando tecnologia CMOS, com melhorias na faixa de operação e ruído de fase. O oscilador proposto tem uma faixa de oscilação de 0,0989 GHz a 1,2 GHz com uma corrente de controle com um intervalo de 0,1 mA a 3 mA com uma potência dissipada de 11,8 mW. A arquitetura apresenta uma melhoria na fase de ruído de -7 dBc / Hz em relação a um oscilador em anel de três estágios (VCO), também apresentado neste trabalho. A estrutura proposta é baseada na mudança da entrada de controle do oscilador e também em modificações nas polarizações dos transistor de carga do estágio de atraso. Estas mudanças, além de aumentar a faixa de operação do oscilador e diminuir o efeito do ruído de fase, também reduzem a variação da amplitude do sinal de saída que acontece a medida que a frequência de operação aumenta ou diminui. Simulações realizadas com ambos os osciladores, confirmam os resultados. / This dissertation presents a Current Controlled Oscillator (CCO-Current-Controlled Oscillator) at ring configuration using CMOS (Complementary Metal-Oxide-Semiconductor) technology, with improvements in operating range and phase noise. The proposed oscillator has an oscillation range of 98.959 MHz to 1.2 GHz with a current control with a range of 0.1 mA to 3 mA with a power dissipation of 11.8 mW. The architecture shows an improvement in phase noise of -7 dBc / Hz when compared with a ring oscillator in three stages (VCO-Voltage- Controlled Oscillator), also presented in this paper. The proposed structure is in the change of input control and also in the polarizations of the load transistor stage of delay. These changes, in modifications increase the operations range of the oscillator, reduce the phase noise and minimize the amplitude variation of the output signal when the frequency operation increase or decrease. Simulations with both oscillators and their comparisons confirm these results.

Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas. / Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.