As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clock inaccuracies to a small fraction of the clock period. In this thesis, a crude deskew buffer (CDB) is designed to facilitate an adaptive deskewing scheme that reduces the clock skew in an ASIC clock network under manufacturing process, supply voltage, and temperature (PVT)variations. The crude deskew buffer adopts a DLL structure and functions on a 1GHz nominal clock frequency with an operating frequency range of 800MHz to 1.2GHz. An approximate 91.6ps phase resolution is achieved for all simulation conditions including various process corners and temperature variation. When the crude deskew buffer is applied to seven ASIC clock networks with each under various PVT variations, a maximum of 67.1% reduction in absolute maximum clock skew has been achieved. Furthermore, the maximum phase difference between all the clock signals in the seven networks have been reduced from 957.1ps to 311.9ps, a reduction of 67.4%. Overall, the CDB serves two important purposes in the proposed deskewing methodology: reducing the absolute maximum clock skew and synchronizes all the clock signals to a certain limit for the fine deskewing scheme. By generating various clock phases, the CDB can also be potentially useful in high speed debugging and testing where the clock duty cycle can be adjusted accordingly. Various positive and negative duty cycle values can be generated based on the phase resolution and the number of clock phases being “hot swapped”. For a 500ps duty cycle, the following values can be achieved for both the positive and negative duty cycle: 224ps, 316ps, 408ps, 592ps, 684ps, and 776ps.

Modern physical experiments often demand advanced instrumentation based on advances in  technology. This work describes four instrumentation physics projects that are based on modern, high-capacity Field-Programmable Gate Arrays, making use of their versatility, programmability, high bandwidth communication interfaces and signal processing capabilities. In the first project, a jet-finding algorithm for the ATLAS detector at the LHC experiment at CERN was developed and implemented, and different verification methods were created to validate the functionality and reliability. The experiment uses a three level trigger system, where the first level uses custom FPGA-based hardware for analysis of collision events in real-time. The second project was an advanced timing and triggering distribution system for the new European X-Ray Free Electron Laser (XFEL) facility at DESY in Hamburg. XFEL will enable scientists to study nano structures on the atomic scale. Its laser pulses will have the strongest peak power in the world with extremely short duration and a high repetition rate, which will even allow filming of chemical reactions. The timing system uses modern FPGAs to distribute high-speed signals over optical fibers and to deliver clocks and triggers with high accuracy. The third project was a new data acquisition board based on high-speed ADCs combined with high-performance FPGAs, to process data from segmented Ge-detectors in real-time. The aim was to improve system performance by greatly oversampling and filtering the analog signals to achieve greater effective resolution. Finally, an innovative solution was developed to replace an aging system used at CERN and Stockholm University to test vital electronics in the Tile Calorimeters of the ATLAS detector system. The new system is entirely based on a commercial FPGA development board, where all necessary custom communication protocols were implemented in firmware to emulate obsolete hardware. / Inom området instrumenteringsfysik bedrivs forskning och utveckling av avancerade instrument, som används inom moderna fysikexperiment. Denna avhandling beskriver fyra projekt där programmerbara kretsar (FPGA) har nyckelfunktioner för att lösa krävande instrumenteringsuppgifter. Den första projektet beskriver utveckling och implementering av en algoritm för detektering av partikelskurar efter partikelkollisioner i LHC-experimentets ATLAS-detektor. Experimentet genererar 40 miljoner händelser per sekund, som måste analyseras i real-tid med hjälp av snabba parallella algoritmer. Resultatet avgör vilka händelser som är tillräckligt intressanta för fortsatt noggrannare analys. Den andra projektet beskriver utvecklingen av ett system som distribuerar klock- och trigger-signaler över ett 3 kilometers experimentområde med extrem precision, i den nya röntgenlaseracceleratorn XFEL vid DESY i Hamburg. Vid XFEL kommer man utforska nanostrukturer och till och med filma molekylers kemiska reaktioner. I den tredje projektet beskrivs utvecklingen av ett höghastighets datainsamlingssystem, för segmenterade Ge-detektorer. Genom att översampla signalen med hög hastighet kan man uppnå en bättre noggrannhet i mätningen än vad AD-omvandlarens egna upplösning medger. Detta leder i sin tur  till förbättrade systemprestanda. Slutligen beskrivs en innovativ lösning till ett test system för den elektronik, som Stockholms universitet har levererat till ATLAS detektorn. Det nya systemet ersätter det föregående testsystemet, som är baserad på föråldrade inte längre tillgängliga komponenter. Det nya systemet är dessutom också billigare eftersom det är baserat på ett standard FPGA utvecklingskort. / ATLAS experiment of the Large Hadron Collider experiment / European X-ray Free Electron Laser

No description available.

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.

In this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for. Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers are significant improvements over the prior art in standing wave based PLLs.

Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.

Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded. The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz. In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz. / Mikroprocessorer till dagens datorer innehåller hundratals miljoner transistorersom utför åtskilliga miljarder komplexa databeräkningar per sekund. I stort settalla operationer i dagens mikroprocessorer ordnas genom att synkronisera demmed en eller flera klocksignaler. Dessa signaler behöver ofta distribueras överhela chippet och driva alla synkroniseringskretsar med klockfrekvenser pååtskilliga miljarder svängningar per sekund. Detta utgör en stor utmaning förkretsdesigners på grund av att klocksignalerna behöver ha en extremt högtidsnoggranhet, vilket blir svårare och svårare att uppnå då chippen blir större.Idealt ska samma klocksignal nå alla synkroniseringskretsar exakt samtidigt föratt uppnå optimal prestanda, avvikelser ifrån denna ideala funktionalitet innebärlägre prestanda. Ytterliggare utmaningar inom klockning av digitala chip, är atten betydande andel av processorns totala effekt förbrukas i klockdistributionen.Därför krävs nya innovativa kretslösningar för att lösa problemen med bådeonoggrannheten och den växande effektförbrukningen i klockdistributionen. att lösa de problem som finns i dagens konventionella kretslösningar förklocksignaler på chip. I den första delen av denna avhandling presenterasforskningsresultat på oscillatorer vilka utgör mycket viktiga komponenter igeneringen av klocksignalerna på chippen. Teoretiska studier avfaslåsningsfenomen i integrerade klockoscillatorer har presenterats. Studiernahar visat att det finns stor potential för reducering av tidsonoggrannhet iklocksignalerna med hjälp av faslåsning till en annan signal. I avhandlingensförsta del presenteras även en diskussion om klockgeneratorer baserade påfördröjningslåsta element. Dessa fördröjningslåsta elementen, kända som DLLkretsar, har egenskapen att de kan fördröja en klocksignal med en bestämdfördröjning, vilket möjliggör skapandet av multipla klockfaser. En nykretsteknik har introducerats för klockgenerering av multipla klockfaser vilken reducerar effektförbrukningen och onoggranheten i DLL-baseradeklockgeneratorer. I denna teknik används en övervakningskrets vilken ser till attalla delar i klockgeneratorn utnyttjas effektivt och att oanvända kretsarinaktiveras. Baserat på experimentalla mätresultat från tillverkade testkretsar ikisel har en effektbesparing på mer än 10% uppvisats vid klockfrekvenser påupp till 2.5 GHz tillsammans med en betydande ökning av klocknoggranheten. I avhandlingens andra del diskuteras en klockdistributionsteknik som baseraspå resonans, vilken har visat sig vara ett lovande alternativ till konventionllabufferdrivna klockningstekniker när det gäller minskande effektförbrukning.Principen bakom tekniken är att återanvända den energi som utnyttjas till attladda upp klocklasten. Teoretiska resonemang har visat att storaenergibesparingar är möjliga, och praktiska mätningar på tillverkadeexperimentchip har visat att effektförbrukingen kan mer än halveras. Ettproblem med den föreslagna klockningstekniken är att data som används iberäkningarna kretsen direkt påverkar klocklasten, vilket även påverkarnoggranheten på klocksignalen. För att komma till rätta med detta problemetpresenteras en teknik, baserad på forskning inom ovan nämndafaslåsningsfenomen, som kan minska onoggrannheten på klocksignalen medöver 50%. Både effektbesparingen och förbättringen av tidsnoggranheten harverifierats med hjälp av mätningar på tillverkade chip vid frekvenser upp mot1.8 GHz.

Les arbres classiques de distribution du signal d’horloge au sein des microprocesseurs synchrones présentent un certain nombre de limitations : skew, jitter, limitation de la fréquence, influence de perturbations et de dispersions quelles que soient leurs natures. Ces facteurs, critiques pour les microprocesseurs modernes complexes, sont devenus la raison principale qui a poussé à la recherche d’autres types d’architecture de génération et de distribution du signal d’horloge. Un exemple d’un tel système alternatif est le réseau de PLLs couplées, où les PLLs sont géographiquement distribuées sur la puce, et génèrent des signaux d’horloge locaux qui sont ensuite synchronisés, en temps réel, par un échange d’information entre les PLLs voisines et une rétroaction locale réalisé par leur correcteurs. La nature active du réseau de PLLs de génération et de distribution du signal d’horloge, qui peut permettre de surpasser les limitations mentionnées plus tôt, oblige à sortir du cadre classique des outils et des méthodes de la Microélectronique habituellement appliqués à l’étude et à la conception de ce type de systèmes. En effet, les aspects dynamiques de bouclage et de transformation de signaux au sein de tels systèmes complexes rendent leur conception extrêmement difficile voire parfois impossible. La difficulté principale consiste en un changement des propriétés d’un sous-système local indépendant par rapport aux propriétés du même sous-système faisant partie du réseau. Effectivement, il existe beaucoup de méthodes et d’outils de conception d’une PLL isolée garantissant un comportement et des propriétés locales désirés. Néanmoins, ces propriétés désirées locales, selon la topologie d’interconnexion considérée, ne sont pas forcément conservées quand il s’agit d’un réseau de PLLs interconnectées et de son comportement global. Le but principal de cette thèse est ainsi de développer une méthode de synthèse de la loi de commande décentralisée réalisée au sein de chaque sous-système (tel qu’une PLL) assurant le comportement désiré pour le réseau global. Une méthode de transformation du problème de synthèse globale en un problème équivalent de synthèse d’une loi de commande locale est proposée en se basant sur l’hypothèse des sous-systèmes identiques interconnectés en réseau. Le lien entre les propriétés locales et globales est établi grâce aux approches d’Automatique avancée telles que les approches entrée-sortie et la dissipativité. Ce choix de méthode permet non seulement de réduire considérablement la complexité du problème initial mais aussi de ramener le problème de synthèse à une forme proche des méthodes de conception locale utilisées en Microélectronique, ce qui garantit une continuité logique de leur évolution. Ensuite la méthode proposée est combinée avec la commande H∞ et l’optimisation sous contraintes LMIs conduisant au développement d’algorithmes efficaces de résolution du problème posé. Elles sont à la fois particulièrement bien adaptées à l’application considérée, c’est-à-dire à la synchronisation d’un réseau de PLLs, et sont facilement généralisables aux autres types de problèmes de commande de systèmes de grande dimension. Le premier aspect permet une intégration naturelle et aisée de la méthode dans le flux de conception existant en Microélectronique, très riche et mature à ce jour, alors que le deuxième offre une solution à d’autres problèmes de commande de systèmes interconnectés en réseau, un champ d’application aujourd’hui en plein essor. / The classical clock distribution trees used in the synchronous microprocessor systems in nowadays have several drawbacks such as skew, jitter, frequency limitation, perturbation and disturbance behavioral impact independently of their origin, etc.. These factors, critical for the modern microprocessors, motivate the research of an alternative architecture of the clock generation and distribution system. An example of such alternative architectures is the network of coupled PLLs where the PLLs are geographically distributed on the chip and produce the local clock signals. These local clock signals are then synchronized, in real time, by an exchange of information between the PLLs and by local feedback corrections realized by its controllers. Distributed PLLs network allows overcoming the mentioned limitation encountered for the classical clock distribution system. However, the active nature of this network requires going beyond the scope of usual stand-alone PLL design methods. Indeed, the dynamical aspects of the feedback loops and the transformations of the signal inside this complex system make the design problem extremely difficult to solve. The main issue consists in ensuring certain properties of the global network as well as local properties of each subsystem PLL because those properties may change drastically from independent stand-alone PLL designed with standard tools and methods. Indeed, depending on the network topology, the local properties and global dynamical behavior are not necessarily ensured for the overall network. The main contribution of this PhD thesis is the development of a control law design method for each subsystem (such as PLL) ensuring the desired behavior of the global network. A method for transforming the global design problem to an equivalent local control law design problem is proposed. It is based on the assumption that all subsystems are identical. The relation between the local and global properties is established using advanced Control System Theory tools such as input-output and dissipativity principle. This principle decreases significantly the problem complexity by transforming the design problem into a form that is closed to the design of a stand-alone closed loop system. The proposed method is combined with robust H∞ control and LMI optimization that can be solved efficiently with appropriate algorithms that are well suited for the considered application i.e. the PLLs network synchronization. The proposed approach can be easily generalized to other types of networked system to be controlled.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

[EN] Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals. The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one. As a first step, a general study of DAQ arquitectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards. Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the particular case of two detectors. This DAQ is finally installed at the experimental setup, where their synchronization properties and resolution as a PET system are characterized and its performance is verified to have improved with respect to the previous system. / [ES] La Tomografía por Emisión de Positrones (PET) es una modalidad de imagen médica nuclear no invasiva que permite observar la distribución de sustancias metabólicas en el interior del cuerpo de un paciente tras marcarlas con isótopos radioactivos y disponer después un escáner anular a su alrededor para detectar su desintegración. Las principales aplicaciones de esta técnica son la detección y seguimiento de tumores en pacientes con cáncer y los estudios metabólicos en animales pequeños. El grupo de investigación Electronic Design for Nuclear Applications (EDNA) del Instituto de Instrumentación para Imagen Molecular (I3M) ha estado involucrado en el estudio de sistemas PET de alto rendimiento y mantiene un pequeño setup experimental con dos módulos detectores. La presente tesis se enmarca dentro de la necesidad de desarrollar un nuevo sistema de adquisición de datos (DAQ) para dicho setup que corrija los inconvenientes del ya existente. En particular, el objetivo es definir una arquitectura de DAQ que sea totalmente escalable, modular, y que asegure la movilidad y la posibilidad de reutilización de sus componentes, de manera que admita cualquier ampliación o alteración del setup y pueda exportarse directamente a los de otros grupos o experimentos. Al mismo tiempo, se desea que dicha arquitectura no limite artificialmente el rendimiento del sistema sino que sea compatible con las mejores resoluciones disponibles en la actualidad, y en particular que sus prestaciones superen a las del DAQ instalado previamente. En primer lugar, se lleva a cabo un estudio general de las arquitecturas de DAQ para setups experimentales para PET y otras aplicaciones de física de altas energías. Por un lado, se determina que las características deseadas implican la digitalización temprana de las señales del detector, la comunicación exclusivamente digital entre módulos, y la ausencia de trigger centralizado. Por otro lado, se hace patente la necesidad de un esquema de sincronización distribuida muy preciso entre módulos, con errores del orden de 100 ps, que opere directamente sobre los enlaces de datos. Un estudio de los métodos ya existentes revela sus graves limitaciones a la hora de alcanzar esas precisiones. Con el fin de paliarlos, se lleva a cabo un análisis teórico de la situación y se propone un nuevo algoritmo de sincronización que es capaz de alcanzar la resolución deseada y elimina las restricciones de alineamiento de reloj impuestas por casi todos los esquemas usuales. Dado que la medida de desfase entre relojes juega un papel crucial en el algoritmo propuesto, se definen y analizan extensiones a los métodos ya existentes que suponen una mejora sustancial. El esquema de sincronismo propuesto se valida utilizando placas de evaluación comerciales. Partiendo del método de sincronismo propuesto, se define una arquitectura de DAQ para PET compuesta de dos tipos de módulos (adquisición y concentración) cuya replicación permite construir un sistema jerárquico de tamaño arbitrario, y se diseñan e implementan placas de circuito basadas en dicha arquitectura para el caso particular de dos detectores. El DAQ así construído se instala finalmente en el setup experimental, donde se caracterizan tanto sus propiedades de sincronización como su resolución como sistema PET y se comprueba que sus prestaciones son superiores a las del sistema previo. / [CA] La Tomografia per Emissió de Positrons (PET) és una modalitat d'imatge mèdica nuclear no invasiva que permet observar la distribució de substàncies metabòliques a l'interior del cos d'un pacient després d'haver-les marcat amb isòtops radioactius disposant un escàner anular al seu voltant per a detectar la seua desintegració. Aquesta tècnica troba les seues principals aplicacions a la detecció i seguiment de tumors a pacients amb càncer i als estudis metabòlics en animals petits. El grup d'investigació Electronic Design for Nuclear Applications (EDNA) de l'Instituto de Instrumentación para Imagen Molecular (I3M) ha estat involucrat en l'estudi de sistemes PET d'alt rendiment i manté un petit setup experimental amb dos mòduls detectors. Aquesta tesi neix de la necessitat de desenvolupar un nou sistema d'adquisició de dades (DAQ) per al setup esmentat que corregisca els inconvenients de l'anterior. En particular, l'objectiu és definir una arquitectura de DAQ que sigui totalment escalable, modular, i que asseguri la mobilitat i la possibilitat de reutilització dels seus components, de tal manera que admeta qualsevol ampliació o alteració del setup i pugui exportar-se directament a aquells d'altres grups o experiments. Al mateix temps, es desitja que aquesta arquitectura no introduisca límits artificials al rendiment del sistema sinó que sigui compatible amb les millors resolucions disponibles a l'actualitat, i en particular que les seues prestacions siguin superiors a les del DAQ instal.lat amb anterioritat. En primer lloc, es porta a terme un estudi general de les arquitectures de DAQ per a setups experimentals per a PET i altres aplicacions de física d'altes energies. Per una banda, s'arriba a la conclusió que les característiques desitjades impliquen la digitalització dels senyals del detector el més aviat possible, la comunicació exclusivament digital entre mòduls, i l'absència de trigger centralitzat. D'altra banda, es fa palesa la necessitat d'un mecanisme de sincronització distribuïda molt precís entre mòduls, amb errors de l'ordre de 100 ps, que treballi directament sobre els enllaços de dades. Un estudi dels mètodes ja existents revela les seues greus limitacions a l'hora d'assolir aquest nivell de precisió. Amb l'objectiu de pal.liar-les, es duu a terme una anàlisi teòrica de la situació i es proposa un nou algoritme de sincronització que és capaç d'obtindre la resolució desitjada i es desfà de les restriccions d'alineament de rellotges imposades per gairebé tots els esquemes usuals. Atès que la mesura del desfasament entre rellotges juga un paper cabdal a l'algoritme proposat, es defineixen i analitzen extensions als mètodes ja existents que suposen una millora substancial. L'esquema de sincronisme proposat es valida mitjançant plaques d'avaluació comercials. Prenent el mètode proposat com a punt de partida, es defineix una arquitectura de DAQ per a PET composta de dos tipus de mòduls (d'adquisició i de concentració) tals que la replicació d'aquests elements permet construir un sistema jeràrquic de mida arbitrària, i es dissenyen i implementen plaques de circuit basades en aquesta arquitectura per al cas particular de dos detectors. L'electrònica desenvolupada s'instal.la finalment al setup experimental, on es caracteritzen tant les seues propietats de sincronització com la seua resolució com a sistema PET i es comprova que les seues prestacions són superiors a les del sistema previ. / Aliaga Varea, RJ. (2016). Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63271 / TESIS / Premios Extraordinarios de tesis doctorales