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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
781

Bridging of SCSI to SATA and Implementationof a SATA Controller using Virtex-5 / Bryggning mellan SCSI och SATA samt implementering av en styrenhet för SATA på en Virtex-5

Landström, Erik January 2009 (has links)
Companies and authorities of today often handle large amount of data, not unusually with a restricted content which should be kept secret from outsiders. One way of accomplish this is to encrypt stored data in real time. For this a hardware solution is ideal since it can be independent, fast enough, and easily added to already existing systems. This report is a starting point to achieve this with two of the most common mass storage standards SATA and SCSI in focus. It is based on the task to develop a FPGA based SATA controller and investigate the possibility to ”speak” SCSI with SATA devices. The working process has involved theoretical studies, system design, test driven development using simulations and hardware tests and technical investigation. The thesis resulted in a SCSI-to-SATA translation investigation pointing out difficulties and presenting a translation model. A SATA host was also implemented in VHDL on a Virtex-5 FPGA that can execute a number of SATA commands on different devices. Simulations performed shows that the total latency reaches one μs/32 bits in the SATA host and that should not be much of a problem for most applications in a possible bridge solution.
782

Vibrationsbaserad maskinaktivitetssensor / Vibration based machine activity sensor

Bergquist, Albert January 2006 (has links)
I detta projekt undersöker vi om man kan bygga en maskinaktivitetssensor med hjälp av en enkretsdator som genom en accelerometer mäter en maskins vibrationer. Sensorn skall generera en statussignal. Accelerometern ger en mätbar signal baserad på maskinens vibrationer. Enkretsdatorn används för att sampla, transformera och analysera signalen och generera statusinformation. Med LabView kan vi spara, studera och analysera olika signaler och olika transformer. Vi studerar maskinvibrationer i LabView och beslutar att 5 kHz sampling räcker för att fånga intressanta vibrationer. Vi jämför transformers egenskaper och beräkningskrav och väljer Fouriertransform som analysmetod. Vi beräknar att en Atmel ARM SAM7S256 kan utföra uppgiften och implementerar interruptbaserad signalsampling, frekvensanalys och en beslutsrutin som resulterar i en utsignal med statusinformation. / In this project we examine the possibility to create a machine activity sensor by a one-chip computer that measures a machines vibrations through an accelerometer. The sensor shall generate a status signal. The accelerometer is used to give a measurable signal of a machines vibrations. The one-chip computer is used to sampel, transform and analyze this signal and generate a status signal. With LabView we can save, study and analyze different signals and their different transforms. By studying machine vibrations in LabView we decide that sampling at 5 kHz is sufficient. By comparing different transformations in regards to performance and calculation needs we choose Fast Fourier Transform as analyzing tool. We calculate that a ARM SAM7S256 can manage the task and implement an interrupt based sampling, frequency analysis and decision making routine which results in a status signal.
783

Evaluation of Image Warping Algorithms for Implementation in FPGA

Serguienko, Anton January 2008 (has links)
The target of this master thesis is to evaluate the Image Warping technique and propose a possible design for an implementation in FPGA. The Image Warping is widely used in the image processing for image correction and rectification. A DSP is a usual choice for implantation of the image processing algorithms, but to decrease a cost of the target system it was proposed to use an FPGA for implementation. In this work a different Image Warping methods was evaluated in terms of performance, produced image quality, complexity and design size. Also, considering that it is not only Image Warping algorithm which will be implemented on the target system, it was important to estimate a possible memory bandwidth used by the proposed design. The evaluation was done by implemented a C-model of the proposed design with a finite datapath to simulate hardware implementation as close as possible.
784

Cryptographic Key Masking During Run-Time

Andersson, Marcus January 2008 (has links)
Many of the products commercially available today contain some form of encrypted or hashed data. It can involve DRM protection, licenses and certificates, signatures or identification information. Regardless of what the data is intended for, it is protected for a reason and may be worth a great deal of money to the owner. There are numerous examples of products that have been subject to hacking in the form of simple memory attacks. If the keys are made all too easily extracted, the value of the protected data will soon be lost. The aim of the thesis work discussed in this report was to evaluate the vulnerabilities in mobile phones to this sort of attacks and to find possible security enhancements that can be applied. A method is proposed where masking will secure the cryptology keys while they reside in the memory. Different masks are developed and tested - The effects on performance are measured and the security is evaluated. The thesis work concludes that it is possible to implement masking on many of the security functions using keys and that the masks will increase security. The conclusion also states that the time consumption of the masking heavily depends on which mask that is used and that the masking could be applied in such a way that the level of masking can be varied.
785

Evaluation of a Floating Point Acoustic Echo Canceller Implementation

Dahlberg, Anders January 2007 (has links)
This master thesis consists of implementation and evaluation of an AEC, Acoustic Echo Canceller, algorithm in a floating-point architecture. The most important question this thesis will try to answer is to determine benefits or drawbacks of using a floating-point architecture, relative a fixed-point architecture, to do AEC. In a telephony system there is two common forms of echo, line echo and acoustic echo. Acoustic echo is introduced by sound emanating from a loudspeaker, e.g. in a handsfree or speakerphone, being picked up by a microphone and then sent back to the source. The problem with this feedback is that the far-end speaker will hear one, or multiple, time-delayed version(s) of her own speech. This time-delayed version of speech is usually perceived as both confusing and annoying unless removed by the use of AEC. In this master thesis the performance of a floating-point version of a normalized least-mean-square AEC algorithm was evaluated in an environment designed and implemented to approximate live telephony calls. An instruction-set simulator and assembler available at the initiation of this master thesis were extended to enable; zero-overhead loops, modular addressing, post-increment of registers and register-write forwarding. With these improvements a bit-true assembly version was implemented capable of real-time AEC requiring 15 million instructions per second. A solution using as few as eight mantissa bits, in an external format used when storing data in memory, was found to have an insignificant effect on the selected AEC implementation’s performance. Due to the relatively low memory requirement of the selected AEC algorithm, the use of a small external format has a minor effect on the required memory size. In total this indicates that the possible reduction of the memory requirement and related energy consumption, does not justify the added complexity and energy consumption of using a floating-point architecture for the selected algorithm. Use of a floating-point format can still be advantageous in speech-related signal processing when the introduced time delay by a subband, or a similar frequency domain, solution is unacceptable. Speech algorithms that have high memory use and small introduced delay requirements are a good candidate for a floating-point digital signal processor architecture.
786

Versionshantering för databaser

Löfling, Louise January 2008 (has links)
Moment Marketing är ett litet företag som arbetar med webbutveckling. För dem är det viktigt med versionshantering och de använder ett fåtal program som underlättar detta arbete. Idag saknar de dock möjligheten att kontrollera olika versioner av databaser. Tillsammans med Moment Marketing och de program som redan används av dem skapas i detta projekt ytterligare applikationer med mål att lösa detta problem. Först görs en undersökning över programmen Subversion, TortoiseSVN, Trac och MySQL för att se de möjligheter som finns att använda dem till att uppnå målet. Därefter skapas ytterligare applikationer som kompletterar dessa program. Det färdiga paketet innehåller program för att hantera strukturen i en lokal databas tillsammans med ett lokalt arbetsprojekt. Tillsammans med de redan tidigare befintliga programmen har ett system bildats som även hanterar databaser. Dessutom har ytterligare möjligheter till förbättrat arbete med databaser undersökts. / Moment Marketing is a small Company working with web development. Version control is an important part of their work and they already use a few programs to handle this. These programs cannot handle different database versions. In this project supplements will be created so that previously installed programs can be used for handling version control of databases. Before the programming begins a study of the programs Subversion, TortoiseSVN, Trac and MySQL will be made.
787

Standardisering av funktionsblock for PLC / Standardization of function blocks for PLC

Hultkrantz, Jörgen January 2009 (has links)
Automationscenter & Bråvalla Elteknik AB is a company that offers the market completed total solutions where the customer can operate and monitor their production from the terminal. In these total solutions they lack standard circuit which are developed by the company and which could manoeuvre/control/monitor controlled process objects. This report defines the work of developing the most common standard circuits.The report is initiated by a short theoretical part about PLC and the PLC system, with a connected terminal, which has been used. Thereafter, the turnout of the demands of specification is reported, after discussing with the supervisor in the course of the project. The report concludes with a disclosure of how the programming, the documentation and the testing have proceeded and a final discussion concerning the project and proposals on continuation.The result is a CD with the documentation of standard circuits and how they are implemented in a new project. One library file with the program code to all standard circuit. Program code and documentation for both demonstration and testing are also on the CD. This project represents a start of POS (Process Objektsstyrnings Standard) as the collection is called at Automationscenter. / Automationscenter & Bråvalla Elteknik AB är ett företag som erbjuder marknaden färdiga totallösningar där kunden kan manövrera och övervaka sin produktion från operatörspaneler. I denna totallösning saknar företaget egna framtagna ”typkretsar” som manövrerar/kontrollerar/övervakar styrda processobjekt. En typkrets skall ha en del som implementeras i PLC och en del som implementeras i operatörspanelen.Denna rapport redogör för hur några av de vanligaste ”typkretsarna” tas fram.Rapporten inleds med en kort teoridel om PLC och det PLC‐system med tillhörande operatörspanel som använts. Därefter redogörs hur typkretsarnas kravspecifikation blev efter att ha diskuterat med handledaren under arbetets gång. Rapporten avslutas med en redovisning för hur programmeringen, dokumentationen och testningen gått till och en avslutande diskussion om arbetet och förslag på fortsättning.Resultatet blev en CD‐skiva med dokumentation om typkretsarna och hur de implementeras i ett nytt projekt: en biblioteksfil med programkoden till alla typkretsar. Programkod och dokumentation för både visning och testning finns också med på skivan. Ex‐jobbet utgör en början på POS Process Objektsstyrnings Standard som samlingen heter på Automationscenter & Bråvalla Elteknik AB.
788

Utvärdering och vidareutveckling av STAPL för användning inom inbäddad Boundary-Scan-baserad test

Holmqvist, Johan January 2007 (has links)
Antalet kretskort som monteras i multikortssystem, till exempel telekommunikationssystem, ökar ständigt. Samtidigt som ytmonteringstekniken och packningstekniken blir allt bättre utvecklas även tillverkningsmetoderna för olika integrerade komponenter, vilket medför att varje kretskort rymmer allt fler integrerade komponenter. Detta gör att testning av integrerade komponenter och multikortsystem blir alltmer komplex. En förutsättning för att kunna genomföra effektiv testning är standarder. Standarder över hur testning ska genomföras medför att en komponent som uppfyller kraven från en standard är direkt utbytbar mot en komponent från en annan tillverkare som uppfyller kraven från samma standard. En god standard bidrar även till att utvecklingen drivs åt samma håll istället för att varje tillverkare har sin egen lösning och ett eget gränssnitt, vilket dessutom leder till att ett antal olika gränssnittsomvandlare behövs för att koppla samman olika komponenter. Internal Joint Test Action Group (IJTAG) arbetar just nu med att ta fram en standard för inbäddade testinstrument på mikronivå. De inbäddade instrumenten kan stödja karaktärisering av komponenter likväl som strukturell och funktionell testning. På makronivå arbetar System Joint Test Action Group (SJTAG) med att ta fram en standard för testadministration. Den främsta uppgiften är att koppla samman IJTAG-standarden med systemtestadministrationen. Behovet av ett kommunikationsprotokoll mellan dessa båda är stort. I denna rapport utvärderas Standard Test and Programming Language (STAPL) i syfte att se hur det passar som länk mellan testmanager och inbäddade instrument. Vidare identifieras ett antal brister i STAPL och ett förslag på en vidareutveckling av språket tas fram. Denna vidareutveckling syftar till att göra språket mer dynamiskt och passande för inbäddad testning via Boundary-Scan-protokollet. Slutligen implementeras en demonstrator som består av mjukvara som exekveras på en PC och en Field Programmable Gate Array (FPGA) som tjänar som testobjekt.
789

A Modular API for Intelligent Virtual Agents

Franzén, Daniel January 2007 (has links)
This report proposes a modular Application Programmer's Interface (API) for handling the mental layer of intelligent virtual agents for a wide range of application types, with the aim of reducing the work required to program a completely new AI engine, and describes its implementation. One of the key elements and major difficulties in its design is the need to make it general enough to suit most types of applications, while preserving its usefulness and keeping it both efficient and reliable. A sample application interfacing with the API is created to demonstrate its capabilities, various AI algorithms are looked into and their respective suitability for the API is evaluated, and some techniques are implemented as modules in the API.
790

Code profiling as a design tool for application specific instruction sets

Skoglund, Björn January 2007 (has links)
As the embedded devices has become more and more generalized and as their product cycles keeps shrinking the field has opened up for the Application Specific Instruction set Processor. A mix between the classic generalized microcontroller and the specialized ASIC the ASIP keeps a set of general processing instructions for executing embedded software but combines that with a set of heavily specialized instructions for speeding up the data intense application core algorithms. One important aspect of the ASIP design flow research is cutting design time and cost. One way of that is automation of the instruction set design. In order to do so a process is needed where the algorithm to be ASIPed is analyzed and critical operations are found and exposed so that they can be implemented in special hardware. This process is called profiling. This thesis describes an implementation of a fine grained source code profiler for use in an ASIP design flow. The profiler software is based on a static-dynamic workflow where data is assembled from both static analysis and dynamic execution of the program and then analyzed together in an specially made analysis software.

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