This projects aims to develop design automation in product development. Design automation causes increase in producibility and decrease in product cost and manufacturing lead time. The study at hand is proposed to provide a new method and to introduce procedure to the design of wiring pattern for a car seat heater for Kongsberg Automotive, KA. KA is a Norwegian company and a global provider of engineering, design, and manufacture for seat comfort, driver and motion control systems, fluid assemblies, and industrial driver interface products. The method that currently is used in the company to create a wiring pattern is neither sufficient enough nor automated. In order to design the wiring pattern, at first procedure is handled by the designer. Secondly, car seat heater 2D layout is imported and then, the dimensions of the elements are defined as constraints. Then VBA codes are opened and the program is run. The result will be a wiring pattern in different 2D layouts. To make the design process easier, we have modeled five different layouts; wiring pattern of one element, two elements, three elements, five elements (with two back sides) and one element trapezoidal 2D layout. The algorithm written in VBA (Visual basic for application) creates the pattern according to the dimensions of the elements which are used as inputs to define constrained parameters. The created macros are simple to use and easy to modify, independent from the programming knowledge. The user is only responsible with parameter input and running the program. The solution gives wiring pattern for a car seat heater.

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed. / text

The main contribution of this thesis consists on the proposition and development a Model-driven Engineering (MDE) framework, in tandem with a component-based approach, for facilitating the design and implementation of Dynamic Partially Reconfigurable (DPR) Systems-on-Chip. The proposed methodology has been constructed around the Metadata-based Composition Framework paradigm, and based on common standards such as UML MARTE and the IEEE IP-XACT standard, an XML representation used for storing metadata about the IPs to be reused and of the platforms to be obtained at high-levels of abstraction. In fact, a componentizing process enables us to reuse the IP blocks, in UML MARTE, by wrapping them with PLB (static IPs) and proprietary (DPR blocks) interfaces. This is attained by reflecting the associated IP metadata to IP-XACT descriptions, and then to UML MARTE templates (IP reuse). Subsequently, these IP templates are used for composing a DPR model that can be exploited to create a Xilinx Platform Studio FPGA-design, through model transformations. The IP reflection and system generation chains were developed using Sodius MDWorkbench, an MDE tool conceived for the creation and manipulation of models and their meta-models, as well as the definition and execution of the associated transformation rules.

Intensive competition on the global market puts great pressure on manufacturing companies to develop and produce products that meet requirements from customers and investors. One key factor in meeting these requirements is the efficiency of the product development and the production preparation processes. Design automation is a powerful tool to increase efficiency in these two processes. The benefits of automating the manufacturability analysis process, a part of the production preparation process, are shortened lead-time, improved product performance, quality assurance, and, ultimately, decreased costs. Further, automation is beneficial as it increases the ability to adapt products to new product specifications with production preparations done in a few or in a single step. During the automation process, knowledge about the manufacturability analysis process is collected and stored in central systems, thus allowing full control over the design of production equipments. Topics addressed in this thesis include the flexibility of design automation systems, knowledge-bases containing alternative design rules, the automation of the finite element analysis process, manufacturability analysis over several productions steps, and the determination of production limits by looping the automated manufacturability analysis process. These topics are discussed in connection with the rotary draw bending of aluminum profiles. It is concluded that the concept of design automation can be applied to the manufacturability analysis process at different levels of automation depending on the characteristics of the implemented knowledge. The concept of object orientation should be adapted when implementing a knowledge-base and when developing the geometrical representations of the products. This makes a design automation system flexible enough to edit underlying knowledge and to extend the targeted design space. It is possible to automate the process of setting up, running, and interpreting finite element analyses to a great extent, enabling the design automation system to evaluate its own design proposals. It is also possible to enable such systems to consider sequences of manufacturing steps and loop them to develop decision support guiding engineers early in the design process, saving time and money while still assuring high product quality.

Saab Aeronautics’ section Overall Design and Survivability develops early aircraft concepts and utilizes Computer Aided Design (CAD) to ensure the feasibility of principal- and critical characteristics. Saab has over the years developed several start models of aircrafts in CAD from pre-defined aircraft configurations, which are to some extent non-generic. When new configurations are to be explored, manual- and repetitive work is required if the new configuration cannot be attained solely through parametric modifications of a start model. The complexity of these CAD models also demands great knowledge of how aircraft components interact with each other to ensure compatibility. The project covered in this thesis was thus carried out to develop a more effective way for Saab to create and explore a larger design space. This by creating a framework that consists of a product configurator coupled with a library of generic CAD models. The product configurator that was created is the Saab Tradespace Analyzer & Reconfigurator (STAR), which takes compatibility relationships into consideration to facilitate concept selection. The STAR also provides a dynamic design space calculation to indicate how close the user is to a final concept selection. Two generic CAD models were created, a fuselage model and an air inlet model. A skeleton model was also created in order to reduce model dependencies and to control the main geometry of the aircraft product. In addition to these, an already existing wing model was implemented to form the library of generic CAD models. The framework coupling the STAR with the CAD library utilizes design automation to allow automatic CAD model generation of a concept that has been selected within the STAR. It was concluded through extrapolation that the created framework would allow Saab to create and explore a larger design space in a more effective way than what is done today, provided the library of CAD models were to contain the same number of components as today’s start models.

En projekteringsprocess av en konstruktion kan ofta delas in i två delar, dimensionering ochprojektering. Dimensioneringen utförs enligt för konstruktionen gällande normkrav ochprojekteringen följer sina egna normer samt den dimensionering som är utförd.Även om 2D-projektering fortfarande är vanligt förekommande i projekteringen har BIMmodelleringblivit allt vanligare och värdet av att lagra information i en modell ses alltmersom en nytta i ett projekt.BIM-modelleringen bygger på parameterstyrning av objekt och egentligen finns inga gränserför vilka parametrar som ska ingå i ett objekt.En av de senaste utvecklingarna i projekteringsprocessen är den visuella programmeringensom ger användare möjlighet att styra parametrar till en BIM-modell med hjälp av ett visuelltskript kopplat till BIM-modelleringsverktyget.Det här arbetet syftar på att visa hur ett skript kan driva modelleringen med hjälp avprojektspecifika indata genom att dimensionering av objekt integreras i programmeringen.Med hjälp av programmeringen kan även dimensioneringen redovisas i en annanprogramvara.Resultatet visar att det är fullt möjligt att skapa en modell med hjälp av objektspecifika indataoch att parametrar kan styras med integrerad dimensionering i ett skript skapat med visuellprogrammering. / A design process of a construction can often be divided into two parts, structural design anddrawing. The structural design is made with current standard requirements for theconstruction while the drawing has its own standard requirements along with the results fromthe dimensioning to follow.Even if 2D- drawing still is common in design of a project, BIM-modelling has become morefrequently used and the value of storing information in a model is see more and more as abenefit in a project.The BIM-modelling is based on parametric design of objects and there are actually no limitsto which parameters that should be a part of an object.One of the most recent developments in the design process is the visual programming whichgives users the opportunity to guide parameters in a BIM-model through a visual scriptconnected to the BIM-modelling tool.This work is aiming to show how a script can push the modelling by using project specificinput and perform structural design of load bearing members integrated in the script. With theuse of the script, results can also be verified in another software.Result is showing that it is possible to create a structurally designed model by using only afew object specific inputs and that parameters can be controlled in a script made with visualprogramming.

As the world is evolving very fast with the developments of new technologies and softwares in design and manufacturing, business organizations and manufacturing industries will always be adapting to the new technologies and softwares for increasing the cost and time efficiency in the development of products. So, this thesis focuses on a comparative study between two Dassault Systems softwares in which, one is mostly used CAD software by industries for a long time, and one is the latest developments in the CAD softwares with satisfying business requirements. For this comparison study, the two methods called design automation and robot simulation are used in the development of modular fixtures platforms used in automobile manufacturing industries. In the first method, the design and assembly of modular fixtures platform are done which holds the automotive car sheet pillars together. With a single mouse click, the complete design and assembly of the modular fixtures can be done using automation. In the second method, the spot-welding manufacturing operation is done to join the car sheet pillars together to produce the B-pillar of the Body in white (BIW) for the automobile, with the help of a welding gun connected to ABB robot arm, using automation in robot simulation. This work takes place in CATIA V5 and 3D Experience, and the final results obtained in both the software are compared and discussed in the results part of this report. Automation in CAD has been one of the advanced developments that happened in the 21st century through which most of the engineering knowledge and intent can be captured and reutilized. CATIA V5 & 3D Experience Automation is done using two programming languages called VB (Visual Basics) and VB.net.

In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs). Exploring and developing new technologies just like CMOS, require tackling two main challenges – first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology. This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping. The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS. Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads. Overall, this thesis lays a strong foundation for the two main objectives – design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract List of Figures List of Tables 1 Introduction 1.1 What are emerging reconfigurable nanotechnologies? 1.2 Why does this technology look so promising? 1.3 Electronics Design Automation 1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies 1.4.1 Abstracting ambipolarity in logic gate designs 1.4.2 Enabling electronic design automation for RFETs 1.4.3 Enhanced functionality: a suitable fit for hardware security applications 1.5 Research questions 1.6 Entire RFET-centric EDA Flow 1.7 Key Contributions and Thesis Organization 2 Preliminaries 2.1 Reconfigurable Nanotechnology 2.1.1 1D devices 2.1.2 2D devices 2.1.3 Factors favoring circuit-flexibility 2.2 Feasibility aspects of RFET technology 2.3 Logic Synthesis Preliminaries 2.3.1 Circuit Model 2.3.2 Boolean Algebra 2.3.3 Monotone Function and the property of Unateness 2.3.4 Logic Representations 3 Exploring Circuit Design Topologies for RFETs 3.1 Contributions 3.2 Organization 3.3 Related Works 3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates 3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs 3.4.2 Estimation of gate delay using the logical effort theory 3.5 Invariable design of Inverters 3.6 Sequential Circuits 3.6.1 Dual edge-triggered TSPC-based D-flip flop 3.6.2 Exploiting RFET’s ambipolarity for metastability 3.7 Evaluations 3.7.1 Evaluation of combinational logic gates 3.7.2 Novel design of 1-bit ALU 3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design 3.8 Concluding remarks 4 Standard Cells and Technology Mapping 4.1 Contributions 4.2 Organization 4.3 Related Work 4.4 Standard cells based on RFETs 4.4.1 Interchangeable Pull-Up and Pull-Down Networks 4.4.2 Reconfigurable Truth-Table 4.5 Distilling standard cells 4.6 HOF-based Technology Mapping Flow for RFETs-based circuits 4.6.1 Area adjustments through inverter sharings 4.6.2 Technology Mapping Flow 4.6.3 Realizing Parameters For The Generic Library 4.6.4 Defining RFETs-based Genlib for HOF-based mapping 4.7 Experiments 4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite 4.7.2 Experiment 2A: HOF-based mapping . 4.7.3 Experiment 2B: Using the distilled standard-cells during mapping 4.8 Concluding Remarks 5 Logic Synthesis with XOR-Majority Graphs 5.1 Contributions 5.2 Organization 5.3 Motivation 5.4 Background and Preliminaries 5.4.1 Terminologies 5.4.2 Self-duality in NPN classes 5.4.3 Majority logic synthesis 5.4.4 Earlier work on XMG 5.4.5 Classification of Boolean functions 5.5 Preserving Self-Duality 5.5.1 During logic synthesis 5.5.2 During versatile technology mapping 5.6 Advanced Logic synthesis techniques 5.6.1 XMG resubstitution 5.6.2 Exact XMG rewriting 5.7 Logic representation-agnostic Mapping 5.7.1 Versatile Mapper 5.7.2 Support of supergates 5.8 Creating Self-dual Benchmarks 5.9 Experiments 5.9.1 XMG-based Flow 5.9.2 Experimental Setup 5.9.3 Synthetic self-dual benchmarks 5.9.4 Cryptographic benchmark suite 5.10 Concluding remarks and future research directions 6 Physical synthesis flow and liberty generation 6.1 Contributions 6.2 Organization 6.3 Background and Related Work 6.3.1 Related Works 6.3.2 Motivation 6.4 Silicon Nanowire Reconfigurable Transistors 6.5 Layouts for Logic Gates 6.5.1 Layouts for Static Functional Logic Gates 6.5.2 Layout for Reconfigurable Logic Gate 6.6 Table Model for Silicon Nanowire RFETs 6.7 Exploring Approaches for Physical Synthesis 6.7.1 Using the Standard Place & Route Flow 6.7.2 Open-source Flow 6.7.3 Concept of Driver Cells 6.7.4 Native Approach 6.7.5 Island-based Approach 6.7.6 Utilization Factor 6.7.7 Placement of the Island on the Chip 6.8 Experiments 6.8.1 Preliminary comparison with CMOS technology 6.8.2 Evaluating different physical synthesis approaches 6.9 Results and discussions 6.9.1 Parameters Which Affect The Area 6.9.2 Use of Germanium Nanowires Channels 6.10 Concluding Remarks 7 Polymporphic Primitives for Hardware Security 7.1 Contributions 7.2 Organization 7.3 The Shift To Explore Emerging Technologies For Security 7.4 Background 7.4.1 IP protection schemes 7.4.2 Preliminaries 7.5 Security Promises 7.5.1 RFETs for logic locking (transistor-level locking) 7.5.2 RFETs for split manufacturing 7.6 Security Vulnerabilities 7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter 7.6.2 Circuit evaluation on sub-circuits 7.6.3 Reliability concerns: A consequence of short-circuit scenario 7.6.4 Implication of the proposed security vulnerability 7.7 Analytical Evaluation 7.7.1 Investigating the security promises 7.7.2 Investigating the security vulnerabilities 7.8 Concluding remarks and future research directions 8 Conclusion 8.1 Concluding Remarks 8.2 Directions for Future Work Appendices A Distilling standard-cells B RFETs-based Genlib C Layout Extraction File (.lef) for Silicon Nanowire-based RFET D Liberty (.lib) file for Silicon Nanowire-based RFETs

En biologie synthétique, il existe plusieurs manières d’adresser les problèmes soulevés dans plusieurs domaines comme la thérapeutique, les biofuels, les biomatériaux ou encore les biocapteurs. Nous avons choisi de nous concentrer sur l’une d’entre elles : les réseaux de régulation génétique (RRG). Un constat peut être fait : la diversité des problèmes résolus grâce aux RRGs est bridée par la complexité de ces RRGs, qui a atteint une limite. Quelles solutions s’offrent aux biologistes, pour repousser cette limite et continuer d’augmenter la complexité de leur système ? Cette thèse a pour but de fournir aux biologistes les outils nécessaires à la conception et à la simulation de RRGs complexes. Un examen de l’état de l’art en la matière nous a mené à adapter les outils de la micro-électronique à la biologie ainsi qu’à créer un algorithme de programmation génétique pour la conception des RRGs. D’une part, nous avons élaboré les modèles Verilog A de différents systèmes biologiques (passe-bande, proie-prédateur, repressilator, XOR) ainsi que de la diffusion spatiotemporelle d’une molécule. Ces modèles fonctionnent très bien avec plusieurs simulateurs électroniques (Spectre et NgSpice). D’autre part, les premières marches vers l’automatisation de la conception de RRGs ont été gravies. En effet, nous avons développé un algorithme capable d’optimiser les paramètres d’un RRG pour remplir un cahier des charges donné. De plus, la programmation génétique a été utilisée pour optimiser non seulement les paramètres d’un RRG mais aussi sa topologie. Ces outils ont su prouver leur utilité en apportant des réponses pertinentes à des problèmes soulevés lors du développement de systèmes biologiques. Ce travail a permis de montrer que notre approche, à savoir adapter les outils de la micro-électronique et utiliser des algorithmes de programmation génétique, est valide dans le contexte de la biologie synthétique. L’assistance que notre environnement de développement fournit au biologiste devrait encourager l’émergence de systèmes plus complexes. / In synthetic biology, Gene Regulatory Networks (GRN) are one of the main ways to create new biological functions to solve problems in various areas (therapeutics, biofuels, biomaterials, biosensing). However, the complexity of the designed networks has reached a limit, thereby restraining the variety of problems they can address. How can biologists overcome this limit and further increase the complexity of their systems? The goal of this thesis is to provide the biologists with tools to assist them in the design and simulation of complex GRNs. To this aim, the current state of the art was examined and it was decided to adapt tools from the micro-electronic field to biology, as well as to create a Genetic Programming algorithm for GRN design. On the one hand, models of diffusion and of other various systems (band-pass, prey-predator, repressilator, XOR) were created and written in Verilog A. They are already implemented and well-functioning on the Spectre solver as well as a free solver, namely NgSpice. On the other hand, the first steps of automatic GRN design were achieved. Indeed, an algorithm able to optimize the parameters of a given GRN according to a specification was developed. Moreover, Genetic Programming was applied to GRN design, allowing the optimization of both the topology and the parameters of a GRN. These tools proved their usefulness for the biologists’ community by efficiently answering relevant biological questions arising in the development of a system. With this work, we were able to show that adapting microelectronics and Genetic Programming tools to biology is doable and useful. By assisting design and simulation, such tools should promote the emergence of more complex systems.

Sie entwickeln Entwurfssysteme für elektronische Baugruppen? Dann gehören für Sie die mit der Pinzuordnung verbundenen Optimierungskriterien - die Verdrahtbarkeit im Elektronikentwurf - zum Berufsalltag. Um die Verdrahtbarkeit unter verschiedenen Gesichtspunkten zu verbessern, werden in diesem Buch neu entwickelte Algorithmen vorgestellt. Sie ermöglichen erstmals die automatisierte Pinzuordnung für eine große Anzahl von Bauelementen in hochkomplexen Schaltungen. Alle Aspekte müssen in kürzester Zeit exakt erfasst, eingeschätzt und im Entwurfsprozess zu einem optimalen Ergebnis geführt werden. Die beschriebenen Methoden reduzieren den Entwicklungsaufwand für elektronische Systeme auf ein Minimum und ermöglichen intelligente Lösungen auf der Höhe der Zeit. Die vorliegende Arbeit behandelt die Optimierung der Pinzuordnung und die dafür notwendige Verdrahtbarkeitsvorhersage im hierarchischen Layoutentwurf. Dabei werden bekannte Methoden der Verdrahtbarkeitsvorhersage aus allen Schritten des Layoutentwurfs zusammengetragen, gegenübergestellt und auf ihre Eignung für die Pinzuordnung untersucht. Dies führt schließlich zur Entwicklung einer Vorhersagemethode, die speziell an die Anforderungen der Pinzuordnung angepasst ist. Die Pinzuordnung komplexer elektronischer Geräte ist bisher ein vorwiegend manueller Prozess. Es existieren also bereits Erfahrungen, welche jedoch weder formalisiert noch allgemein verfügbar sind. In den vorliegenden Untersuchungen werden Methoden der Pinzuordnung algorithmisch formuliert und damit einer Automatisierung zugeführt. Besondere Merkmale der Algorithmen sind ihre Einsetzbarkeit bereits während der Planung des Layouts, ihre Eignung für den hierarchisch gegliederten Layoutentwurf sowie ihre Fähigkeit, die Randbedingungen differenzieller Paare zu berücksichtigen. Die beiden untersuchten Aspekte der Pinzuordnung, Verdrahtbarkeitsvorhersage und Zuordnungsalgorithmen, werden schließlich zusammengeführt, indem die neue entwickelte Verdrahtbarkeitsbewertung zum Vergleichen und Auswählen der formulierten Zuordnungsalgorithmen zum Einsatz kommt. / This work deals with the optimization of pin assignments for which an accurate routability prediction is a prerequisite. Therefore, this contribution introduces methods for routability prediction. The optimization of pin assignments, for which these methods are needed, is done after initial placement and before routing. Known methods of routability prediction are compiled, compared, and analyzed for their usability as part of the pin assignment step. These investigations lead to the development of a routability prediction method, which is adapted to the specific requirements of pin assignment. So far pin assignment of complex electronic devices has been a predominantly manual process. Hence, practical experience exists, yet, it had not been transferred to an algorithmic formulation. This contribution develops pin assignment methods in order to automate and improve pin assignment. Distinctive characteristics of the thereby developed algorithms are their usability during layout planning, their capability to integrate into a hierarchical design flow, and the consideration of differential pairs. Both aspects, routability prediction and assignment algorithms, are finally brought together by using the newly developed routability prediction to evaluate and select the assignment algorithms.