Made available in DSpace on 2014-06-11T19:29:39Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-08-21Bitstream added on 2014-06-13T20:19:44Z : No. of bitstreams: 1 costaneto_a_me_sjrp.pdf: 316929 bytes, checksum: 812a1d9aaa7c2c0a64b9a5ae34eed517 (MD5) / O ensino é de vital importância para a evolução de uma sociedade. Metodologias e ferramentas de ensino visam otimizar e facilitar o aprendizado de forma que o processo de aprendizagem seja eficiente. Descreve-se nesta dissertação um ambiente de apoio ao ensino – chamado Classroom – com ênfase na Teoria das Inteligências Múltiplas cujo objetivo é fornecer ferramentas e guias para a criação de aulas virtuais, facilitando a composição e exposição de complementos para aulas presenciais. Além do ambiente e suas ferramentas, descreve-se também os raciocínios que nortearam a criação de um curso complementar de Sistemas Digitais para demonstração do uso do ambiente, tanto pelo professor que o criou quanto pelos alunos que o estudaram e avaliaram. Em seguida, são relatadas as formas de avaliação do ambiente, bem como os resultados obtidos. Por fim, conclui-se a dissertação com indicações dos pontos positivos que foram identificados com os resultados das avaliações e de melhorias que podem ser realizadas em extensões do ambiente Classroom. / Teaching has a vital importance to the evolution of a society. Teaching methodologies and tools aim to optimize and facilitate the learning process so that it becomes more efficient. This dissertation describes a teaching support environment – named Classroom – based on the Theory of Multiple Intelligences whose goal is to provide tools and guides to the creation of virtual classes, facilitating the composition of and exposure to material complimentary to that presented in attendance classes. Besides the environment and its tools, it is also described the reasoning behind the creation of a complementary Digital Systems course to demonstrate the use of the environment by the professor and the students that tested it. Afterwards, the process to evaluate the environment is presented, as well as the obtained results. In the end, the dissertation is concluded with indication of the positive and negative points that were identified by analyses of the evaluations results. Improvements are also proposed so that the Classroom environment may be extended.

Made available in DSpace on 2014-06-11T19:29:40Z (GMT). No. of bitstreams: 0 Previous issue date: 2012-12-13Bitstream added on 2014-06-13T20:19:47Z : No. of bitstreams: 1 mertes_jg_me_sjrp.pdf: 1925204 bytes, checksum: 46490bb6ae153565ad970cc3d025ddfc (MD5) / Este trabalho descreve um sistema para o processamento de imagens digitais coloridas. Este sistema possui um conjunto de filtros, o qual aliado a um controlador pode ser configurado pelo usuário através de um arquivo de configuração, buscando a melhor adequação do sistema às imagens a serem tratadas. O conjunto de filtros é composto por filtros que desempenham as tarefas de suavização, deteção de borda, equalização de histogramas, normalização de cores e normalização de luminância. O sistema foi descrito utilizando a linguagem de descrição de hardware System Verilog e implementado em um FPGA. Devido à sua característica reconfigurável, este sistema mostrou-se capaz de processar diversos tipos de imagens coloridas, ajustando-se facilmente às mais diferentes aplicações / This work describes a colored digital images processing system. This system has a set of filters, which in junction with a controller can be configured by the user through a setup file, in order to adapt the system to the images to be treated.This set is composed by several filters that perform tasks such as smoothing, edge detection, histogram equalization, color normalization and luminance normalization. The system was described using hardware description language (System Verilog), and implemented in an FPGA. Due to its reconfigurable caracteristic, this system showed capable of processing several types of colored images, easily fitting to a broad set of applications

Orientador: Norian Marranghello / Banca: Furio Damiani / Banca: Alexandre C. Rodrigues da Silva / Resumo: Este trabalho descreve um sistema para o processamento de imagens digitais coloridas. Este sistema possui um conjunto de filtros, o qual aliado a um controlador pode ser configurado pelo usuário através de um arquivo de configuração, buscando a melhor adequação do sistema às imagens a serem tratadas. O conjunto de filtros é composto por filtros que desempenham as tarefas de suavização, deteção de borda, equalização de histogramas, normalização de cores e normalização de luminância. O sistema foi descrito utilizando a linguagem de descrição de hardware System Verilog e implementado em um FPGA. Devido à sua característica reconfigurável, este sistema mostrou-se capaz de processar diversos tipos de imagens coloridas, ajustando-se facilmente às mais diferentes aplicações / Abstract: This work describes a colored digital images processing system. This system has a set of filters, which in junction with a controller can be configured by the user through a setup file, in order to adapt the system to the images to be treated.This set is composed by several filters that perform tasks such as smoothing, edge detection, histogram equalization, color normalization and luminance normalization. The system was described using hardware description language (System Verilog), and implemented in an FPGA. Due to its reconfigurable caracteristic, this system showed capable of processing several types of colored images, easily fitting to a broad set of applications / Mestre

Orientadores: Rodolfo Jardim de Azevedo, Guido Costa Souza de Araujo / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-08T21:29:56Z (GMT). No. of bitstreams: 1 Santos_RicardoRibeirodos_D.pdf: 1101695 bytes, checksum: 4ed1029f4633af49dda77618650600a7 (MD5) Previous issue date: 2007 / Resumo: Anúncios recentes sobre os limites do desempenho dos processadores devido ao alcance da barreira térmica têm motivado a pesquisa sobre novas organizações arquiteturais e modelos de execução que visam continuar o aumento de desempenho dos processadores. Este trabalho propõe uma nova arquitetura de processador denominada 2D-VLIW. A arquitetura possui uma organização arquitetural baseada em uma matriz bidimensional de unidades funcionais e de registradores distribuídos ao longo dessa matriz. O modelo de execução 2D-VLIW possibilita que instruções longas, formadas por operações simples, sejam buscadas na memória e executadas sobre a matriz de unidades funcionais. Além disso, são propostos algoritmos para geração de código para extrair o paralelismo e preparar o código para ser executado sobre a arquitetura. Algumas contribuições deste trabalho são a concepção de uma nova arquitetura de processador que explora paralelismo em nível de instruções através de um novo arranjo dos elementos arquiteturais, a adoção de um modelo de execução que captura a geometria dos DAGs e associa os vértices e arestas desses DAGs aos recursos do hardware, um conjunto de algoritmos para escalonamento de instruções, a alocação de registradores e a codificação de instruções na arquitetura 2D-VLIW. Os resultados experimentais comparam o desempenho do modelo de execução dessa arquitetura com o modelo EPIC adotado pelo processador HPL-PD. O speedup obtido por 2D-VLIW foi de 5% at'e 63%. A estratégia de escalonamento adotada por 2D-VLIW foi também avaliada e os ganhos obtidos através do OPC e OPI foram até 4 vezes melhores que aqueles obtidos por um algoritmo de escalonamento baseado em list scheduling / Abstract: Recent announcements on processor performance limits due to the thermal barrier have motivated research into innovative architectural organizations and execution models to sustain the increase of performance. This work proposes a new architecture named 2D-VLIW. The architecture provides a new architectural organization of the processing elements by using a two-dimensional functional units matrix and registers spread out along this matrix. The 2D-VLIW execution model fetches long instructions comprised of simple operations in the memory and dispatches these operations to the matrix. Moreover, the work presents new algorithms for code generation which are the responsible for extracting the parallelism of the applications and preparing the code for the 2D-VLIW architecture. Some contributions of this work are a new high performance architecture that exploits instruction level parallelism by a new arrangement of the architectural elements, the adoption of an execution model that captures the geometry of the DAGs and matches them to the hardware resources, a set of algorithms for code generation that make them possible to schedule instructions, allocate registers and encode long instructions of the 2D-VLIW architecture. Experimentos were used for comparing the performance of the 2D-VLIWexecution model to the EPIC execution model of the HPL-PD architecture. The speedup obtained by 2D-VLIW ranges from 5%-63% for all the evaluated programs. The scheduling strategy based on subgraph isomorphism was also evaluated and the OPC and OPI gains were up to 4× better than that of the list scheduling algorithm / Doutorado / Doutor em Ciência da Computação

Abstract The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs) has traditionally required test instruments with higher linearity and resolution than that of the device under test. In this thesis ways to test converters without expensive precision instruments are studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) and integral non-linearity (INL) estimation is proposed. The algorithm assumes that two stimuli with constant offset between them are applied to the ADC under test and that the code density histograms for both stimuli are recorded. The probability density function (PDF) of the stimulus is then solved using simple calculations so that DNL and INL of the ADC can be estimated without a priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputs are digital and the new algorithm can be used to obtain the PDF of the DAC output. Moreover, the PDF of DAC actually characterizes its INL and DNL so that this all-digital test configuration enables a simultaneous testing of both converters thanks to the new algorithm. The proposed algorithm is analyzed thoroughly both mathematically and by carrying out several simulations and experimental tests. On the basis of the analysis it is possible to approximate the impending estimation error and select the optimal value for the offset between the stimuli. In theory, the accuracy of the algorithm proposed equals that of the standard histogram method with ideal stimulus, but in practice, the accuracy is limited by that of the offset between the stimuli. Therefore, special attention is paid to development of an accurate and small offset generator which enables ratiometric test setup and solves the problems in the case of reference voltage drift. The proposed on-chip offset generator is built using only four resistors and switches. It occupies 122·22 μm2 in a 130 nm CMOS process and accuracy is appropriate for the INL testing of 12-bit converters from rail-to-rail. Based on the analysis of the influence of resistor non-linearity on the accuracy of offset, it is possible to improve the offset generator further. With discrete resistors, the INL of 16-bit ADCs was tested using a 12-bit signal generator. The proposed simple algorithm and tiny offset generator are considered to be important steps towards built-in DNL and INL testing of ADCs and DACs.

The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of a standard reference. The standard response is typically obtained from simulations. The test pattern and response are created and evaluated assuming ideal test conditions. The standard response is normally stored within automated test equipment (ATE). However the use of ATE is the major contributor to the test cost. This thesis explores an alternative strategy to the standard response. As an alternative to the stored standard response, the response is estimated by fault tolerant technique. The purpose of the fault tolerant technique is to eliminate the need of standard response and enable online/real-time testing. Fault tolerant techniques use redundancy and majority voting to estimate the standard response. Redundancy in the circuit leads to fault aliasing. Fault aliasing misleads the majority voter in estimating the standard response. The statistics and phenomenon of aliasing are analyzed for benchmark circuits. The impact of fault aliasing on test with respect to coverage, test escape and over-kill is analyzed. The results show that aliasing can be detected with additional test vectors and get 100% fault coverage.

In order to improve the sensitivity of an optical receiver, the gain and the collection area of the photo-detectors within the receiver should be increased. Detectors with internal gain such as avalanche photodiodes (APD) are usually used to increase the sensitivity of the receiver. One problem with APDs is the sensitivity of their gain to their bias voltage, which makes them challenging to be fabricated in a standard CMOS process due to variations in their gain. However, when an APD is biased over its breakdown voltage, it is sensitive to a single photon, hence, referred to as a single photon avalanche diodes (SPAD). The SPADs are photon-counting detectors, which are less sensitive to their bias voltage, and can be integrated with rest of the electronic circuitry that form an optical receiver. An avalanche diode requires dedicated circuits to be operated in the SPAD mode. These circuits make the diode insensitive to an incident photon for a duration that is known as deadtime. Unfortunately, The collection area of the PD, APD, and SPADs are limited to their capacitance. Hence, a large photo-detector leads to a larger capacitance, which reduces the bandwidth of the receiver. In this thesis, a photon counting optical receiver based on an array of SPADs is proposed which increases the collection area with a low output capacitance. The avalanche diode and peripheral circuits which operate and readout-out the SPAD array are fabricated in the commercially available UMC 0.18 μm CMOS process. Initially, the avalanche diode is tested and characterised. A high performance circuit is then designed and tested which is able to achieve short deadtimes up to 4 ns. Once the photon counting operation of the SPAD is verified, a numerical model is developed to investigate the influence of several factors, including the deadtime, on the performance of the photon-counting detector in a communication link. Based on the simulation results, which show the advantages of an array over a single detector, a prototype detector array of 64 asynchronous SPADs is designed and tested. This array uses a high-speed readout mechanism which is inspired by the current steering digital-to-analogue converters. Bit error ratio tests (BERT) verify the photon counting capability of the proposed detector, and a bit error rate of 1E-3 has been achieved at data rate of 100 Mbps. In addition, the array of SPAD is compatible with a front-end of conventional optical receiver which uses a photodiode as a photo detector.

Today, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic volume changes that can occur during the day or even a month. To improve traffic signal operation most of the traffic signal controllers in the same corridor or zone operate in coordination mode. Furthermore, phases need to be in coordination to achieve “green wave”. Green wave is term used when in corridor traffic lights allow continues flow of traffic through intersections that are coordinated. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2016. / FAU Electronic Theses and Dissertations Collection

Yang, Xiaoqing. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 113-120). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.