Made available in DSpace on 2015-04-14T13:56:40Z (GMT). No. of bitstreams: 1 395124.pdf: 1485381 bytes, checksum: 9936ed7d7bb8dd338419e42e6aea0c89 (MD5) Previous issue date: 2007-08-02 / O constante aumento na densidade dos dispositivos de l?gica program?vel (FPGA s), aliado ? diminui??o dos pre?os destes circuito integrados, tem viabilizado a implementa??o de sistemas complexos, que antes necessariamente implicavam no uso de circuitos integrados dedicados. Em projetos onde um FPGA j? ? utilizado, justifica-se ainda mais facilmente a integra??o de novas funcionalidades ao projeto de l?gica program?vel, uma vez que os custos envolvendo as ferramentas de desenvolvimento, tanto de hardware quanto de software, j? foram contabilizados. Este trabalho implementa uma bridge ethernet atrav?s de um sistema composto por um softprocessor, onde as fun??es relativas ? classifica??o e encaminhamento dos pacotes s?o realizadas em software, o que torna o sistema mais acess?vel ? mudan?as na implementa??o e de f?cil manuten??o. Al?m do softprocessor, implementados em VHDL ainda temos um controlador de acesso ao meio f?sico ethernet (MAC) e um controlador HDLC o qual ? utilizado como ponto de liga??o entre as bridge local e a bridge remota. A prototipagem do sistema, para avalia??o e an?lise de desempenho, ? feita com o uso das ferramentas de software e placas de desenvolvimento de hardware da Xilinx, por serem de f?cil acesso e que oferecem o n?cleo de softprocessor MicroBlaze, um microprocessador RISC de 32 bits com arquitetura harvard. A an?lise de desempenho do sistema, realizada com o aux?lio de ferramentas de software (Iperf) e hardware (SmartBits), mostrou que a bridge consegue atingir taxas acima de 1Mbps com pacotes pequenos (64 bytes), t?picos das aplica??es VoIP. Para pacotes maiores, o desempenho se aproximou dos 2 Mbps, que representam a taxa t?pica m?xima onde este dispositivo ser? usado na pr?tica. Devido ? sua natureza extremamente male?vel, em vista da utiliza??o de l?gica program?vel e de fun??es de software, o sistema permite a inclus?o de novas facilidades em atividades futuras, tais como a filtragem de pacotes, redes locais virtuais (VLAN s) e o protocolo Spanning Tree. Al?m de novas funcionalidades de software, novos m?dulos do hardware sintetiz?vel tamb?m podem ser incorporados, sejam para desempenhar novas fun??es, tais como o aumento das interfaces WAN, como para otimizar m?dulos j? existentes.

El presente proyecto de tesis consiste en el diseño de una red de transporte de datos multidepartamental en el Perú, con el objetivo de ofrecer servicios Carrier Ethernet con protección a nivel de capa 2 según el modelo OSI. El mecanismo de protección propuesto es G.8032 y la red permitirá otorgar perfiles de QoS a los servicios de los clientes. El primer capítulo ofrece una visión general de la evolución de las redes de transmisión de datos del Perú, así como una breve presentación del actual despliegue del proyecto de Red Dorsal Nacional de Fibra Óptica. Además se muestra un enfoque de la importancia de la tecnología Ethernet en la actualidad. El segundo capítulo presenta el marco teórico de la arquitectura de una red Carrier Ethernet, así como el mecanismo de protección para topologías en anillo G.8032, con sus principales características y funcionalidades. El tercer capítulo analiza la evolución de la demanda de tráfico datos hasta la actualidad y realiza una proyección a 6 años de dicha demanda. El cuarto capítulo describe el diseño de los anillos lógicos correspondientes al mecanismo de protección G.8032, el diseño global de la red y una breve descripción de los equipos a usar y sus funcionalidades. El quinto capítulo detalla el cálculo del OPEX y el CAPEX de la red, así como los ingresos recurrentes por los servicios dedicados prestados a las empresas u operadoras de telecomunicaciones. Por último, se presentan las conclusiones y recomendaciones del presente trabajo, que permitirán consolidar y/o mejorar la solución desarrollada en la presente tesis. / Tesis

Submitted by Samira Prince (prince@ufpa.br) on 2012-06-05T16:22:35Z No. of bitstreams: 2 Dissertacao_PropostaMinimizarPenalidade.pdf: 1676269 bytes, checksum: 9b4c221be145de9e5952de5ca8f2d702 (MD5) license_rdf: 23898 bytes, checksum: e363e809996cf46ada20da1accfcd9c7 (MD5) / Approved for entry into archive by Samira Prince(prince@ufpa.br) on 2012-06-05T16:24:52Z (GMT) No. of bitstreams: 2 Dissertacao_PropostaMinimizarPenalidade.pdf: 1676269 bytes, checksum: 9b4c221be145de9e5952de5ca8f2d702 (MD5) license_rdf: 23898 bytes, checksum: e363e809996cf46ada20da1accfcd9c7 (MD5) / Made available in DSpace on 2012-06-05T16:24:52Z (GMT). No. of bitstreams: 2 Dissertacao_PropostaMinimizarPenalidade.pdf: 1676269 bytes, checksum: 9b4c221be145de9e5952de5ca8f2d702 (MD5) license_rdf: 23898 bytes, checksum: e363e809996cf46ada20da1accfcd9c7 (MD5) Previous issue date: 2011 / Neste trabalho, propõe-se uma melhoria na estratégia de escalonamento baseada em pesos das classes de tráfego em redes óticas passivas Ethernet – EPON, de modo a não penalizar demasiadamente a classe tipo melhor esforço (BE). Como suporte, desenvolveu-se um modelo híbrido analítico/simulado para análise de desempenho do fluxo de subida, baseado no atraso total de quadros. A modelagem foi feita utilizando Redes de Petri Coloridas Estocásticas (Stochastic Colored Petri Nets - SCPN) da qual se obtém, por simulação, o tamanho médio da fila que posteriormente é usado para, analiticamente, obter-se o atraso total. Não obstante ao crescimento de aplicações multimídia em tempo real, no ano de 2010, o tráfego tradicional na Internet (navegação web, email, mensagens instantâneas) classificado como melhor esforço ainda foi responsável, sozinho (excluindo transferência de arquivos P2P), por valores em torno de 18% do tráfego na Internet. Somando-se a este percentual as aplicações P2P, que também não são essencialmente sensíveis ao atraso, têm-se uma participação de 58% (o tráfego P2P foi no ano de 2010 responsável por aproximadamente 40% do volume total de informações trafegadas na Internet). Mesmo em previsões feitas para o ano de 2014 o tráfego BE ainda representará aproximadamente 40% do volume total de dados a serem trafegados nas redes IPs mundiais. Estes números demonstram que a preocupação com este tipo de tráfego não pode ser relegada a uma importância secundária em detrimento às aplicações que exigem maior qualidade de serviço. Tomando como base o escalonamento IPACT (Interleaved Polling with Adapting Cycle Time) esta dissertação demonstra que é possível, através da melhoria proposta, obter atrasos menores no tráfego de melhor esforço, sem que as classes de tráfego prioritárias ultrapassem as especificações de atraso recomendadas para cada uma destas. / An improvement in the scheduling strategy based on weights of classes of traffic (CoS) is proposed in this work so as not to penalize too much the best-effort (BE) class type. As support, a hybrid analytical/simulated model to analyze the performance of upstream flows in Ethernet Optical Passive Networks (EPON) based on frame’s total delay, was developed. The modeling was done using Stochastic Colored Petri Networks (SCPN), from where the average queue size is obtained. Then, this average is used to analytically obtain the total delay. Besides the growth of multimedia real-time applications, the traditional traffic in the Internet (as web browser, email and instant messengers) is still, alone, responsible for 18% of the total traffic (excluding P2P traffic). Adding the P2P applications load, which traffic is also not sensible to delay, a 58% of participation is reached (only P2P traffic was responsible for 40% of the total traffic flowing thru the Internet in the year of 2010). Also in traffic’s forecasts for 2014 the Best Effort (BE) traffic will be still responsible for 40% of the total load in IP networks in the world. This numbers shows that the cares with this kind of traffic cannot be put in low relevance while giving more resources to classes that requires more quality of services. Having the scheduling strategy called IPA(Interleaved Polling with Adapting Cycle Time) as a base, this work demonstrates, by the improvement proposed, that is possible to reach lowers delays in the best effort traffic, without making the upper priority classes reach delays over the parameters recommended for which one.

Este trabalho apresenta o projeto, a verificação funcional e a síntese dos módulos funcionais de um comutador Gigabit Ethernet. As funções destes módulos encontramse definidas nos padrões IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 e nos seguintes RFCs (Request for Comments): RFC 2697, RFC 2698 e RFC 4115. Estes módulos formam o núcleo funcional do comutador e implementam as principais funções dele. Neste trabalho quatro módulos são desenvolvidos e validados. Estes módulos foram projetados para serem inseridos na plataforma NetFPGA, formando o chamado “User Data Path”. Esta plataforma foi desenvolvida pela universidade de Stanford para permitir a prototipagem rápida de hardware para redes. O primeiro módulo chamado de “Árbitro de entrada” decide qual das portas de entrada do comutador ele vai atender, para que os quadros que ingressam por essa porta sejam processados. Este módulo utiliza um algoritmo Deficit Round Robin (DRR). Este algoritmo corrige um problema encontrado no módulo original desenvolvido na plataforma NetFPGA. O segundo módulo é o “Pesquisador da porta de saída”. O bloco principal deste módulo é o motor de classificação. A função principal do motor de classificação e aprendizagem de endereços MAC é encaminhar os quadros à suas respectivas portas de saída. Para cumprir esta tarefa, ele armazena o endereço MAC de origem dos quadros em uma memória SRAM e é associado a uma das portas de entrada. Este motor de classificação utiliza um mecanismo de hashing que foi provado que é eficaz em termos de desempenho e custo de implementação. São apresentadas duas propostas para implementar o motor de classificação. Os resultados da segunda proposta permite pesquisar efetivamente 62,5 milhões de quadros por segundo, que é suficiente para trabalhar a uma taxa wire-speed em um comutador Gigabit de 42 portas. O maior desafio foi conseguir a taxa de wire-speed durante o processo de “aprendizagem” usando uma memória SRAM externa. O terceiro módulo é o marcador de quadros. Este módulo faz parte do mecanismo de qualidade de serviço (QoS). Com este módulo é possível definir uma taxa máxima de transferência para cada uma das portas do comutador. O quarto módulo (Output Queues) implementa as filas de saída do comutador. Este módulo faz parte de plataforma NetFPGA, mas alguns erros foram encontrados e corrigidos durante o processo de verificação. Os blocos foram projetados utilizando Verilog HDL e visando as suas implementações em ASIC, baseado em uma tecnologia de 180 nanômetros da TSMC com a metodologia Semi-Custom baseada em standard cells. Para a verificação funcional foi utilizada a linguagem SystemVerilog. Uma abordagem de estímulos aleatórios restritos é utilizada em um ambiente de testbench com capacidade de verificação automática. Os resultados da verificação funcional indicam que foi atingido um alto porcentual de cobertura de código e funcional. Estes indicadores avaliam a qualidade e a confiabilidade da verificação funcional. Os resultados da implementação em ASIC amostram que os quatro módulos desenvolvidos atingem a freqüência de operação (125 MHz) definida para o funcionamento completo do comutador. Os resultados de área e potência mostram que o módulo das Filas de saída possui a maior área e consumo de potência. Este módulo representa o 92% da área (115 K portas lógicas equivalentes) e o 70% da potência (542 mW) do “User Data Path”. / This work presents the design, functional verification and synthesis of the functional modules of a Gigabit Ethernet switch. The functions of these modules are defined in the IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 standards and the following RFCs (Request for Comments): RFC 2697, RFC 2698 and RFC 4115. These modules are part of the functional core of the switch and implement the principal functions of it. In this work four modules are developed and validated. These modules were designed to be inserted in the NetFPGA platform, as part of the “User Data Path”. This platform was developed at Stanford University to enable the fast prototype of networking hardware. The first module called “input arbiter” decides which input port to serve next. This module uses an algorithm Deficit Round Robin (DRR). This algorithm corrects a problem found in the original module developed in the NetFPGA platform. The second module is the classification engine. The main function of the MAC address classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task, it stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation cost. It can search effectively 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the “learning” process using external SRAM memory. The third module is the frame marker. This module is part of the quality of service mechanism (QoS). With this module is possible to define a maximum transmission rate for each port of the switch. The fourth module (Output Queues) implements the output queues of the switch. This module is part of the NetFPGA platform, but some errors were found and corrected during the verification process. These module were designed using Verilog HDL, targeting the NetFPGA prototype board and an ASIC based on a 180 nm process from TSMC with the Semi-custom methodology based on standard cells. For the functional verification stage is used the SystemVerilog language. A constrained-random stimulus approach is used in a layered-testbench environment with self-checking capability. The results from the functional verification indicate that it was reached a high percentage of functional and code coverage. These indicators evaluate the quality and reliability of the functional verification. The results from the ASIC implementation show that the four modules developed achieve the operation frequency (125 MHz) defined for the overall switch operation. The area and power results demonstrate that the Output Queues module has the largest area and power consumption. This module represents the 92% of area (115 K equivalent logic gates) and the 70% of power (542 mW) from the User Data Path.

Dissertação apresentada para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores (Área de especialização de Informática Industrial), na Faculdade de Engenharia da Universidade do Porto, sob a orientação do Professor Paulo José Cerqueira Gomes da Costa

Fieldbuses are defined as a family of communication media specified for industrial applications. They usually interconnect embedded systems. Embedded systems exist everywhere in the modern world, they are included in simple personal technology as well as the most advanced spaceships. They aid in producing a specific task, often with the purpose to generate a greater system functionality. These kinds of implementations put high demands on the communication media. For a medium to be applicable for use in embedded systems, it has to reach certain requirements. Systems in industry practice react on real-time events or depend on consistent timing. All kinds are time sensitive in their way. Failing to complete a task could lead to irritation in slow monitoring tasks, or catastrophic events in failing nuclear reactors. Fieldbuses are optimized for this usage. This thesis aims to research fieldbus theory and connect it to industry practice. Through interviews, requirements put on industry are explored and utilization of specific types of fieldbuses assessed. Based on the interviews, guidelines are put forward into what fieldbus techniques are relevant to study in preparation for future work in the field. A discussion is held, analysing trends in, and synergy between, state of the art and the state of practice. A strong momentum is identified. The traditional communication media Ethernet, not originally intended for time-sensitive industry appliances, are expanding throughout the field, both in research and, maybe most interestingly, in practice. It is mainly motivated through qualities of somewhat lesser technical significance. A plethora of methods have emerged trying to optimize Ethernet for real-time purposes, each one resulting in some drawbacks, which are in turn addressed. In the end of this paper, the large-scale trend of Real-Time Ethernet is questioned and discussed.

<p>The result of this master thesis report describes the advantages and the drawbacks that will arise when implementing an Ethernet based intercommunication system in military vehicles. The report presents a possible solution and describes how different sound applications will be implemented into the suggested solution. </p><p>The report show that IP LAN in vehicles leads to more advantages than drawbacks. The main advantages are that all kind of media can share the same LAN and that there is a lot of knowledge of this technique in the civil area. The main drawback is about delay. The drawbacks are otherwise well known and methods are known to decrease the impact of them. In the suggested intercommunication system the processing delay gives the largest impact on not deliver data in real time. The suggested solution, with separate connections for intercom unit and PC platform to the switch at each crew member gives good reliability and security.</p>

<p>Due to the development towards more dense programmable devices (FPGAs) it is today possible to fit a complete embedded system including microprocessor, bus architecture, memory, and custom peripherals onto one single reprogrammable chip, it is called a System-on-Chip (SoC). The custom peripherals can be of literally any nature from I/O interfaces to Ethernet Media Access Controllers. The latter core, however, usually consumes a big part of a good sized FPGA. The purpose of this thesis is to explore the possibilities of interfacing an FPGA based Microblaze system to an off-chip Ethernet MAC/PHY. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. This work includes evaluation of different available Ethernet devices, decision of interface technology, implementation of the interface, testing and verification. Since the ISA interface still is a common interface to Ethernet MAC devices a bus bridge is implemented linking the internal On-Chip Peripheral Bus (OPB) with the ISA bus. Due to delivery delays of the selected Ethernet chip a small on-chip ISA peripheral was constructed to provide a tool for the testing and verification of the bus bridge. The main result of this work is an OPB to ISA bus bridge core. The bridge was determined to work according to specification, and with this report at hand the connection of the Ethernet chip to the system should be quite straightforward.</p>

<p>Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design.</p><p>Hence, the purpose of this master's thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description language called VHDL. The method for this master's thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.</p>

<p>Switched Ethernet is an Ethernet LAN that uses switches to connect individual nodes. </p><p>This is popular because of its effective and convenient way of extending the bandwidth of </p><p>existing Ethernets. Switched Ethernet is being considered by the industry community because </p><p>of its open standardization, cost effectiveness, and the support for higher data rates up to </p><p>10Gbps. Even though many special-purposed solutions were proposed to support time </p><p>constrained communication over Switched Ethernet, still there were some doubts about the </p><p>real time handling capability of Switched Ethernet. To achieve reliable transmission </p><p>guarantees for real time traffic over Switched Ethernet, it is important to measure the </p><p>performance of Switched Ethernet networks for real time communication. In this thesis work </p><p>we have observed the average end-to-end packet delay for real time traffic over a Switched </p><p>Ethernet by simulation, which is very much essential for real time communication in </p><p>industrial applications, where the communication is time-deterministic. In our thesis we used </p><p>FCFS priority queuing in both the source nodes and switch. In this thesis we also discussed </p><p>about the feasibility analysis for fixed sized frames and some traffic handling methods. We </p><p>used 100mbp/s single full duplex Ethernet switch for our simulation. Finally simulation </p><p>analysis and simulation results are discussed. Our purpose of simulation of Switched Ethernet </p><p>networks is of good importance for the real time industrial applications.</p>