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Dans les technologies d'aujourd'hui, l’épitaxie est une technique indispensable pour la fabrication des composants. Avec la diminution continue de la taille des transistors les objets epitaxiés rétrécissent aussi. Par conséquence, des effets morphologiques qui sont négligeables à grande échelle, doivent être considéré dans les petits motifs, et de plus des anisotropies doivent être prises en compte. C'est pour cela que cette thèse est consacrée à l'étude de la morphologie en fonction de la taille et de l'orientation des motifs. La caractérisation de la morphologie du SiGe comme déposé sur des motifs orientés selon <100> et <110> nous conduit à introduire de nouveaux effets de charge, pas encore reportés dans la littérature. Après avoir étudié en profondeur la morphologie après croissance, les épitaxies sont soumises à des températures légèrement supérieures à celle de dépôt, et les changements sont discutés en fonction de l'orientation et de la largeur des lignes. Des recuits sous H2 à des températures plus élevées sont réalisés sur des motifs différents ce qui permet l'observation des effets morphologiques en bord et en coin de motif. Ces effets dominent la morphologie globale des couches epitaxiées quand la taille des motifs diminue. En particulier, la stabilité des lignes de Si et SiGe lors des recuits est étudiée, ce qui permet de déterminer les facteurs importants pour la stabilité des lignes. Dans des expériences supplémentaires un procédé est développé pour augmenter la stabilité thermique des couches SiGe. En outre, l'épitaxie cyclique - nécessaire pour réaliser les sources/drains des CMOS avancés - est discutée. L'influence des changements dans l'étape de gravure d'un procédé cyclique de Si, en gardant l'étape de dépôt inchangée, est étudiée pour des motifs orientés selon <100>. Nous avons trouvé des conditions dans lesquelles la couche n'est plus continue. Des expériences pour étudier la gravure séparément permettent d'expliquer les phénomènes observés. / In current technology nodes, epitaxy is an indispensable technique in device fabrication. With the continuous decrease of the transistor size, the epitaxial objects shrink as well. As a consequence, morphology effects which can be neglected at the large scale, have to be considered in small patterns and in addition, anisotropies have to be taken into account. Therefore, this thesis is dedicated to morphology studies as a function of pattern size and orientation. The characterization of the SiGe morphology in the as-deposited state on <100> and <110> oriented patterns leads to the introduction of new loading effects, which have not been reported elsewhere so far. After having studied thoroughly the as-deposited morphology, the epitaxial layers are exposed to a temperature slightly higher than the deposition temperature and the changes are discussed as a function of line width and orientation. H2 annealing at higher temperatures are performed with various Si and SiGe patterns leading to the observation of morphology effects at the pattern edges and corners. These effects dominate the global layer appearance with decreasing pattern size. In particular, the stability of annealed Si and SiGe lines is studied which allows to determine the crucial factors for line stability. In additional experiments, a process is developed which can increase the thermal stability of epitaxial SiGe. Moreover, cyclic epitaxy - required for sources/drains of advanced CMOS devices - is discussed. The influence of changes in the etch step of a cyclic Si process, by keeping the deposition step unchanged, is studied for <100> oriented patterns. Conditions are found, where cyclic epitaxy results in a discontinuous layer. Experiments, which consider the etching separately can explain the observed phenomena.

This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si1-xGex) films for high-speed bipolar transistors.In situdoping of polycrystalline silicon (poly-Si)using phosphine (PH3) and disilane (Si2H6) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H2desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea. <b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,in situdoping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect

Heterojunction bipolar transistors (HBT) based on SiGeC havebeen investigated. Two high-frequency architectures have beendesigned, fabricated and characterized. Different collectordesigns were applied either by using selective epitaxial growthdoped with phosphorous or by non-selective epitaxial growthdoped with arsenic. Both designs have a non-selectivelydeposited SiGeC base doped with boron and a poly-crystallineemitter doped with phosphorous. Selective epitaxial growth of the collector layer has beendeveloped by using a reduced pressure chemical vapor deposition(RPCVD) technique. The incorporation of phosphorous and defectformation during selective deposition of these layers has beenstudied. A major problem of phosphorous-doping during selectiveepitaxy is segregation. Different methods, e.g. chemical orthermal oxidation, are shown to efficiently remove thesegregated dopants. Chemical-mechanical polishing (CMP) hasalso been used as an alternative to solve this problem. The CMPstep was successfully integrated in the HBT process flow. Epitaxial growth of Si1-x-yGexCy layers for base layerapplications in bipolar transistors has been investigated indetail. The optimization of the growth parameters has beenperformed in order to incorporate carbon substitutionally inthe SiGe matrix without increasing the defect density in theepitaxial layers. The thermal stability of npn SiGe-based heterojunctionstructures has been investigated. The influence of thediffusion of dopants in SiGe or in adjacent layers on thethermal stability of the structure has also been discussed. SiGeC-based transistors with both non-selectively depositedcollector and selectively grown collector have been fabricatedand electrically characterized. The fabricated transistorsexhibit electrostatic current gain values in the range of 1000-2000. The cut-off frequency and maximum oscillation frequencyvary from 40-80 GHz and 15-30 GHz, respectively, depending onthe lateral design. The leakage current was investigated usinga selectively deposited collector design and possible causesfor leakage has been discussed. Solutions for decreasing thejunction leakage are proposed. <b>Key words:</b>Silicon-Germanium-Carbon (SiGeC),Heterojunction bipolar transistor (HBT), chemical vapordeposition (CVD), selective epitaxy, non-selective epitaxy,collector design, high-frequency measurement, dopantsegregation, thermal stability.

<p>This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si_1-xGe_x) films for high-speed bipolar transistors.<i>In situ</i>doping of polycrystalline silicon (poly-Si)using phosphine (PH₃) and disilane (Si₂H₆) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H₂desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea.</p><p><b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,<i>in situ</i>doping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect</p>

<p>Heterojunction bipolar transistors (HBT) based on SiGeC havebeen investigated. Two high-frequency architectures have beendesigned, fabricated and characterized. Different collectordesigns were applied either by using selective epitaxial growthdoped with phosphorous or by non-selective epitaxial growthdoped with arsenic. Both designs have a non-selectivelydeposited SiGeC base doped with boron and a poly-crystallineemitter doped with phosphorous.</p><p>Selective epitaxial growth of the collector layer has beendeveloped by using a reduced pressure chemical vapor deposition(RPCVD) technique. The incorporation of phosphorous and defectformation during selective deposition of these layers has beenstudied. A major problem of phosphorous-doping during selectiveepitaxy is segregation. Different methods, e.g. chemical orthermal oxidation, are shown to efficiently remove thesegregated dopants. Chemical-mechanical polishing (CMP) hasalso been used as an alternative to solve this problem. The CMPstep was successfully integrated in the HBT process flow.</p><p>Epitaxial growth of Si1-x-yGexCy layers for base layerapplications in bipolar transistors has been investigated indetail. The optimization of the growth parameters has beenperformed in order to incorporate carbon substitutionally inthe SiGe matrix without increasing the defect density in theepitaxial layers.</p><p>The thermal stability of npn SiGe-based heterojunctionstructures has been investigated. The influence of thediffusion of dopants in SiGe or in adjacent layers on thethermal stability of the structure has also been discussed.</p><p>SiGeC-based transistors with both non-selectively depositedcollector and selectively grown collector have been fabricatedand electrically characterized. The fabricated transistorsexhibit electrostatic current gain values in the range of 1000-2000. The cut-off frequency and maximum oscillation frequencyvary from 40-80 GHz and 15-30 GHz, respectively, depending onthe lateral design. The leakage current was investigated usinga selectively deposited collector design and possible causesfor leakage has been discussed. Solutions for decreasing thejunction leakage are proposed.</p><p><b>Key words:</b>Silicon-Germanium-Carbon (SiGeC),Heterojunction bipolar transistor (HBT), chemical vapordeposition (CVD), selective epitaxy, non-selective epitaxy,collector design, high-frequency measurement, dopantsegregation, thermal stability.</p>

Made available in DSpace on 2015-03-26T13:35:11Z (GMT). No. of bitstreams: 1 texto completo.pdf: 2893346 bytes, checksum: 9ae656930afe35b3a72cddee0c2cc87c (MD5) Previous issue date: 2009-05-29 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The epitaxial growth technique by molecular beams (Molecular Beam Epitaxy &#8211; MBE) can be considered as one of the most important for obtaining thin fine films, heterostructures and nanostructures nowadays, allowing the production of high quality layers, and it also allows the in situ monitoring of process through several techniques of characterization. This work presents the project, the construction and the initial tests of a MBE system for the growing of compounds containing cadmium, tellurium, manganese and zinc. The work shows a bibliographic revision of the main types of epitaxy, some of the main techniques of growth, the basic principles of vacuum technology and the necessary tools to the construction of the system. The detailed project of the system and its main components represented. Finally, the functioning tests of the vacuum systems, the effusion cells, the system of controlling and automation and the results obtained with the first obtained samples represented. The total cost of the system in the current configuration is approximately R$150.000 which is about as less as one fourth of one commercial system with approximately the same characteristics. / A técnica de crescimento epitaxial por feixes moleculares (Molecular Beam Epitaxy &#8211; MBE) pode ser considerada como uma das mais importantes para a obtenção de filmes finos, heteroestruturas e nanoestruturas nos dias atuais, permitindo a obtenção de filmes de excelente qualidade, além de permitir o acompanhamento do crescimento in situ através de diversas técnicas de caracterização. Este trabalho aborda o projeto, a construção e os testes iniciais de um sistema de MBE para o crescimento de compostos contendo Cádmio, Telúrio, Manganês e Zinco. O trabalho apresenta uma revisão bibliográfica dos principais tipos de epitaxia, algumas das principais técnicas de crescimento, princípios básicos da tecnologia de vácuo e os instrumentos necessários à construção do sistema. É apresentado o projeto detalhado do sistema e seus principais componentes. Finalmente, descrevem-se os testes de funcionamento do sistema de vácuo, das células de efusão, o sistema de controle e automatização e os resultados obtidos com as primeiras amostras obtidas. O custo total do sistema na configuração atual é de aproximadamente R$ 150.000, cerca de 4 vezes menor que o de um sistema comercial com aproximadamente as mesmas características.

The continuous evolution of digital technology we enjoy today is the result of ever shrinking, faster and cheaper transistors that make up the ubiquitous integrated circuits of our devices. Over the decades, the industry has gone from purely geometrical scaling to innovative solutions like high-k dielectrics combined with metal gates and FinFETs. A possible future is the use of high mobility materials such as Germanium for the active areas of a transistor instead of Silicon. As a step towards building devices on Ge, we characterize a gate last process with epitaxial deposition of Si0.75Ge0.25 source and drain areas on bulk Si wafers. Devices fabricated are proof-of-concept PMOSFETs and NMOSFETs with channel widths of 10 µm and 40 µm and channel lengths between 0.6 µm and 50 µm. The gate electrode of the fabricated devices is insitu doped polycrystalline Silicon. The devices are electrically characterized through I-V measurements and exhibit a yield of 95%. / Den konstanta utvecklingen av digital teknik som vi åtnjuter idag drivs av den ständiga utvecklingen av transistorer. Dessa blir mer kompakta, snabbare och kostar mindre för varje generation och bygger upp de integrerade kretsar som driver all vår vardagsteknik. Under ett tidsspann på flera decennier har krympningen gått från enbart geometrisk skalning till mer innovativa lösningar. Gate-oxiden har gått från rent kiseldioxid till material med lägre relativ permittivitet vilket möjliggjort en tunnare ekvivalent elektrisk tjocklek än vad som varit möjligt för kiseloxid. FinFet eller så kallade ’tri-gate’ transistorer har ersatt den plana varianten för att öka den ledande arean utan att enheterna sväller ut över substratet. En framtida möjlighet är även att använda material med högre mobilitet för elektroner och hål än kisel där en möjlig kandidat är Germanium. Som ett steg mot målet at bygga Germanium-transistorer tillverkar vi här gate last transistorer med source och drain i in-situ dopad kisel-germanium. Dessa konceptenheter används för att definiera och utveckla tillverkningsprocessen och tillverkas i flera omgångar. Varje skiva innehåller transistorer med en bredd på 40 µm och 10 µm. Kanallängden på transistorerna går mellan 0.6 µm och 50 µm för båda bredderna och av varje enhet finns 101 stycken per kiselskiva (100 mm diameter). Gate-elektroden består i samtliga fall av in-situ dopat poly-kristallint kisel. Enheterna karaktäriseras därefter genom elektriska mätningar och mätdata analyseras och sammanställs. Det visas genom dessa mätningar att ett utfall om över 95% fungerande enheter kan uppnås med processen.

Diese Arbeit befasst sich mit dem Wachstum von Dünnschichtstrukturen, die zur Herstellung eines Spin-selektiven Schottky-Barrier-Tunneltransistors (SS-SBTT) erforderlich sind. Das Bauelement basiert auf dem Transport von Ladungsträgern durch eine dünne halbleitende (SC) Schicht, die zwei ferromagnetische (FM) Kontakte trennt. Daher müssen hochqualitative und gitterangepasste vertikale FM/SC/FM-Trilayer gezüchtet werden, was aufgrund der inkompatiblen Kristallisationsenergien zwischen SC und Metallen eine experimentelle Herausforderung darstellt. Das Problem wurde mit einem Festphasenepitaxie-Ansatz gelöst, bei dem eine dünne amorphe Ge-Schicht (4-8 nm) durch Ausglühen über Fe3Si auf GaAs(001)-Substraten kristallisiert wird. Langsame Glühgeschwindigkeiten bis zu einer Temperatur von 260°C konnten ein neues gitterangepasstes Polymorph von FeGe2 erzeugen, über das ein zweites Fe3Si mittels Molekularstrahlepitaxie gezüchtet werden könnte. SQUID-Magnetometermessungen zeigen, dass die dreischichtigen Proben in antiparallele Magnetisierungszustände versetzt werden können. Vertikale Spin-Ventil-Bauelemente, die mit verschiedenen Trilayern hergestellt wurden, wurden verwendet, um zu demonstrieren, dass der Ladungstransport über die Heteroübergänge spinselektiv ist und bei Raumtemperatur einen Magnetowiderstand von höchstens 0,3% aufweist. Der Effekt nimmt bei niedrigen Temperaturen ab, was mit einem ferromagnetischen Übergang in der FeGe2-Schicht korreliert. Durch TEM- und XRD-Experimente konnte festgestellt werden, dass das neue FeGe2-Polymorph die Raumgruppe P4mm aufweist und bis zu 17% Si-Atome als Ersatz für Ge-Stellen enthält. Die Isolierung von FeGe2 war möglich, indem das Verhältnis von Fe-, Si- und Ge-Atomen so eingestellt wurde, dass die richtige Stöchiometrie bei vollständiger Durchmischung erreicht wurde. Anhand von FeGe2-Dünnschichten wurde ein zunehmender spezifischer Widerstand bei niedriger Temperatur und ein semi-metallischer Charakter beobachtet. / This thesis discusses the growth of thin film structures required to fabricate a Spin-Selective Schottky Barrier Tunnel transistor (SS-SBTT). The device relies on charge carriers being transported through a thin semiconducting (SC) layer separating two ferromagnetic (FM) contacts. Thus, high quality and lattice-matched FM/SC/FM vertical trilayers must be grown, which is experimentally challenging due to incompatible crystallization energies between SC and metals. The problem was solved using a solid-phase epitaxy approach, whereby a thin amorphous layer of Ge (4-8 nm) is crystallized by annealing over Fe3Si on GaAs(001) substrates. Slow annealing rates up to a temperature of 260°C could produce a lattice-matched Ge-rich compound, over which a second Fe3Si could be grown my molecular-beam epitaxy. The compound obtained during annealing is a new layered polymorph of FeGe2. SQUID magnetometry measurements indicate that the trilayer samples can be placed in states of antiparallel magnetization. Vertical spin valve devices created using various trilayers were used to demonstrate that charge transport is spin-selective across the heterojunctions, showing a magnetoresistance of at most 0.3% at room temperature. The effect decreases at low temperature, correlating with a ferromagnetic transition in the FeGe2 layer. TEM and XRD experiments could determine that the new FeGe2 polymorph has a space group P4mm, containing up to 17% Si atoms substituting Ge sites. Isolating FeGe2 was possible by tuning the proportion Fe, Si and Ge atoms required to obtain the right stoichiometry upon full intermixing. Hall bars fabricated on FeGe2 thin films were used to observe an increasing resistivity at low temperature and semimetallic character.

Master of Science / Department of Electrical and Computer Engineering / Andrew Rys / It is important in semiconductor manufacturing to understand the physical and electrical characteristics of new proposed semiconductors to determine their usefulness. Many tests are used in order to achieve this goal, such as x-ray diffraction, Hall effect measurements, and the scanning electron microscope. With these tests, the usefulness of the semiconductor can be determined, leading to more possibilities for growth in industry. The purpose of the present study was to look at the semiconductor scandium nitride (ScN), grown using the hydride vapor phase epitaxy (HVPE) method on various substrates, and determine the physical and electrical properties of the sample. This study also sought to answer the following questions: 1) Can any trends be found from the results?, and 2) What possible application could scandium nitride be used for in the future? A sample set of scandium nitride samples was selected. Each one of these samples was checked for contaminants from the growth procedure, such as chlorine, under the scanning electron microscope and checked for good conduction of current needed for the Hall effect measurements. The thickness of the scandium nitride layer was computed using the scanning electron microscope. Using the thickness of the scandium nitride, Hall effect measurement values were computed. The plane the samples lie on was checked using x-ray diffraction. The test results shed light on many trends in the scandium nitride. Many of the samples were determined to have an aluminum nitride (AlN) contamination. This contamination led to a much higher resistivity and a much lower mobility no matter what thickness the scandium nitride was. The data from the samples was then used to offer suggestions on how to improve the growth process.