The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the transistor's breakdown caused by short channel effects. An alternative solution to this is the FinFET transistor technology, where the gate of the transistor is a three dimensional fin that surrounds the transistor and prevents the breakdown caused by scaling and short channel effects. FinFET devices are reported to have excellent control over short channel effects, high On/Off Ratio, extremely low gate leakage current and relative immunization over gate edge line roughness. Sub 20 nm node size is perceived to be the limit of scaling the CMOS transistors, but FinFETs can be scaled down further because of its unique design. Due to these advantages, the VLSI industry has now shifted to FinFET in implementation of their designs. However, these transistors have not been completely opened to academia. Analyzing and observing the effects of these devices can be pivotal in gaining an in-depth understanding of them. This thesis explores the implementation of FinFETs using a standard cell library designed using these transistors. The FinFET package file used to design these cells is a 15nm FinFET technology file developed by NCSU in collaboration with Cadence and Mentor Graphics. Post design, the cells were characterized, the results were analyzed and compared with cells designed using CMOS transistors at different node sizes to understand and extrapolate conclusions on FinFET devices.

Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques. / text

<p>Beta-gallium oxide (<i>β</i>-Ga₂O₃) is an emerging wide bandgap semiconductor for next generation power devices which offers the potential to replace GaN and SiC. It has an ultra-wide bandgap (UWBG) of 4.8 eV and a corresponding <i>E</i>_brof 8 MV/cm. <i>β</i>-Ga₂O₃also possesses a decent intrinsic electron mobility limit of 250 cm²/V<i>·</i>s, yielding high Baliga’s figure of merit of 3444. In addition, the large bandgap of <i>β</i>-Ga₂O₃gives stability in harsh environment operation at high temperatures. </p> <p>Although low-cost large-size <i>β</i>-Ga₂O₃native bulk substrates can be realized by melt growth methods, the unique property that (100) surface of <i>β</i>-Ga₂O₃has a large lattice constant of 12.23 Å allows it to be cleaved easily into thin and long nano-membranes. Therefore, <i>β</i>-Ga₂O₃FETs on foreign substrates by transferring can be fabricated and investigated before <i>β</i>-Ga₂O₃epitaxy technology becomes mature and economical viable. Moreover, integrating <i>β</i>-Ga₂O₃on high thermal conductivity materials has an advantage in terms of suppressing self-heating effects. </p><p>In this dissertation, structural and material innovations to overcome and improve critical challenges are summarized as follows: 1) Top-gate nano-membrane <i>β</i>-Ga₂O₃FETs on a high thermal conductivity diamond substrate with record high maximum drain current densities are demonstrated. The reduced self-heating effect due to high thermal conductivity of the substrate was verified by thermoreflectance measurement. 2) Local electro-thermal effect by electrical bias was applied to enhance the electrical performance of devices and improvements of electrical properties were shown after the annealing. 3) Thin thermal bridge materials such as HfO₂and ZrO₂were inserted between <i>β</i>-Ga₂O₃and a sapphire substrate to reduce self heating effects without using a diamond substrate. The improved thermal performance of the device was analyzed by phonon density of states plots of <i>β</i>-Ga₂O₃and the thin film materials. 4) Nano-membrane tri-gate <i>β</i>-Ga₂O₃FETs on SiO₂/Si substrate fabricated via exfoliation have been demonstrated for the first time. 5) Using the robustness of <i>β</i>-Ga₂O₃in harsh environments, <i>β</i>-Ga₂O₃ferroelectric FETs operating as synaptic devices up to 400 °C were demonstrated. The result offers the potential to use the novel device for ultra-wide bandgap logic applications, specifically neuromorphic computing exposed to harsh environments.<br></p>