Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicações teóricas, simulações numéricas e medidas experimentais para demonstrar a viabilidade do uso desta tecnologia em blocos de circuitos fundamentais, atuando como alternativa para permitir o contínuo escalamento de dispositivos. A motivação para o uso de transistores com corrente principal resultante do tunelamento de banda para banda consiste na proposta de superar o limite físico de inclinação de sublimiar da tecnologia CMOS convencional de 60 mV/década sob temperatura ambiente. Afinal, esta limitação impede a redução na tensão de alimentação de circuitos e, consequentemente, apresenta crescentes problemas quanto à dissipação de potência. Com este objetivo, foram realizadas simulações numéricas de diversas geometrias alternativas visando atenuar as características indesejáveis dos TFETs, como a corrente ambipolar e a relativamente baixa relação ION/IOFF. Inicialmente foram definidos os modelos necessários para representar adequadamente os fenômenos relevantes sob variação de temperatura e é definida uma estrutura capaz de minimizar os efeitos da ambipolaridade. Posteriormente, medidas experimentais foram utilizadas para calibrar as simulações e estudar o efeito da temperatura e do dimensionamento no funcionamento de dispositivos desta tecnologia. Comparando resultados práticos e simulados, nota-se como uma redução no comprimento de porta, com a consequente inserção de uma subposição (underlap) em relação à junção canal/dreno, e uma diminuição na temperatura permitem a obtenção de valores promissores de inclinação de sublimiar e de relação ION/IOFF. Com base nestes resultados individuais, foram projetados circuitos básicos de aplicações analógicas, notadamente espelho de corrente e par diferencial, para a avaliação da viabilidade de duas diferentes estruturas de transistores de tunelamento. Foram realizadas medidas experimentais e simulações numéricas de ambos os circuitos com variações nas condições de polarização, na situação de descasamento entre os dispositivos e na temperatura de operação. O impacto em parâmetros fundamentais dos circuitos estudados, como a tensão de conformidade, a razão de espelhamento de corrente e o ganho de tensão diferencial, foi comparado para estruturas de tunelamento pontual (Point TFET), de tunelamento em linha (Line TFET) e de FinFETs. Em relação aos circuitos de espelhos de corrente, observou-se alta tensão de conformidade e baixa dependência com a temperatura para os circuitos com transistores de tunelamento. O Point TFET ainda apresentava a vantagem adicional da baixa susceptibilidade ao descasamento do comprimento de canal, porém com a desvantagem da baixa magnitude da corrente de referência quando comparado ao espelho com Line TFETs ou FinFETs. Já no caso de pares diferenciais, a maior tensão de conformidade foi obtida com FinFETs, enquanto os transistores de tunelamento apresentaram em comum a não degradação do ganho com a temperatura. Novamente o circuito com Point TFETs apresentou melhor resultado quando houve descasamento, enquanto que as outras duas tecnologias foram superiores quando ao ganho de tensão diferencial. Dessa forma, foram propostas equações generalizadas para os parâmetros fundamentais de ambos os circuitos para as 3 tecnologias. De modo geral, foi possível validar, portanto, a viabilidade de transistores de tunelamento para a obtenção de dispositivos com bons parâmetros individuais e com bons impactos em circuitos analógicos fundamentais, reforçando a importância desta promissora tecnologia. / This works presents the study of tunneling field effect transistors, namely TFETs. Analyses have been performed based on theoretical explanations, numerical simulations and experimental data in order to show this technology suitability as part of basic circuit blocks, being an important alternative for the continuous devices scaling. The basic idea of making use of band-to-band tunneling as the main current component comes from the possibility of reaching sub-60 mV/decade subthreshold slopes at room temperature, differently from conventional CMOS devices. After all, this physical limitation causes relevant power dissipation issues, since it requires relatively high power supply voltages. Bearing this objective, numerical simulations of several alternative geometries have been performed in order to tackle TFETs disadvantages, such as the undesirable ambipolar currents and the low ION/IOFF ratio. At first, it was necessary to choose the most appropriate models to take into consideration the relevant phenomena under temperature variation and to define the physical structure in order to minimize ambipolar effects. After these analyses, experimental data have been used to calibrate simulation parameters and to study how temperature and physical dimensions affect the performance of devices based on this technology. Comparing experimental and simulated results, it was possible to notice that when the structure is designed with gate underlap related to channel/drain junction and the temperature decreases, it was possible to obtain promising values for subthreshold slope and ION/IOFF ratio. Based on the analyses of these individual results, basic analog circuits have been designed, namely current mirror and differential pair, so that two different tunneling devices structures have been highlighted. Experimental measurements and numeric simulations have been performed for both circuits, under different conditions in terms of bias voltages, channel length mismatch and operation temperature. The impact on fundamental circuit parameters, such as compliance voltage, current mirroring ratio and differential voltage gain, has been compared for circuits designed with Point TFETs, Line TFETs and FinFETs. Regarding current mirror circuits, the obtained results revealed higher values of compliance voltage and lower susceptibility to the temperature for circuits designed with tunneling transistors. In addition, Point TFETs provided the lowest susceptibility to channel length mismatch, but also the worst values of reference currents, when compared to circuits with Line TFETs and FinFETs. Following the same procedure for differential pair, higher compliance voltage was obtained for FinFETs, while both tunneling transistors structures presented better behavior for differential voltage gain susceptibility to temperature variation. Once more, pairs with Point TFETs showed the best performance in terms of channel length mismatch, but the worst magnitude of differential voltage gain. This way, general equations have been proposed to model relevant parameters for the circuits designed with each technology. From an overall point of view, it was possible to support the suitability of optimizing tunneling transistors in order to obtain devices with favorable individual parameters and positive impacts on essential analog circuits, reassuring the relevance of this promising technology.

Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicações teóricas, simulações numéricas e medidas experimentais para demonstrar a viabilidade do uso desta tecnologia em blocos de circuitos fundamentais, atuando como alternativa para permitir o contínuo escalamento de dispositivos. A motivação para o uso de transistores com corrente principal resultante do tunelamento de banda para banda consiste na proposta de superar o limite físico de inclinação de sublimiar da tecnologia CMOS convencional de 60 mV/década sob temperatura ambiente. Afinal, esta limitação impede a redução na tensão de alimentação de circuitos e, consequentemente, apresenta crescentes problemas quanto à dissipação de potência. Com este objetivo, foram realizadas simulações numéricas de diversas geometrias alternativas visando atenuar as características indesejáveis dos TFETs, como a corrente ambipolar e a relativamente baixa relação ION/IOFF. Inicialmente foram definidos os modelos necessários para representar adequadamente os fenômenos relevantes sob variação de temperatura e é definida uma estrutura capaz de minimizar os efeitos da ambipolaridade. Posteriormente, medidas experimentais foram utilizadas para calibrar as simulações e estudar o efeito da temperatura e do dimensionamento no funcionamento de dispositivos desta tecnologia. Comparando resultados práticos e simulados, nota-se como uma redução no comprimento de porta, com a consequente inserção de uma subposição (underlap) em relação à junção canal/dreno, e uma diminuição na temperatura permitem a obtenção de valores promissores de inclinação de sublimiar e de relação ION/IOFF. Com base nestes resultados individuais, foram projetados circuitos básicos de aplicações analógicas, notadamente espelho de corrente e par diferencial, para a avaliação da viabilidade de duas diferentes estruturas de transistores de tunelamento. Foram realizadas medidas experimentais e simulações numéricas de ambos os circuitos com variações nas condições de polarização, na situação de descasamento entre os dispositivos e na temperatura de operação. O impacto em parâmetros fundamentais dos circuitos estudados, como a tensão de conformidade, a razão de espelhamento de corrente e o ganho de tensão diferencial, foi comparado para estruturas de tunelamento pontual (Point TFET), de tunelamento em linha (Line TFET) e de FinFETs. Em relação aos circuitos de espelhos de corrente, observou-se alta tensão de conformidade e baixa dependência com a temperatura para os circuitos com transistores de tunelamento. O Point TFET ainda apresentava a vantagem adicional da baixa susceptibilidade ao descasamento do comprimento de canal, porém com a desvantagem da baixa magnitude da corrente de referência quando comparado ao espelho com Line TFETs ou FinFETs. Já no caso de pares diferenciais, a maior tensão de conformidade foi obtida com FinFETs, enquanto os transistores de tunelamento apresentaram em comum a não degradação do ganho com a temperatura. Novamente o circuito com Point TFETs apresentou melhor resultado quando houve descasamento, enquanto que as outras duas tecnologias foram superiores quando ao ganho de tensão diferencial. Dessa forma, foram propostas equações generalizadas para os parâmetros fundamentais de ambos os circuitos para as 3 tecnologias. De modo geral, foi possível validar, portanto, a viabilidade de transistores de tunelamento para a obtenção de dispositivos com bons parâmetros individuais e com bons impactos em circuitos analógicos fundamentais, reforçando a importância desta promissora tecnologia. / This works presents the study of tunneling field effect transistors, namely TFETs. Analyses have been performed based on theoretical explanations, numerical simulations and experimental data in order to show this technology suitability as part of basic circuit blocks, being an important alternative for the continuous devices scaling. The basic idea of making use of band-to-band tunneling as the main current component comes from the possibility of reaching sub-60 mV/decade subthreshold slopes at room temperature, differently from conventional CMOS devices. After all, this physical limitation causes relevant power dissipation issues, since it requires relatively high power supply voltages. Bearing this objective, numerical simulations of several alternative geometries have been performed in order to tackle TFETs disadvantages, such as the undesirable ambipolar currents and the low ION/IOFF ratio. At first, it was necessary to choose the most appropriate models to take into consideration the relevant phenomena under temperature variation and to define the physical structure in order to minimize ambipolar effects. After these analyses, experimental data have been used to calibrate simulation parameters and to study how temperature and physical dimensions affect the performance of devices based on this technology. Comparing experimental and simulated results, it was possible to notice that when the structure is designed with gate underlap related to channel/drain junction and the temperature decreases, it was possible to obtain promising values for subthreshold slope and ION/IOFF ratio. Based on the analyses of these individual results, basic analog circuits have been designed, namely current mirror and differential pair, so that two different tunneling devices structures have been highlighted. Experimental measurements and numeric simulations have been performed for both circuits, under different conditions in terms of bias voltages, channel length mismatch and operation temperature. The impact on fundamental circuit parameters, such as compliance voltage, current mirroring ratio and differential voltage gain, has been compared for circuits designed with Point TFETs, Line TFETs and FinFETs. Regarding current mirror circuits, the obtained results revealed higher values of compliance voltage and lower susceptibility to the temperature for circuits designed with tunneling transistors. In addition, Point TFETs provided the lowest susceptibility to channel length mismatch, but also the worst values of reference currents, when compared to circuits with Line TFETs and FinFETs. Following the same procedure for differential pair, higher compliance voltage was obtained for FinFETs, while both tunneling transistors structures presented better behavior for differential voltage gain susceptibility to temperature variation. Once more, pairs with Point TFETs showed the best performance in terms of channel length mismatch, but the worst magnitude of differential voltage gain. This way, general equations have been proposed to model relevant parameters for the circuits designed with each technology. From an overall point of view, it was possible to support the suitability of optimizing tunneling transistors in order to obtain devices with favorable individual parameters and positive impacts on essential analog circuits, reassuring the relevance of this promising technology.

La réduction de la taille des circuits CMOS vers des dimensions extrêmement petites est telle que son élément constitutif, le MOSFET à base de Silicium, commence à souffrir d’une faible efficacité de puissance. L’une des alternatives qui ne peut être écartée est le concept du transistor MOSFET à base de matériaux III-V. Ses propriétés de transport extraordinaires, apportées par les matériaux III-V, promettent de réduire la tension d’alimentation des circuits CMOS sans réduire leur performance. Cette transition technologique pourrait aboutir non seulement à des circuits CMOS plus petits, plus écologiques mais aussi à des circuits co-intégrés avec des technologies RF. C’est dans ce contexte que nous présentons, dans ce travail de thèse, la fabrication et la caractérisation des transistors MOSFET Ultra-Thin Body (UTB) à base d’InAs et du transistor FinFET à base d’InAs. La combinaison d’une longueur de grille extrêmement réduite, d’une faible résistance d’accès et d’une mobilité impressionnante dans le canal d’InAs a permis d’obtenir des courants importants (IMAX=2000mA/mm pour LG=25nm). Egalement, l‘utilisation des architectures du canal de type ultra mince et FinFET permet d’obtenir un bon contrôle électrostatique. De plus, une spécificité du procédé technologique présentée dans ce travail est les réalisations des contacts et du canal par une épitaxie par jets moléculaires (MBE) localisée. / Scaling the size of CMOS circuits to extremely small dimensions gets the semiconductor industry to a point where its cornerstone, Silicon-based MOSFET starts to suffer a poor power efficiency. In the quest for alternative solutions cannot be omitted a concept of III-V MOSFET. Its outstanding transport properties hold a promise of reduced CMOS supply voltage without compromising the performance. This can path a way not only to the smaller, greener electronics but also to more co-integrated RF and CMOS electronics. In this context, we present fabrication and characterization of Ultra-Thin body InAs MOSFETs and InAs FinFET. Synergy of a deeply scaled gate length, low access resistance and a high mobility of InAs channel enabled to obtain impressively high drain currents (IMAX=2000mA/mm for LG=25nm). Equally, the introduction of Ultra-Thin body and FinFET channel design provides an improved electrostatic control. A specific feature of the process presented in this work is a fabrication of contacts and channel by localized molecular beam epitaxy MBE epitaxy.

The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices. First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification. Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability. Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology. / QC20100708 / NEMO, NANOSIL, SINANO

Si complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices. / text

Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However, calibration requires going through temperature steps in a tester, increasing test application time and cost. Consequently, calibrating thermal sensors in typical digital designs including mainstream desktop and notebook processors increases the cost of the processor. This creates a need for design of thermal sensors whose accuracy does not vary significantly with process variations. Other qualities desired from thermal sensors include low area requirement so that many of them maybe integrated in a design as well as low power dissipation, such that the sensor itself does not become a significant source of heat. In this work, we developed a process variation tolerant thermal sensor design with (i) active compensation circuitry and (ii) signal dithering based self calibration technique to meet the above requirements in 32nm technology. Results show that we achieve 3ºC temperature accuracy, with a relatively small design which compares well with designs that are currently used.

No description available.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

The incredible technological advancements over the last century have been possible due to tiny trinkets designed using semiconducting crystalline materials, especially Silicon and III-V compounds. Silicon, a group IV element has become the first choice in developing microchips serving an ever-growing set of applications including, computation, RF communications, solar cells, power electronics, quantum computing and its periphery, optoelectronics, IOT sensors, and lately artificial intelligence. Billions of Si-based complementary transistors (CMOS) are present at the center of most computing devices used today such as HPC servers, compute farms, laptops, and smartphones. The astonishing rise in transistor count, performance, and functionality as well as the exponential reduction in cost has been possible over the past decades due to a singular idea: shrinking the device. However, this rule, also called Moore's Law has been slowing over the past two decades and has eventually come to a standstill in its traditional definition. Moore's law has since been sustained by ingenious innovations such as high-k gate dielectrics, vertical scaling, lattice strain engineering, novel material developments and, lately chiplets as well as multi-die vertical packaging. As conventional Si CMOS approaches a roadblock, this work presents research on Germanium-based multi-gate devices providing promise for faster and low-power operation. This work discusses how Ge grown on a GaAs substrate can be tuned and utilized to form a virtually defect-free channel for ultra-scaled multi-gate transistors. Calibrated solvers informed using in-house materials and devices as well as literature are used to predict device performance for advanced structures. Further, a hybrid CMOS system with the high hole mobility p-channel device formed using tensile strained Ge, and the high electron mobility n-channel device formed using the underlying InGaAs layer is proposed and simulated. As scaling approaches Gate-all-around Nanosheet FETs in 2024 and complementary-FETs (CFETs) around 2034, Ge-on-AlAs based transistors can offer unique process simplifications, defect reduction, yield improvement, and high-performance advantages showing promise for future IRDS nodes. The process design, material stack, device, and circuit performance for this novel Ge-based NSFET is presented in this work. The lack of large strain or strain relaxation in the NS multilayer starting stack is seen to be a great process advantage for the Ge-AlAs NSFET system. To a certain extent, Si seems omnipotent for all things electronics. However, one exception is on-chip light generation. A coherent electrically controllable on-chip light source is a central component critical for optoelectronics, quantum technologies, fiber communications, and sensing. Due to the indirect bandgap, Si cannot produce light hence direct bandgap materials such as GaAs and GaN have been the primary choice for off-chip light sources integrable on the platform. Interestingly, Ge has a pseudo-direct bandgap, i.e., unlike Silicon, it can be manipulated to produce light using heavy doping, tensile strain, and Sn alloying. Similar to conventional III-V light sources, reduction in the dimensionality of the gain medium, i.e., Ge can enable a drastic reduction in the current required to produce light, among other performance considerations. This reduced dimensionality can be achieved by forming quantum wells and quantum dots. In this work, two new types of Ge-based quantum well lasers are introduced and analyzed along with qualitative and quantitive benchmarking. The first QW laser uses a small epitaxial biaxial tensile strain to improve the direct-ness of the Ge gain medium. The internal quantum efficiency, net gain, and threshold current can be improved drastically by choosing the right tensile strain while staying within a certain critical thickness value. For the first time, the impact of biaxial tensile strain on the optical properties of Ge is analyzed and reported through a systematic study of the dielectric spectra and optical constant using VASE. The changes in the band structure due to tensile strain are correlated with the critical points to uncover various optical transitions. An even better QW laser architecture is possible by utilizing a GeSn QW. This QW laser uses Sn-alloying to form a GeSn active region which is further lattice matched to the waveguide (InGaAs) and the optical confinement layers (InAlAs) around it. This completely lattice-matched laser structure can offer unique advantages such as virtually defect-free active region, tunability as well as improved efficiency and threshold current density. The absence of strain and consequently strain relaxation in the laser stack enables one to steer away from the critical thickness limitation while opening doors to designing multiple quantum well lasers among other complex architectures. The impact of Sn alloying on the atomic structure, lattice coherence, and relaxation is analyzed through XRD reciprocal space maps and rocking curves as a function of Sn concentration. Further, this lattice-matched system, GeSn-InGaAs-InAlAs has the potential to mirror the benefits of the mature GaAs-AlGaAs system which led to many great technological innovations over the past decades such as lasers and LEDs. / Doctor of Philosophy / This thesis introduces two transistor technologies to extend the scaling beyond conventional Si devices into the next decade, and two QW laser technologies for integrated photonics. Through calibrated numerical solvers, a high mobility Ge and InGaAs cointegrated CMOS system for 0.5 V is introduced, analyzed and benchmarked with literature. A lattice matched Ge-on-AlAs multilayer stack is shown to have great potential to form a novel CMOS system which uses Ge Nanosheets, providing process advantage and superior performance. The next part of the thesis introduces two types of Ge based quantum well lasers, one based on tensile strained Ge and the other based on lattice matched Ge. Both show large performance improvements over previous attempts in literature. Lasing from an indirect bandgap material such as Ge, the associated challenges and performance metrics are discussed. Lastly, the optical, dielectrics and CP properties of tensile strained are presented for the first time uncovering interesting trends. Ge samples with increasing tensile strain are grown using MBE and measured using VASE to elucidate the physical phenomenon.

<div>Germanium-based MOS device which is considered as one of the promising alternative channel materials has been studied with well-known FinFET, nanowire structures and HKMG (High-k metal gate). Recent introduction of Ferroelectric (FE) Zr-doped HfO₂ (Hf_xZr_1-xO₂, HZO) has opened various possibilities both in memory and logic</div><div>applications.</div><div><br></div><div>First, integration of FE HZO into the conventional Ge platform was studied to demonstrate Ge FeFET. The FE oxide was deposited with optimized atomic layer deposition (ALD) recipe by intermixing HfO₂ and ZrO₂. The HZO film was characterized with FE tester, XRD and AR-XPS. Then, it was integrated into conventional gate stack of Ge devices to demonstrate Ge FeFETs. Polarization switching was measured with ultrafast measurement set-up down to 100 ps.</div><div><br></div><div>Then, HZO layer was controlled for the first demonstration of hysteresis-free Ge negative capacitance (NC) CMOS FinFETs with sub-60mV/dec SS bi-directionally at room temperature towards possible logic applications. Short channel effect in Ge NCFETs were compared with our reported work to show superior robustness. For smaller widths that cannot be directly written by the e-beam lithography tool, digital etching on Ge fins were optimized.</div><div>Lastly, Ge FeFET-based synaptic device for neuromorphic computing was demonstrated. Optimum pulsing schemes were tested for both potentiation and depression which resulted in highly linear and symmetric conductance profiles. Simulation was done to analyze Ge FeFET's role as a synaptic device for deep neural network.</div>