Ion sensing represents a grand research challenge. It finds a vast variety of applications in, e.g., gas sensing for domestic gases and ion detection in electrolytes for chemical-biological-medical monitoring. Semiconductor genome sequencing exemplifies a revolutionary application of the latter. For such sensing applications, the signal mostly spans in the low frequency regime. Therefore, low-frequency noise (LFN) present in the same frequency domain places a limit on the minimum detectable variation of the sensing signal and constitutes a major research and development objective of ion sensing devices. This thesis focuses on understanding LFN in ion sensing based on both experimental and theoretical studies. The thesis starts with demonstrating a novel device concept, i.e., ion-gated bipolar amplifier (IGBA), aiming at boosting the signal for mitigating the interference by external noise. An IGBA device consists of a modified ion-sensitive field-effect transistors (ISFET) intimately integrated with a bipolar junction transistor as the internal current amplifier with an achieved internal amplification of 70. The efficacy of IGBA in suppressing the external interference is clearly demonstrated by comparing its noise performance to that of the ISFET counterpart. Among the various noise sources of an ISFET, the solid/liquid interfacial noise is poorly studied. A differential microelectrode cell is developed for characterizing this noise component by employing potentiometry and electrochemical impedance spectroscopy. With the cell, the measured noise of the TiN/electrolyte interface is found to be of thermal nature. The interfacial noise is further found to be comparable or larger than that of the state-of-the-art MOSFETs. Therefore, its influence cannot be overlooked for design of future ion sensors. To understand the solid/liquid interfacial noise, an electrochemical impedance model is developed based on the dynamic site-binding reactions of surface hydrogen ions with surface OH groups. The model incorporates both thermodynamic and kinetic properties of the binding reactions. By considering the distributed nature of the reaction energy barriers, the model can interpret the interfacial impedance with a constant-phase-element behavior. Since the model directly correlates the interfacial noise to the properties of the sensing surface, the dependencies of noise on the reaction rate constants and binding site density are systematically investigated.

In dieser Arbeit wird das epitaktische Wachstum von GaP/Si Heterostrukturen zur Herstellung von rauscharmen GaP/Si Nanodiodenarrays untersucht, wobei eine top-down Ätztechnik zur Herstellung der verwendeten Nanodiodenarrays genutzt wurde. Zur Untersuchung der gewachsenen Schichten wurden Röntgenstreuung (XRD), Rasterelektronenmikroskopie sowie die elektrische Charakterisierung mittels Strom-Spannungs und Kapazität-Spannungsmessungen verwendet. Zudem wurde die Grenzfläche zwischen epitaktischer Schicht und Substrat mittels Niederfrequenter Rauschspektroskopie (LFN) untersucht. Die GaP-Schichten wurden auf p-dotierten Si (100) Substraten mittels eines Riber-32P Gasquellen-Molekularstrahlepitaxiesystems gewachsen. Die Abhängigkeit der Oberflächenbeschaffenheit und Kristallqualität von denWachstumsbedingungen, wie der Wachstumstemperatur, wurden intensiv untersucht, um die Defektdichte zu minimieren. Dafür wurden nominal 500 nm dicke Heterostrukturschichten beiWachstumstemperaturen von 550 °C, 400 °C und 250 °C gewachsen, wobei 400 °C als die optimale Wachstumstemperatur bestimmt wurde. Trotzdem waren die erhaltenen Schichten aufgrund der hohen Versetzungsdichte von schlechter Qualität. Eine nur sehr geringe Qualitätsverbesserung konnte durch einen in situ durchgeführten thermischen Annealingschritt bei 500 °C für 10 Minuten erreicht werden. Daher wurde eine neue Annealingmethode vorgeschlagen, die in dieser Arbeit step-graded annealing (SGA) genannt wird. Bei dieser Methode wurde die Temperatur schrittweise von 400 °C auf 480 °C innerhalb von 90 Minuten erhöht. Dabei wurde die Oberfläche die gesamte Zeit mittels Reflexion hochenergetischer Elektronen (RHEED) untersucht. Die Oberflächenrekonstruktion, die während des Annealens mittels RHEED beobachtet wurde, zeigte schließlich eine große Verbesserung der Kristallqualität. Die Gitterparameter von GaP wurden mittels asymmetrischer XRD gemessen, wobei festgestellt wurde, dass sie exakt denen von Volumen-GaP entsprechen. Zudem wurde festgestellt, dass die GaP-Schicht automatisch n-dotiert ist und diodentypisches Gleichrichtungsverhalten aufweist. Interessante Informationen über Fallenzustände in den Heterostrukturfilmen konnten mittels LFN-Messungen gefunden werden. In einer nicht annealten Probe wurden beispielsweise zwei Fallenzustände im Bereich der Bandlücke festgestellt. In den mittels der SGA-Methode annealten Proben wurde hingegen ein rauscharmes und fallenfreies System erhalten. Anschließend wurde Elektronenstrahllithografie (EBL) zum Erstellen von Nanomustern auf der Oberfläche genutzt, die zur Herstellung von Nanodrähten genutzt werden sollen. Zur Optimierung der Elektronenstrahllithografie wurden dabei GaPSubstrate aufgrund der im Vergleich zu den epitaktischen Schichten besseren und glatteren Oberflächenstruktur genutzt. Dabei konnten in einer Goldschicht 200 nm große Löcher in einem Gitter mit hoher Dichte auf GaP erstellt und in die GaPSchicht übertragen werden. Die metallunterstütztes chemisches Ätzen (MacEtch) genannte Technik wurde kürzlich vorgeschlagen und eignet sich für die Herstellung von Nanodrähten. Die Anwendung zur Herstellung von Nanodrähten aus GaP war herausfordernd aufgrund bisher begrenzter Anwendung für III-V Halbleiter. Zur Optimierung der MacEtch Technik wurde zunächst wieder GaP-Substrat verwendet, um den Einfluss von Kristalldefekten und der Oberflächenrauigkeit auf die Ergebnisse zu minimieren. Genutzt wurde ein Gemisch aus Lösungen von HF/KMnO4 mit verschiedenen Konzentrationen. Mit den so bestimmten Prozessbedingungen konnten erfolgreich GaP Nanodrähte aus GaP-Epilayern hergestellt werden. GaP/Si Heteroübergangsnanodioden wurden anschließend unter Nutzung von Au-Ge/Ni Kontakten zu GaP-Schicht und Al/Ni Kontakten zum rückseitigen Si hergestellt. Die Transporteigenschaften des Nanodiodenarrays bestätigen die Möglichkeit, diese Arrays als elektronische NiederLärmbauelemente einzusetzen. / An epitaxial growth of GaP/Si heterostructures for the fabrication of low-noise GaP/Si nanodiode array based on nanowires is reported. The grown films were characterized using X-ray diffraction, scanning-electron microscopy, atomic-force microscopy and electrical measurements. Besides that, the interface between the epilayer and the substrate was deeply studied using a low-frequency noise (LFN) spectroscopy. The GaP epilayers were grown on p-type Si (100)substrates using gas-source molecular-beam epitaxy system. The dependence of surface morphology and crystal quality on the growth conditions was intensively investigated for minimizing the defects. The heterostructure films were grown at an optimal growth temperature of 400 °C and a nominal thickness of 500 nm. In order to improve the crystalline quality of the heterostructures, a new thermal annealing method was proposed, and referred to as step-graded annealing (SGA). In this method, the temperature was increased gradually to the annealing temperature to reduce the strain relaxation in the epilayers. A highly improvement in the crystal quality was confirmed using the SGA method. In addition, the epilayers were found to be n-type autodoped, and exhibited diode rectification behavior. Furthermore, the trap levels in the band gap, which were revealed via LFN measurements, were found to be suppressed in the annealed films. Thereafter, gold-mesh nanopatterns on the GaP surfaces were fabricated using an electron-beam lithography, as a step for the fabrication of GaP nanowires. A metal-assisted chemical etching technique with a mixture of HF:KMnO4 was carried out to fabricate GaP nanowires. GaP/Si heterojunction nanodiodes were then fabricated using an Au-Ge/Ni contact on the top of the GaP nanowires as well as an Al/Ni contact on the backside of Si. Transport properties of the nanodiode array confirmed the possibility of using the array as a low-frequency electronic device.

Cette thèse porte sur l’étude de transistor à effet tunnel (TFET) en FDSOI à géométries planaire et triple grille/nanofils. Nous rapportons pour la première fois des TFETs fabriqués par un processus basse température (600°C), qui est identique à celui utilisé pour l’intégration monolithique 3D. La méthode “Dual IDVDS” confirme que ces TFETs fonctionnent par effet tunnel et non pas par effet Schottky. Les résultats des mesures électriques montrent que l’abaissement de la température de fabrication de 1050°C (HT) à 600°C (LT) ne dégrade pas les propriétés des TFETs. Néanmoins, les dispositifs réalisés à basse température montrent un courant de drain et de fuite plus élevés et une tension de seuil différente par rapport aux HT TFETs. Ces phénomènes ne peuvent pas être expliqués par le mécanisme d’effet tunnel. Le courant de pompage de charges révèle une densité d’états d’interface plus grande à l’interface oxide/Si pour les dispositifs LT que dans les TFETs HT pour les zones actives étroites. Par ailleurs, une analyse de bruit basse fréquence permet de mieux comprendre la nature des pièges dans les TFETs LT et HT. Dans les TFETs réalisés à basse température nous avons mis en évidence une concentration en défauts non uniforme à l’interface oxide/Si et à la jonction tunnel qui cause un effet tunnel assisté par piège (TAT). Ce courant TAT est responsable de la dégradation de la pente sous seuil. Ce résultat montre la direction à suivre pour optimiser ces structures, à savoir une épitaxie de très haute qualité et une optimisation fine des jonctions. Finalement, nous avons proposé de nouvelles architectures innovatrices de transistors à effet tunnel. L’étude de simulation TCAD montre que l’extension de la jonction tunnel dans le canal augmente la surface de la région qui engendre le courant BTBT. Une fine couche dopée avec une dose ultra-haute en bore pourrait permettre l’obtention à la fois d’une pente sous le seuil faible et un fort courant ON pour le TFET. / This thesis presents a study of FDSOI Tunnel FETs (TFETs) from planar to trigate/nanowire structures. For the first time we report functional “Low-Temperature” (LT) TFETs fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration. “Dual IDVDS” method confirms that these devices are real TFETs and not Schottky FETs. Electrical characterization shows that LT TFETs performance is comparable with “High-Temperature” (HT) TFETs (1050°C). However, LT TFETs exhibit ON-current enhancement, OFF-current degradation and VTH shift with respect to HT TFETs that cannot be explained via BTBT mechanism. Charge pumping measurements reveal a higher defect density at the top silicon/oxide interface for geometries with narrow widths in LT than HT TFETs. In addition, low-frequency noise analyses shed some light on the nature of these defects. In LT TFETs, we determined a non-uniform distribution of defects at the top surface and also at the tunneling junction that causes trap-assisted tunneling (TAT). TAT is responsible of the current generation that degrades the subthreshold swing. This indicates the tight requirements for quality epitaxy growth and junction optimization in TFETs. Finally, we proposed novel TFET architectures. TCAD study shows that the extension of the source into the body region provides vertical BTBT and a larger tunneling surface. Ultra-thin heavily doped boron layers could allow the possibility to obtain simultaneously a good ON-current and sub-thermal subthreshold slope in TFETs.

O objetivo principal deste trabalho é o estudo de transistores MuGFETs de porta tripla de Corpo de canal tipo-n com e sem a aplicação da configuração DTMOS. Este estudo será realizado através de simulações numéricas tridimensionais e por caracterizações elétricas. A corrente de dreno, a transcondutância, a resistência, a tensão de limiar, a inclinação de sublimiar e a Redução da Barreira Induzida pelo Dreno (DIBL) serão analisadas em modo DTMOS e em configuração de polarização convencional. Importantes figuras de mérito para o desempenho analógico como transcondutância-sobre-corrente de dreno, a condutância de saída, a tensão Early e o ganho de tensão intrínseco serão estudados tanto experimentalmente como através de simulações numéricas tridimensionais para diferentes concentrações de dopantes no canal. Os resultados indicam que a configuração DTMOS apresenta as características elétricas superiores (4 e 10 %) e maior eficiência dos transistores. Além disso, os dispositivos DTMOS com alta concentração de dopantes no canal apresentaram um desempenho analógico muito melhor quando comparados ao transistor de porta tripla de Corpo em modo de operação convencional. O ruído de baixa frequência (LF) é pela primeira vez experimentalmente analisado na região linear e saturação. A origem do ruído é analisada de maneira a compreender os mecanismos físicos envolvidos neste tipo de ruído. As medições mostraram que os espectros do sinal dos dispositivos de porta tripla de Corpo e DTMOS são compostos por flutuações referentes ao número de portadores devido ao ruído flicker e por ondas de ruído de geração e recombinação no dielétrico de porta que se torna maior com o aumento da tensão de porta. No entanto, o principal fato desta análise é que o dispositivo DTMOS apresentou praticamente a mesma magnitude do ruído LF na região linear e de saturação que o dispositivo de Corpo. A energia de 60 MeV na fluência de p/1012 cm-2 de radiações de prótons é também estudada experimentalmente em termos das características elétricas, desempenho do analógico e ruído LF nos dispositivos de porta tripla de Corpo e DTMOS. Os resultados indicam que combinado com as suas melhores características elétricas e um ótimo desempenho analógico do DTMOS, faz o transistor de porta tripla de Corpo um candidato muito competitivo para aplicações analógicas em ruído de baixa frequência antes e depois da irradiação. A vantagem da técnica DTMOS em transistores de porta tripla em ambientes onde os dispositivos têm de suportar alta radiação é devido à menor penetração do campo de dreno que reduz o efeito das cargas induzidas pelo óxido de isolação (STI). Finalmente, o transistor de Corpo de porta tripla de canal tipo-n é experimentalmente estudado como célula de memória, isto é, como 1T-DRAM (Memória de Acesso Aleatório Dinâmico com 1 transistor). Para escrever e ler 1 é utilizado um modo de programação que utiliza o efeito do transistor bipolar parasitário (BJT) enquanto a polarização direta da junção do corpo e do dreno é usada para escrever 0. As correntes de leitura e escrita aumentam com o aumento da tensão do corpo (VB) porque as cargas induzidas pelo efeito BJT é armazenada dentro da aleta. Quando o corpo do transistor está flutuante, o dispositivo retém mais cargas dentro da sua aleta. Além disso, transistor de Corpo pode ser utilizado como 1T-DRAM com eletrodo de porta e substrato flutuando. Neste caso, o dispositivo funciona como um biristor (sem porta). / The main goal of this work is to investigate the n-channel MuGFETs (triple-gate) Bulk transistors with and without the application of DTMOS operation. This work will be done through three-dimensional numerical simulation and by electrical characterizations. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DTMOS mode and the standard biasing configuration. Important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional numerical simulations for different channel doping concentrations. The results indicate that the DTMOS configuration has superior electrical characteristics (4 e 10 %) and higher transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode. Low-Frequency (LF) noise is for the first time experimentally investigated in linear and saturation region. The origin of the noise will be analyzed in order to understand the physical mechanisms involved in this type of noise. Measurements showed that the signal spectra for Bulk and DTMOS are composed of number fluctuations related flicker noise with on top generation and recombination noise humps, which become more pronounced at higher gate voltage. However, the most important finding is the fact that DTMOS devices showed practically the same LF noise magnitude in linear and saturation region than standard Bulk device. Proton irradiation with energy of 60 MeV and fluence of p/1012 cm-2 is also experimentally studied in terms of electric characteristic, analog performance and the LF noise in Bulk and DTMOS triple gate devices. The results indicate that the combined of the better electrical characteristics and an excellent analog performance of DTMOS devices, makes it a very competitive candidate for low-noise RF analog applications before and after irradiation. The advantage of dynamic threshold voltage in triple gate transistors in environments where the devices have to withstand high-energy radiation is due to its lower drain electric field penetration that lowers the effect of the radiation-induced charges in the STI (shallow trench isolation) regions adjacent to the fin. Finally, the n-channel triple gate Bulk device is used for memory application, that is, 1T-DRAM (Dynamic Random Access Memory with 1 Transistor). Bipolar junction transistor (BJT) programming mode is used to write and read 1 while the forward biasing of the body-drain junction is used to write 0. The reading and writing current increases with increasing body bias (VB) because the load induced by the BJT effect is stored within the fin. When the body of the transistor is floating, the device retains more charge within its fin. In addition, transistor could also operate as 1T-DRAM with both gate and bulk contacts floating, which is similar to the biristor (gateless) behavior.

Le développement des technologies de communication et de l’information nécessite des composants semi-conducteurs ultrarapides et à faible niveau de bruit. Les transistors bipolaires à hétérojonction (TBH) sont des dispositifs qui visent des applications à hautes fréquences et qui peuvent satisfaire ces conditions. L’objet de cette thèse est l’étude expérimentale et la modélisation du bruit haute fréquence des TBH Si/SiGe:C (technologie STMicroelectronics) et InP/InGaAs (III-V Lab Alcatel-Thales).Accompagné d’un état de l’art des performances dynamiques des différentes technologies de TBH, le chapitre I rappelle brièvement le fonctionnement et la caractérisation des TBH en régime statique et dynamique. La première partie du chapitre II donne la description des deux types de TBH, avec l’analyse des performances dynamiques et statiques en fonction des variations technologiques de ceux-ci (composition de la base du TBH SiGe:C, réduction des dimensions latérales du TBH InGaAs). Avec l’aide d’une modélisation hydrodynamique, la seconde partie montre l’avantage d’une composition en germanium de 15-25% dans la base du TBH SiGe pour atteindre les meilleurs performances dynamiques. Le chapitre III synthétise des analyses statiques et dynamiques réalisées à basse température permettant de déterminer le poids relatif des temps de transit et des temps de charge dans la limitation des performances des TBH. L’analyse expérimentale et la modélisation analytique du bruit haute fréquence des deux types de TBH sont présentées en chapitre IV. La modélisation permet de mettre en évidence l’influence de la défocalisation du courant, de l’auto-échauffement, de la nature de l’hétérojonction base-émetteur sur le bruit haute fréquence. Une estimation des performances en bruit à basse température des deux types de TBH est obtenues avec les modèles électriques. / In order to fulfil the roadmap for the development of telecommunication and information technologies (TIC), low noise level and very fast semiconductor devices are required. Heterojunction bipolar transistor has demonstrated excellent high frequency performances and becomes a candidate to address TIC roadmap. This work deals with experimental analysis and high frequency noise modelling of Si/SiGe:C HBT (STMicroelectronics tech.) and InP/InGaAs HBT (III-V Lab Alcatel-Thales).Chapter I introduces the basic concepts of HBTs operation and the characterization at high-frequency. This chapter summarizes the high frequency performances of many state-of-the-art HBT technologies. The first part of chapter II describes the two HBT sets, with paying attention on the impact of the base composition (SiGe:C) or the lateral reduction of the device (InGaAs) on static and dynamic performances. Based on TCAD modelling, the second part shows that a 15-25% germanium composition profile in the base is able to reach highest dynamic performances. Chapter III summarizes the static and dynamic results at low temperature, giving a separation of the intrinsic transit times and charging times involved into the performance limitation. Chapter IV presents noise measurements and the derivation of high frequency noise analytical models. These models highlight the impact of the current crowding and the self-heating effects, and the influence of the base-emitter heterojunction on the high frequency noise. According to these models the high frequency noise performances are estimated at low temperature for both HBT technologies.

Les propriétés électriques et physiques de structures à faible dimensionalité ont été étudiées pour des applications dans des domaines divers comme l’électronique, les capteurs. La mesure du bruit bruit à basse fréquence est un outil très utile pour obtenir des informations relatives à la dynamique des porteurs, au piègeage des charges ou aux mécanismes de collision. Dans cette thèse, le transport électronique et le bruit basse fréquence mesurés dans des structures à faible dimensionnalité comme les dispositifs multi-grilles (FinFET, JLT…), les nanofils 3D en Si/SiGe, les nanotubes de carbone ou à base de graphène sont présentés. Pour les approches « top-down » et « bottom-up », l’impact du bruit est analysé en fonction de la dimensionalité, du type de conduction (volume vs surface), de la contrainte mécanique et de la présence de jonction metal-semiconducteur. / Electrical and physical properties of low-dimensional structures have been studied for the various applications such as electronics, sensors, and etc. Low-frequency noise measurement is also a useful technique to give more information for the carrier dynamics correlated to the oxide traps, channel defects, and scattering. In this thesis, the electrical transport and low-frequency noise of low-dimensional structure devices such as multi-gate structures (e.g. FinFETs and Junctionless FETs), 3-D stacked Si/SiGe nanowire FETs, carbon nanotubes, and graphene are presented. From the view point of top-down and bottom-up approaches, the impacts of LF noise are investigated according to the dimensionality, conduction mechanism (surface or volume conduction), strain technique, and metal-semiconductor junctions.

L'objectif de cette thèse est d'étudier la fiabilité et la cyclabilité des jonctions Tunnel magnétique pour mieux comprendre les mécanismes de dégradation et de claquage de la barrière. Une étude de l'endurance de la barrière MgO jusqu'au claquage électrique est présentée. Les échantillons ont été testés sous un mode impulsionnel. Par l'étude de l'effet de retard entre des impulsions successives, une durée de vie optimale des JTM est observée pour une valeur intermédiaire de retard entre les impulsions correspondant à un compromis optimal entre la densité moyenne de charge piégée dans la barrière et la modulation temporelle de charge. En outre, un modèle de piégeage / dépiégeage de charge a été développé qui appuie cette interprétation. L'étude souligne le rôle des pièges de charges dans le mécanisme de claquage de la barrière tunnel. Elle montre aussi que l'endurance extrêmement longue pourrait être obtenue en réduisant la densité des sites de piégeage d'électrons dans la barrière tunnel. Puis, une étude de l'endurance et le bruit basse fréquence a été dans les jonctionS CoFeB/MgO/CoFeB pour STT-MRAM ou TA-MRAM. Une corrélation a été observée et expliquée par la présence de sites de piégeage d'électrons dans la barrière de MgO et le rôle des phénomènes de charge/ décharge à la fois dans la fiabilité et la puissance du bruit en 1 / f électrique. Ces résultats prouvent que le test du bruit basse fréquence peut être utilisé comme une caractérisation prédictive de l'endurance. Enfin, en perspectives, des mesures complémentaires en été proposées pour développer plus le modèle de charge/décharge, une optimisation de la barrière pourrait ainsi être réaliser pour réduire le nombre des pièges de charge au sein de la barrière et par conséquent améliorer la fiabilité des jonctions Tunnel. / The thesis objective is to study the Magnetic Tunnel Junction reliability and cyclability to more understand the barrier breakdown mechanisms. An investigation of barrier endurance till electrical breakdown in MgO-based magnetic tunnel junctions (MTJs) is presented. Samples were tested under pulsed electrical stress. By studying the effect of delay between successive pulses, an optimum endurance of MTJs is observed for an intermediate value of delay between pulses corresponding to an optimum trade-off between the average density of charge trapped in the barrier and the amplitude of its time-modulation at each voltage pulse. Furthermore, a charge trapping/detrapping model was developed which support this interpretation. The study emphasizes the role of electron trapping/detrapping mechanisms on the tunnel barrier reliability. It also shows that extremely long endurance could be obtained in MTJs by reducing the density of electron trapping sites in the tunnel barrier. Then the write endurance and the 1/f noise of electrical origin were characterized in CoFeB/MgO/CoFeB MTJ for STT-MRAM or TA-MRAM. A correlation was observed and explained by the presence of electron trapping sites in the MgO barrier and the role of electron trapping/detrapping phenomena in both the MTJ reliability and its 1/f electrical noise power. These results suggest that 1/f noise could be used as a predictive characterization of the MTJ endurance. Finally, as thesis perspectives, some complement measurements were proposed to further investigate this model and an optimization of MgO barrier which could be carried out to reduce the density of these trapping sites was presented to ameliorate the MTJs reliability.

Parmi les architectures candidates pour les générations sub-22nm figurent les transistors sur silicium sur isolant (SOI). A cette échelle, les composants doivent intégrer des films isolants enterrés (BOX) et des canaux de conduction (Body) ultra-minces. A ceci s'ajoute l'utilisation d'empilements de grille avancés (diélectriques à haute permittivité / métal de grille) et une ingénierie de la contrainte mécanique avec l'utilisation d'alliages SiGe pour le canal des transistors de type P. La mise au point d'une telle technologie demande qu'on soit capable d'extraire de façon non destructive et avec précision la qualité du transport électronique et des interfaces, ainsi que les valeurs des paramètres physiques (dimensions et dopages), qui sont obtenues effectivement en fin de fabrication. Des techniques d'extraction de paramètres ont été développées au cours du temps. L'objectif de cette thèse est de reconsidérer et de faire évoluer ces techniques pour les adapter aux épaisseurs extrêmement réduites des composants étudiés. Elle combine mesures approfondies et modélisation en support. Parmi les résultats originaux obtenus au cours de cette thèse, citons notamment l'adaptation de la méthode split CV complète qui permet désormais d'extraire les paramètres caractérisant l'ensemble de l'empilement SOI, depuis le substrat et son dopage jusqu'à la grille, ainsi qu'une analyse extrêmement détaillée du transport grâce à des mesures en régime de couplage grille arrière à température variable ou l'exploitation de la magnétorésistance de canal depuis le régime linéaire jusqu'en saturation. Le mémoire se termine par une analyse détaillée du bruit basse fréquence. / Silicon on insulator (SOI) transistors are among the best candidates for sub-22nm technology nodes. At this scale, the devices integrate extremely thin buried oxide layers (BOX) and body. They also integrate advanced high-k dielectric / metal gate stacks and strain engineering is used to improve transport properties with, for instance, the use of SiGe alloys in the channel of p-type MOS transistors. The optimization of such a technology requires precise and non-destructive experimental techniques able to provide information about the quality of electron transport and interface quality, as well as about the real values of physical parameters (dimensions and doping level) at the end of the process. Techniques for parameter extraction from electrical characteristics have been developed over time. The aim of this thesis work is to reconsider these methods and to further develop them to account for the extremely small dimensions used for sub-22nm SOI generations. The work is based on extended characterization and modelling in support. Among the original results obtained during this thesis, special notice should be put on the adaptation of the complete split CV method which is now able to extract the characteristic parameters for the entire stack, from the substrate and its doping level to the gate stack, as well as an extremely detailed analysis of electron transport based on low temperature characterization in back-gate electrostatic coupling conditions or the exploitation of channel magnetoresistance from the linear regime of operation to saturation. Finally, a detailed analysis of low-frequency noise closes this study.

O objetivo principal deste trabalho é o estudo de transistores MuGFETs de porta tripla de Corpo de canal tipo-n com e sem a aplicação da configuração DTMOS. Este estudo será realizado através de simulações numéricas tridimensionais e por caracterizações elétricas. A corrente de dreno, a transcondutância, a resistência, a tensão de limiar, a inclinação de sublimiar e a Redução da Barreira Induzida pelo Dreno (DIBL) serão analisadas em modo DTMOS e em configuração de polarização convencional. Importantes figuras de mérito para o desempenho analógico como transcondutância-sobre-corrente de dreno, a condutância de saída, a tensão Early e o ganho de tensão intrínseco serão estudados tanto experimentalmente como através de simulações numéricas tridimensionais para diferentes concentrações de dopantes no canal. Os resultados indicam que a configuração DTMOS apresenta as características elétricas superiores (4 e 10 %) e maior eficiência dos transistores. Além disso, os dispositivos DTMOS com alta concentração de dopantes no canal apresentaram um desempenho analógico muito melhor quando comparados ao transistor de porta tripla de Corpo em modo de operação convencional. O ruído de baixa frequência (LF) é pela primeira vez experimentalmente analisado na região linear e saturação. A origem do ruído é analisada de maneira a compreender os mecanismos físicos envolvidos neste tipo de ruído. As medições mostraram que os espectros do sinal dos dispositivos de porta tripla de Corpo e DTMOS são compostos por flutuações referentes ao número de portadores devido ao ruído flicker e por ondas de ruído de geração e recombinação no dielétrico de porta que se torna maior com o aumento da tensão de porta. No entanto, o principal fato desta análise é que o dispositivo DTMOS apresentou praticamente a mesma magnitude do ruído LF na região linear e de saturação que o dispositivo de Corpo. A energia de 60 MeV na fluência de p/1012 cm-2 de radiações de prótons é também estudada experimentalmente em termos das características elétricas, desempenho do analógico e ruído LF nos dispositivos de porta tripla de Corpo e DTMOS. Os resultados indicam que combinado com as suas melhores características elétricas e um ótimo desempenho analógico do DTMOS, faz o transistor de porta tripla de Corpo um candidato muito competitivo para aplicações analógicas em ruído de baixa frequência antes e depois da irradiação. A vantagem da técnica DTMOS em transistores de porta tripla em ambientes onde os dispositivos têm de suportar alta radiação é devido à menor penetração do campo de dreno que reduz o efeito das cargas induzidas pelo óxido de isolação (STI). Finalmente, o transistor de Corpo de porta tripla de canal tipo-n é experimentalmente estudado como célula de memória, isto é, como 1T-DRAM (Memória de Acesso Aleatório Dinâmico com 1 transistor). Para escrever e ler 1 é utilizado um modo de programação que utiliza o efeito do transistor bipolar parasitário (BJT) enquanto a polarização direta da junção do corpo e do dreno é usada para escrever 0. As correntes de leitura e escrita aumentam com o aumento da tensão do corpo (VB) porque as cargas induzidas pelo efeito BJT é armazenada dentro da aleta. Quando o corpo do transistor está flutuante, o dispositivo retém mais cargas dentro da sua aleta. Além disso, transistor de Corpo pode ser utilizado como 1T-DRAM com eletrodo de porta e substrato flutuando. Neste caso, o dispositivo funciona como um biristor (sem porta). / The main goal of this work is to investigate the n-channel MuGFETs (triple-gate) Bulk transistors with and without the application of DTMOS operation. This work will be done through three-dimensional numerical simulation and by electrical characterizations. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DTMOS mode and the standard biasing configuration. Important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional numerical simulations for different channel doping concentrations. The results indicate that the DTMOS configuration has superior electrical characteristics (4 e 10 %) and higher transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode. Low-Frequency (LF) noise is for the first time experimentally investigated in linear and saturation region. The origin of the noise will be analyzed in order to understand the physical mechanisms involved in this type of noise. Measurements showed that the signal spectra for Bulk and DTMOS are composed of number fluctuations related flicker noise with on top generation and recombination noise humps, which become more pronounced at higher gate voltage. However, the most important finding is the fact that DTMOS devices showed practically the same LF noise magnitude in linear and saturation region than standard Bulk device. Proton irradiation with energy of 60 MeV and fluence of p/1012 cm-2 is also experimentally studied in terms of electric characteristic, analog performance and the LF noise in Bulk and DTMOS triple gate devices. The results indicate that the combined of the better electrical characteristics and an excellent analog performance of DTMOS devices, makes it a very competitive candidate for low-noise RF analog applications before and after irradiation. The advantage of dynamic threshold voltage in triple gate transistors in environments where the devices have to withstand high-energy radiation is due to its lower drain electric field penetration that lowers the effect of the radiation-induced charges in the STI (shallow trench isolation) regions adjacent to the fin. Finally, the n-channel triple gate Bulk device is used for memory application, that is, 1T-DRAM (Dynamic Random Access Memory with 1 Transistor). Bipolar junction transistor (BJT) programming mode is used to write and read 1 while the forward biasing of the body-drain junction is used to write 0. The reading and writing current increases with increasing body bias (VB) because the load induced by the BJT effect is stored within the fin. When the body of the transistor is floating, the device retains more charge within its fin. In addition, transistor could also operate as 1T-DRAM with both gate and bulk contacts floating, which is similar to the biristor (gateless) behavior.

Kadmium telurid je velmi důležitý materiál jak základního, tak i aplikovaného výzkumu. Je to dáno zejména jeho výhodnými elektronickými, optickými a strukturními vlastnostmi, které ho předurčují pro náročné technické aplikace. Dnes se hlavně používá pro jeho vysoké rozlišení k detekci a X-záření. Hlavní výhodou detektorů na bázi CdTe je, že nepotřebují chlazení a mohou spolehlivě fungovat i při pokojové teplotě. To způsobuje efektivnější interakce fotonů než je tomu u Si nebo jiných polovodičových materiálů. Obsahem této práce byla analýza a interpretace výsledků získaných studiem šumových a transportních charakteristik CdTe vzorků. Měření ukázaly že odpor homogenní části CdTe krystalů mírně klesá při připojení elektrického pole na vzorku. Při změně teploty navíc dochází k odlišné reakci u CdTe typu p a n. Právě těmto efektům je v práci věnována pozornost. Pomocí šumové spektroskopie bylo zjištěno, že při nízkých frekvencích je u vzorků dominantní šum typu 1/f, zatímco při vyšších frekvencích je sledován generačně-rekombinační šum a tepelný šum. Všechny měřené vzorky vykazovaly mnohem vyšší hodnotu šumu na nízkých frekvencích než udává Hoogeova rovnice. Byly nalezeny a popsány zdroje nadbytečného šumu.