Une utilisation intelligente de l’espace Hertzien sera nécessaire pour permettre aunombre croissant d’objets sans-fil connectés de communiquer dans le même espace de propagation.Ces travaux de thèse proposent une architecture d’émetteur radiofréquence flexible, faiblecoût et faible consommation, en rupture avec les techniques conventionnelles. Cet émetteur estfondé sur un encodage de la dérivée du signal à générer, ce qui permet de réduire le coût énergétiquede la conversion de l’information. Un convertisseur numérique analogique compatibleavec cette architecture est présenté et ses performances sont évaluées dans le cadre de la générationde signaux radiofréquence. Les résultats de mesures obtenus avec un prototype réalisé entechnologie CMOS 65 nm apporte la preuve du concept. / The increasing density of wireless devices and the associated communication flowssharing the same air interface will require a smart and agile use of frequency resources. Thisthesis proposes a flexible, low cost and low power disruptive transmitter architecture. It usesa differentiating coding scheme which leverages a mathematical and technological reduction ofthe energy cost of information conversion. The design of a DAC suited to this architecture isdeveloped and its performances are assessed toward RF signal generation. The measurementsof a demonstrator designed in 65 nm CMOS technology bring a proof of concept.

<p>The problem of fault diagnosis consists of detecting and isolating faults present in a system. As technical systems become more and more complex and the demands for safety, reliability and environmental friendliness are rising, fault diagnosis is becoming increasingly important. One example is automotive systems, where fault diagnosis is a necessity for low emissions, high safety, high vehicle uptime, and efficient repair and maintenance.</p><p>One approach to fault diagnosis, providing potentially good performance and in which the need for additional hardware is minimal, is model-based fault diagnosis with residuals. A residual is a signal that is zero when the system under diagnosis is fault-free, and non-zero when particular faults are present in the system. Residuals are typically generated by using a mathematical model of the system and measurements from sensors and actuators. This process is referred to as residual generation.</p><p>The main contributions in this thesis are two novel methods for residual generation. In both methods, systems described by Differential-Algebraic Equation (DAE) models are considered. Such models appear in a large class of technical systems, for example automotive systems. The first method consider observer-based residual generation for linear DAE-models. This method places no restrictions on the model, such as e.g. observability or regularity, in comparison with other previous methods. If the faults of interest can be detected in the system, the output from the design method is a residual generator, in state-space form, that is sensitive to the faults of interest. The method is iterative and relies on constant matrix operations, such as e.g. null-space calculations and equivalence transformations.</p><p>In the second method, non-linear DAE-models are considered. The proposed method belongs to a class of methods, in this thesis referred to as sequential residual generation, which has shown to be successful for real applications. This method enables simultaneous use of integral and derivative causality, and is able to handle equation sets corresponding to algebraic and differential loops in a systematic manner. It relies on a formal framework for computing unknown variables in the model according to a computation sequence, in which the analytical properties of the equations in the model as well as the available tools for equation solving are taken into account. The method is successfully applied to complex models of an automotive diesel engine and a hydraulic braking system.</p>

<p>Multiplication is an important part of real-time system applications. Various hardware parallel multipliers used in such applications have been proposed. However, when the operand sizes of the multipliers and the process technology need to be changed, the existing multipliers have to be redesigned. </p><p>From the point of library cell reuse, this master thesis work aims at developing a module generator for parallel multipliers with the help of software programs. This generator can be used to create the gate-level schematic for fixed point two's complement number multipliers. Based on the generated schematic, the entire multiplier can be implemented by small manual intervention. This feature can reduce the time of chip design. </p><p>The design phases consist of the logic, circuit and physical designs. The logic design includes gate-level schematic generation with C and SKILL programs and structural VHDL-code descriptions as well as validation. The circuit and physical design are custom in Cadence and the routing uses automatic place and route tools. </p><p>To demonstrate the design method, an 18 by 18-bit modified Booth recoded multiplier was implemented in 0.18 µm CMOS process with a supply voltage of 1.2 V and simulated using simulator (Spectre). The number of integrated transistors is 13000 and the active area is 85000 µm². The postlayout simulation shows the critical path with a delay of 17 ns.</p>

<p>Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. </p><p>The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. </p><p>The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.</p>

<p>The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. </p><p>Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. </p><p>The testcases are selected to represent the FPGA designs made at Ericsson Microwave Systems. The testcases show that Xilinx System Generator can be used to effectivly implement a model made in Simulink in a FPGA from Xilinx. The result of the implementation is comparable to the implementation of VHDL code written by hand. </p><p>The use of tools for implementation of a model in hardware cause change in the design methods used at Ericsson Microwave Systems. The higher level of abstraction introduced by System Generator results in the design decisions made at system level having a higher impact on the final realization.</p>

<p>The purpose of this report is to implement and evaluate parts of the simulation software used in the SoCBUS project. In order to complete and evaluate the entire software package, a traffic model and a stimuli generator must be implemented. They are implemented and evaluated together with the entire simulator software. The purpose of the Traffic model is to model communication traffic as good and descriptive as possible. The output of the Traffic model is called a test case, which works as input for the Stimuli generator. The Stimuli generator computes and creates an event list for the Simulator. This report will investigate and motivate the presented traffic model and stimuli generator in detail. The simulator software is then tested with two separate test cases in order to investigate if the simulator software works properly. The results are promising and the simulator software behaves as expected.</p>

<p>In this work, an existing generator for layout of Static Random Access Memory (SRAM) is improved. The tool is completed with a block decoder, which was missing when the thesis started. A feature of generating schematic files is also added. The schematics are important to get a better overview, to test parts properly, and enable Layout versus Schematics (LVS) checks.</p><p>The main focus of this thesis work is to implement and evaluate a new SRAM cell, called Zero Aware Asymmetric SRAM cell. This cell saves major power when zeros are stored. Furthermore the pull-up circuit is modified to be less power consuming. Other parts are also modified to fit the new memory cell.</p><p>Several minor flaws are corrected in the layout generator. It does still not produce a complete memory without manual interventions, but it does at least create all parts with one command. Several tests, including Design Rule Checks (DRC) and LVS checks, are carried out both on minor and larger parts. Development of documentation that makes it easier for users and developers to use and understand the tool is initiated.</p>

<p>This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem.</p><p>The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.</p>

<p>System-on-Chip is increasingly built using ASIP(Application  Specific Instruction set Processor) due to the flexibility and efficiency obtained from ASIPs. NoGAP (Novel Generator of Accelerator and Processor framework) is an innovative approach for  ASIP design, which provides the advantage of both ADL (Architecture  Description Language) and HDL (Hardware Description Language) to the  designer.</p><p>For the processors designed using NoGAP, software tools need to be automatically generated, to aid the  designer in programming and verifying the processor. As part of the master thesis work, we have developed two generators namely Assembler generator and Cycle-Accurate Simulator generator for NoGAP using C++. The Assembler generator automatically generates an assembler, which is used to convert the assembly code written by a programmer into relocatable binary code. The Cycle-Accurate Simulator generator automatically generates a cycle-accurate simulator to model the behavior of the designed processor. Both these generators are static, and can be used to generate the tools for any processor created using NoGAP.</p><p>In this report, we have detailed the concepts behind the generators,and the implementation details of the generators. We have listed the results obtained from running assembler and cycle-accurate simulator on a test processor created using NoGAP.</p> / NoGAP

<p>In this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technologys, automating the simulation process and the creation of the workflow for the energy model.</p><p>One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layout is suggested which saves a lot of area and power. The technology that is used to create the RAM generator is old and a suitable way to port it to newer technology has also been found.</p><p>To create an energy model one has to simulate a lot of memories with a lot of data. This cannot be done in the traditional way of simulating circuits using the GUI. Hence an automation procedure has been suggested which can be made to work to create energy models by simulating the memories comprehensively.</p><p>Finally, basic ground work has been initiated by creating a workflow for the creation of the energy model.</p>