Le travail de doctorat réalisé s'attache à étudier les nouveaux types d'interconnexions comme les TSV (Through Silicon Via), les lignes de redistribution (RDL) et les piliers de cuivre (Cu-Pillar) présentes dans le domaine de l'intégration 3D en microélectronique avancée, par exemple pour des applications de type « imager » où une puce « capteur optique » est empilée sur une puce « processeur ». Afin de comprendre et quantifier le comportement électrique de ces nouveaux composants d'interconnexion, une première problématique de la thèse s'articulait autour de la caractérisation électrique, sur une très large bande de fréquence (10 MHz - 60 GHz) de ces éléments, enfouis dans leurs environnements complexes d'intégration, en particulier avec l'analyse de l'impact des pertes dans les substrats de silicium dans une gamme de conductivités allant de très faible (0 S/m) à très forte (10 000 S/m). Par la suite, une nouvelle problématique prend alors naissance sur la nécessité de développer des modèles mathématiques permettant de prédire le comportement électrique des interconnexions 3D. Les modèles électriques développés doivent tenir compte des pertes, des couplages ainsi que de certains phénomènes liés à la montée en fréquence (courants de Foucault) en fonction des caractéristiques matériaux, des dimensions et des architectures (haute à faible densité d'intégration). Enfin, à partir des modèles développés, une dernière partie propose une étude sur les stratégies de routage dans les empilements 3D de puces à partir d'une analyse sur l'intégrité de signaux. En opposant différents environnements, débit de signaux binaires ou dimensions des TSV et des RDL des conclusions émergent sur les stratégies à adopter pour améliorer les performances des circuits conçus en intégration 3D. / The aim of this doctoral work is to study the new kind of interconnections like TSV (Through Silicon Via), redistribution lines (RDL) and copper pillars used in 3D integration context in advanced microelectronic components. An example of 3D integration application could be an imager designed by staking an optical sensor chip upon a processor chip. In order to understand and quantify the electrical behaviour of these new interconnection components, the first issue was about electrical characterization in a very wide frequency band (10 MHz - 60 GHz) of these elements, buried in their complex environment, in particular with the analysis of the silicon substrate loss impact which can be found in a wide band of conductivities from very low (0 S/m) to very high (10 000 S/m). Subsequently, a second issue appears from the need to develop mathematical models to predict the electrical behavior of 3D interconnects. The developed models have to take into account losses, coupling effects and some phenomena appearing with the rise of frequency (eddy currents) according to material characteristics, dimensions and architecture (from high to low density of integration). Finally, based on developed models, the last part presents a study on routing strategies in the 3D stacking chip from the analysis of signal integrity. By contrasting various environments, binary signals flow or dimensions of TSV and RDL, conclusions emerge on the best strategies to use to improve performances of circuits designed in 3D integration.

Ces dernières années, l’évolution de la taille des circuits intégrés a été dirigée par la loi de Moore conduisant à des noeuds technologiques de 22 nm et en-deçà. Cependant, les problématiques de performances, de taille et de coût des composants rendent cette conjecture difficile à suivre. La tendance de diversification appelée « More than Moore » consiste à intégrer des fonctions analogiques avec des technologies CMOS dans le but d’optimiser les coûts.L'une de ses technologies clés est le TSV, qui maintient le contact entre deux niveaux de composants. Leurs facteurs de forme devenant de plus en plus élevés, les techniques de dépôts standards par iPVD sont proches de leurs limites. De plus, les méthodes de caractérisation usuelles ne sont pas adaptées à ces structures.La première partie de cette thèse sera dédiée au développement des procédés de dépôt de la barrière de diffusion du cuivre par MOCVD à basse température pour s’adapter aux divers schémas d'intégration de type via middle et via last. La deuxième partie sera consacrée à l’élaboration des protocoles avancés de caractérisation des films dans ces structures afin d’étudier leurs comportements en intégration. / For the past years, Moore’s law has pointed mainstream microelectronics, driving integrated circuits down to 22 nm and below. Yet, performance, dimension and cost issues make it difficult to follow the trend. Integrating analog functions into CMOS-based technologies enables cost-optimized systems solutions. These diversified tendencies are known as “More than Moore”. One of the key technologies of this trend is the TSV, which maintains the contact between two components.The increasing aspect ratio of via made it critical to obtain a continuous, conformal coverage of the copper diffusion barrier layer using iPVD.In the first part of this thesis, a promising deposition technique by MOCVD has been developed at low temperature to fulfill various integration schemes including via last and via middle processes.Characterizations of the behavior of these materials in the TSV then became a great challenge in order to handle the integration protocol. Working at theses scales makes standard methods limited to evaluate the intrinsic properties inside the TSV. In the second part, the implementations of advanced characterization into these structures were carried out.

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Future high-capacity wireless communications will extensively use the broad bands still available millimeter-wave frequencies. Channels with bandwidth broader than those in use today will guarantee enhanced data-rate and reduced latency performance. The recent progress of integrated-circuit semiconductor technologies finally allowed the design of reliable electronics operating at millimeter-wave frequencies. On top, advanced Fully Depleted Silicon On Insulator (FD-SOI) Complementary Metal Oxide Semiconductor (CMOS) and Silicon Germanium (SiGe) Bipolar CMOS (BiCMOS) processes enabled to co-integrate large digital blocks with frontends operating at tens or hundreds of GHz. The current under-deployment fifth-generation mobile-communication standard (5G) takes advantage of these advancements, massively exploiting the frequency bands from 24 GHz to 100 GHz. Furthermore, besides enlarging the channel bandwidth, improvements of the signal-to-noise power ratio (SNR) at the receiver input, combined with Multiple-Input Multiple-Output (MIMO) techniques provide an additional boost to the communication data-rate. Both approaches require arrays of antennas, plus electronic beam-steering which becomes essential in the case of moving transmitting-receiving pairs. Finally, social, economic, historical, and technological trends indicate that future wireless standards will require data-rates, latencies, and density of served users per square kilometer well beyond those offered by the 5G. Envisioned to be deployed towards the end of this decade, the six mobile communication standard (6G) will win future challenges thanks to the very ultra-broad bands available from 100 GHz until the tens of THz. Basic research is hence needed to address the open challenges necessary to reach the goals of future wireless communication systems, such as bandwidth and frequency operation factor-10 increase or power consumption reduction against the actual state of the art. This Habilitation thesis proposes circuit theory and concepts up to feasibility study of circuit implementation and experimental characterization in the laboratory of transceiver electronics for future high-capacity communications useful for the knowledge gain necessary for the conception of future communication systems. In detail, basic scientific research to understand the operation of millimeter-wave communication circuits implemented in 22 nm FD-SOI CMOS and 130 nm SiGe BiCMOS technologies has been performed.

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This study examines the intellectual capital (IC) disclosure practices in the annual reports of 100 listed UK firms selected from sectors considered to be IC-intensive. It also investigates the possible determinants of such disclosure practices from the three perspectives of corporate governance structure, company characteristics and market factors. IC disclosures were captured using content analysis, and were measured by a disclosure index, supported by word count and percentage of word count metrics to assess the variety, volume and focus of IC disclosure respectively, at both overall and subcategory levels. The presentational formats and locations of IC disclosures were also recorded. The results indicate that the UK firms sampled provide considerable IC information in their annual reports, mainly in text form, with popular use of numerical information, while the use of graphs and pictures for many IC elements remains low. The distribution of IC disclosures, captured in three categories, varies by the three measures of disclosure applied. IC information was found in virtually all sections of the annual report and was most concentrated in the Operating and Financial Review section. IC terms typically used in the academic literature do not feature in the sampled annual reports. The results of the statistical analyses based on the three measures of IC disclosure indicate significant associations with a number of corporate governance factors (i.e. board composition, share concentration, audit committee size and frequency of meeting, board directors' shareholding, audit committee directors' shareholding, and board directors with cross-directorships), company characteristics (i.e. firm size, profitability, and listing age), and market factors (i.e. 'hidden value', share price volatility, share turnover, and multiple listing). These findings offer support for a number of theories, such as information asymmetry, agency and signalling theory. The influence of these explanatory factors on human, structural and relational capital disclosures, based on all three disclosure measure metrics, as well as on the format of IC disclosure, was also explored. The study also finds that its IC framework is more effective than a less detailed framework used in prior studies for the purpose of examining IC disclosure practice and its determinants. The study contributes to the further advancement of the state of knowledge in relation to IC disclosure both empirically and methodologically. It provides information users, preparers, regulatory bodies and academics with a state-of-the-art understanding of IC disclosure practices in the annual report. The transparent content analysis process enables future replication and comparison of results. The rigorous measurements of IC disclosure, the greater specificity of disclosure about the location and presentational format, and the more detailed IC research framework can be usefully applied by other studies. By examining the relationship between explanatory factors and IC disclosure, it helps shareholders and other groups of information users as well as the regulatory bodies to identify factors that may encourage IC disclosure in the annual report.

After undergoing a study about current engine modelling and mapping approaches as well as the engine modelling requirements for different applications, a major problem found to be present is the extensive and time consuming mapping procedure that every engine has to go through so that all control parameters can be derived from experimental data. To improve this, a cycle-by-cycle modelling approach has been chosen to mathematically represent reciprocating engines starting by a complete dynamics crankshaft mechanism model which forms the base of the complete engine model. This system is modelled taking into account the possibility of a piston pin offset on the mechanism. The derived Valvetrain model is capable of representing a variable valve lift and phasing Valvetrain which can be used while modelling most modern engines. A butterfly type throttle area model is derived as well as its rate of change which is believed to be a key variable for transient engine control. In addition, an approximation throttle model is formulated aiming at real-time applications. Furthermore, the engine inertia is presented as a mathematical model able to be used for any engine. A spark ignition engine simulation (SIES) framework was developed in MATLAB SIMULINK to form the base of a complete high fidelity cycle-by-cycle simulation model with its major target to provide an environment for virtual engine mapping procedures. Some experimental measurements from an actual engine are still required to parameterise the model, which is the reason an engine mapping (EngMap) framework has been developed in LabVIEW, It is shown that all the moving engine components can be represented by a single cyclic variable which can be used for flow model development.

In this thesis Graphit-iC™, an amorphous carbon coating developed by Teer Coatings Ltd. was modified and deposited onto CoCr and WHMWPE substrates in order to improve the wear properties. It was identified that depositing a hard coating onto soft substrate would cause high stresses and lead to coating delamination. Consequently the polyethylene substrates were ion implanted with nitrogen to reduce the hardness differential at the substrate-coating boundary. The coating was characterised using a pin on disc method in order to determine wear and friction. Hardness and fatigue was characterised using nano-indentation and the coating adhesion was measured using scratch testing. Application of the coatings resulted in a significant reduction in wear. Wear factors as low as 3.65x10¯18m³/Nm were achieved for coated CoCr substrates compared to 3.53x10¯15m³/Nm reported in the literature for uncoated CoCr. The coating resulted in friction coefficients between 0.12 and 0.19 with hardness ranging from 6.65 and 15.63GPa. Similarly coating UHMWPE resulted in a reduction in the wear factor to less than 9.6x10¯17m³/Nm. It was concluded that the deposition of amorphous carbon coatings can improve wear of hip joint prostheses, although consideration must be made for the adhesion of the coating to the substrate so that it does not contribute to an early failure of the device. Improved adhesion can be achieved by reducing the hardness differential between the coating and adhesion, either through softening the coating or by using interlayers.

我國立法院於民國94年12月9日正式三讀通過「所得稅基本稅額條例」，使得最低稅負制度正式成為國人熱門討論的話題。我國實施最低稅負制的起因主要在於立法院有立法委員批評我國高科技產業公司如台積電、聯電等，近幾年來所繳的營利事業所得稅遠低於一般社會大眾的認知；再加上財政部公佈了全國前40位最富有的納稅義務人，民眾赫然發現其中竟然有人免繳所得稅，這一連串對於所得稅及租稅公平有關的負面新聞接連公佈後，促成主管機關認真檢討及思考現行的所得稅制是否有需要修改的必要性。 由於高科技產業所享有的龐大租稅優惠及利益一向為社會投資大眾所熟知，而IC設計產業因為是我國政府目前重點扶植的產業之ㄧ，在資本市場的股價表現上來看，該類產業的股票本益比也往往較其他科技產業來得高。所以投資人將會特別注意最低稅負制實施後是否會對於IC設計產業在營利事業所得稅及公司的投資決策、財務操作等方面造成一些不良的衝擊與影響。 本研究希望透過蒐集上市櫃及興櫃掛牌的IC設計產業公司從民國93年度至民國96年度間的各項財務、稅務相關資料，利用統計進行相關分析，探討上市櫃及興櫃掛牌的IC設計產業公司在最低稅負制實施後，是否對於其所得稅負擔與財務、投資決策等方面造成重大的影響；並進一步評估最低稅負制度是否能達成主管機關預期的目標及促進租稅公平的效果。