<p>Detta examensarbete undersöker effekter av en elektromagnetisk puls på IC-kretsar.</p><p>För att kunna utvärdera inverkan har ett testobjekt, innehållande komponenter som skall testas, konstruerats. Detta testobjekt består av batteri, en enkel komponent och last. Ett pulsaggregat och en antenn användes för att generera de elektromagnetiska pulser som testobjektet utsattes för. Resultaten visar att inverkan på de testade komponenterna är möjlig. Inverkan visade sig vara beroende av bl.a. avståndet till antennen och den tid som testobjektet utsätts för störning. Störning har också utförts vid olika polariseringar.</p><p>Ett mål var att kunna jämföra en elektromagnetisk störning via en antenn med en trådbunden störning, där pulsen genererats från samma pulsaggregat. Försöken att utföra trådbunden störning av testobjektet misslyckades då pulsen inte var tillräckligt bra.</p><p>Detta examensarbete är en del av en artikel, <em>High Power Ultra Wide Band </em>and <em>Vircator Source-Victim Experiment</em>, som presenterades vid konferensen EMC Europe 2008.</p> / <p>This paper studies the effects of an electromagnetic pulse on IC-circuits. A DUT (device under test) has been constructed so that the effects of the pulse can be evaluated. The DUT consists of a battery, a load and the component, which is to be tested. A high voltage power supply and an antenna were used to generate the pulses that the DUT were exposed to. The results show that the effects were dependent on, among others, the distance between the antenna and the DUT and the time during which the DUT was exposed to the pulse. The DUT has also been exposed to different polarisations of the pulse.</p><p>One of the objectives of the study was to compare the difference between a pulse from an antenna and from a wire. This was to be done with the same high voltage power supply. Attempts to use a wire, for injecting the pulse, were unsuccessful since the damped pulse was not satisfying.</p><p>This paper is a part of a paper, <em>High Power Ultra Wide Band</em> and <em>Vircator Source-Victim Experiment</em>, that was presented at the conference EMC Europe 2008.</p>

近年來，企業併購風吹向科技業。在台灣素來引以為傲而且在全球產業鍊中佔有一席之地的IC設計產業也不可避免的帶來併購的機會。在過去一年以來，數個美國中大型IC設計公司紛至台灣探路，透過併購來完善其技術組合，或者與台灣ODM之間拉近關係。而台灣自己的IC設計公司也同時透過併購的過程加速企業的成長與產品的佈局。 本研究會先以一般的企業併購理論來分析IC設計產業，並且在兩家大型IC設計公司Marvell與聯發科成功的併購成長案例中來討論在IC設計產業裏，因產業的特殊性而顯得特別重要的併購成功因素。 本研究分析出八項併購的成功因素: 1.高階人員參與策略規劃 2.目標市場的選擇 3.購併的財務規劃 4.購併價值評估 5.併購後之人才資源管理 6.購併後之整合管理 7.矽智財之管理 8.委外生產之議價能力 其中將特別強調矽智財之管理與委外生產之議價力。這兩項因素是其他產業沒有著墨的地方，但是在IC設計產業卻顯得重要。而且也是文中提到的兩家IC設計公司對於併購能夠成功的獨到法則。 很多大型企業都有併購的經驗，併購成功的比率在美國相關的報導裏約只有百分之二十。透過這一次的分析，本研究也希望能讓業界先進們在以後的併購決策中有多一層的考量，在企業進行併購活動時，能掌握有較高的成功機率，達到預期的目標。

併購是企業策略中，短時間內迅速擴張規模，最快速且具主控能力的成長方式。隨著國際情勢的改變，全球各家半導體大廠紛紛透過併購進行水平整合，以期在創新能力上有所突破。本研究目的為以聯發科併購晨星一案為例，探討台灣半導體IC設計產業概況、併購動機、併購過程及未來策略發展，並分別以現金流量折現、類似企業比價、資產價值評價作為企業評價方法以分析財務績效。 透過個案研究，瞭解全球與台灣半導體IC設計產業因總體經濟情勢未來發展而趨緩、智慧型手機快速發展及面臨大陸IC設計廠商崛起，佐以過去數年台灣半導體產業發生的重大交易案件，發現具水平整合趨勢。因此聯發科併購晨星可結合手機與電視晶片市場，擴大3C市場競爭力，同時整合雙方研發技術，強化產品競爭性，並擴大企業規模以因應國際化競爭。策略角度而言，更能夠節省產品線研發的重覆投入成本、建立進入門檻及滿足更多客戶需求。 績效分析結果顯示，在現金流量折現法的部分，無論是聯發科單獨存在的企業價值或晨星單獨存在的企業價值，換算成每股內含價值後皆超過現有的股價。而在類似企業比較法的部分，由於業務性質差異，換算股價時較現金流量折現法產生價格低。而資產價值評價法的部分，由於採用清算價值法，出發點為會計之評價方法，但未考慮公司的未來獲利能與現金流量，且按清算價值計算時容易低估企業價值；同時對商譽、專利與或有負債對公司價值的影響不易正確評價。 / M&A (Merger and Acquisition) is undoubtedly the fastest enterprise growth strategy to grow business scale with controllability. As international industry changes, most of semiconductor enterprises began their horizontal integration though M&A to cope with their innovation difficulty. In this study, we analyzed Taiwanese IC design industry, the M&A intention and transaction process and future strategy development through MediaTek’s acquisition of MStar, and evaluated financial performance with enterprise valuation methods such as discounted cash flow (DCF), comparable enterprises and asset valuation. Though case study, we realized the slowdown of global and Taiwanese IC design industry, fast-growing smartphone demand and the rise of Chinese IC design firms, and also found the trend of horizontal integration in Taiwanese semiconductor industry by reviewing major cases past years. Therefore, the acquisition of MStar enabled MediaTek to strengthen their competitiveness in smartphone and TV IC market, enhance technology level and increase business scale to compete in this global competition. From the perspective of strategy analysis, it also saved research cost, built up entry barrier and fulfilled more clients’ need. The results of performance analyses in this study are as follows: in DCF, MediaTek’s or MStar’s standalone implied share price both exceed stock prices. In comparable enterprises, both of them are lower than the ones with DCF method due to different companies are valued differently based on their business portfolio and client base. In asset valuation, we used liquidation value as proxy, where it takes total amount of assets and liabilities into account but future profitability and cash flow. Intangible assets, such as goodwill and intellectual property, and contingent liabilities should be also considered. Hence the liquidation share price is likely to be underestimated.

A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack is needed. Second, in the heterogeneous integration, an effective thermal isolation solution is needed to ‘protect’ the low-power tier from the high-power tier. This research focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal resistance of 0.269 K·cm2/W at a flow rate of 70 mL/min. High aspect ratios TSVs (18:1) are integrated in the micropin-fins. Within-tier microfluidic cooling is then implemented in 3D stacks to emulate different heating scenarios, such as memory-on-processor and processor-on-processor. Air gap and mechanically flexible interconnects (MFIs) are proposed for the first time to decrease the vertical thermal coupling between high-power (e.g. processor) and low-power tiers (e.g. memory or nanophotonics). A two-tier testbed with the proposed thermal isolation technology is designed, fabricated and tested. Compared with conventional 3D integration approach, thermal isolation technology helps reduce the temperature at a fixed location in the low-tier by 12.9 °C. The resistance of a single MFI is measured to be 46.49 mΩ.

This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy. The first prototype SoC is a neural recording interface intended for wireless monitoring of intractable epilepsy. The 0.13um CMOS SoC has 64 recording channels, 64 programmable FIR filters and an integrated 915MHz FSK PLL-based wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a minimal area and power overhead. In vivo measurement results from freely moving rodents demonstrate its utility in preoperative monitoring epileptic seizures. Treatment of intractable epilepsy by responsive neurostimulation requires seizure detection capabilities. Next, a low-power VLSI processor architecture for early seizure detection is described. It the magnitude, phase and phase synchronization of two neural signals - all precursors of a seizure. The processor is utilized in an implantable responsive neural stimulator application. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The efficacy of the processor in epileptic seizure detection is validated on human EEG data and yields comparable performance to software-based algorithms. The second prototype SoC is a closed-loop 64-channel neural stimulator that includes the aforementioned seizure detector processor and is used for preventive seizure abortion. It constitutes a neural vector analyzer that monitors the magnitude, phase and phase synchronization of neural signals to enable seizure detection. In a closed loop, abnormal phase synchrony triggers the programmable-waveform biphasic neural stimulator. To implement these functionalities, the 0.13um CMOS SoC integrates 64 amplifiers with switched-capacitor (SC) bandpass filters, 64 MADCs, 64 16-tap FIR filters, a processor, 64 biphasic stimulators and a wireless transmitter. The SoC is validated in the detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. The results demonstrate its utility in treatment of intractable epilepsy.

This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy. The first prototype SoC is a neural recording interface intended for wireless monitoring of intractable epilepsy. The 0.13um CMOS SoC has 64 recording channels, 64 programmable FIR filters and an integrated 915MHz FSK PLL-based wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a minimal area and power overhead. In vivo measurement results from freely moving rodents demonstrate its utility in preoperative monitoring epileptic seizures. Treatment of intractable epilepsy by responsive neurostimulation requires seizure detection capabilities. Next, a low-power VLSI processor architecture for early seizure detection is described. It the magnitude, phase and phase synchronization of two neural signals - all precursors of a seizure. The processor is utilized in an implantable responsive neural stimulator application. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The efficacy of the processor in epileptic seizure detection is validated on human EEG data and yields comparable performance to software-based algorithms. The second prototype SoC is a closed-loop 64-channel neural stimulator that includes the aforementioned seizure detector processor and is used for preventive seizure abortion. It constitutes a neural vector analyzer that monitors the magnitude, phase and phase synchronization of neural signals to enable seizure detection. In a closed loop, abnormal phase synchrony triggers the programmable-waveform biphasic neural stimulator. To implement these functionalities, the 0.13um CMOS SoC integrates 64 amplifiers with switched-capacitor (SC) bandpass filters, 64 MADCs, 64 16-tap FIR filters, a processor, 64 biphasic stimulators and a wireless transmitter. The SoC is validated in the detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. The results demonstrate its utility in treatment of intractable epilepsy.

Pas de résumé / CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade. Furthermore technology advancement has provided the capability to integrate more and more functionality into a single chip in multiple layers leading to a new paradigm, 3D integration. CMOS image sensor is one such application which could utilize the capability of 3D stacked architecture to achieve dedicated technologies in different layers, wire length reduction, less area, improved performancesThis research work is focused mainly on the early stages of design space exploration using hierarchical approach and aims at reducing time to market. This work investigates the imager from the top-down design perspective. Methodical anal y sis of imager is performed to achieve high level of flexibility and modularity. Re-useable models are developed to explore early design choices throughout the hierarchy. Finally, pareto front (providing trade off solutions) methodology is applied to explore the operating range of individual block at system level to help the designer making his design choice. Furthermore the thermal issues which get aggravated in the 3D stacked chip on the performance of the imager are studied. Systeme based thermal model is built to investigate the behavior of imager pixel matrix and to simulate the pixel matrix at high speed with acceptable accuracy compared to electrical simulations. The modular nature of the model makes simulations with future matrix extension straightforward. Validation of the thermal model with respect to electrical simulations is discussed. Finally an integrated design flow is developed to perform 3D floorplanning and to perform thermal anal y sis of the imager pixel matrix.

Estudamos, através de fotometria superficial CCD em B, V, R e I, quatro galáxias espirais, classificadas como barradas, com tipos morfológicos entre Sa e Se: NGC 6835, NGC 5757, IC 1091 e NGC 7412. Para cada galáxia, obtivemos mapas de isofotas e, através do ajuste de elipses às isofotas, determinamos parâmetros como inclinação, orientação no céu e diâmetros. Pelo ajuste de curvas padrões de crescimento às magnitudes integradas, obtivemos magnitudes totais em B e V. Traçamos diferentes tipos de perfis de brilho, tais como perfis de luminosidade ao longo dos eixos maior e menor das galáxias e/ou das barras, perfis de luminosidade promediados elipticamente e perfis azimutais. Os perfis nas direções das barras mostraram que o brilho superficial ao longo dessas componentes decresce de maneira uniforme, com um gradiente quase exponencial, e que é mais íngreme em I do que em B. Decompusemos os perfis de luminosidade médios em componentes bojo e disco, ajustando leis de De Vaucouleurs e exponencial. Os perfis azimutais foram estudados com análise de Fourier para determinar as componentes dominantes na região da barra. Traçamos perfis em várias cores ao longo dos eixos principais das galáxias e constatamos que três delas têm núcleo azul, sugerindo ser esse um fenômeno comum em galáxias barradas. Comparamos as cores nucleares com modelos de síntese de população estelar, o que mostrou que aconteceram eventos de formação estelar nesses núcleos nos últimos 108 anos. / We obtained CCD surface photometry in the B, V, R, I wavebands, for four barred spiral galaxies with morphological types ranging from Sa to Se: NGC 6835, NGC 5757, IC 1091, and NGC 7412. For each galaxy we obtained isophote maps, inclination, orientatión, and diameters. We determined B and V total magnitudes by fitting standard growth curves to integrated magnitudes. We determined different kinds of luminosity profiles, · such as luminosity profiles along the major and minor axis of the galaxies and/or the bars, elliptically averaged luminosity profiles and azimuthal profiles. The profiles along the major axis of the bars showed that the surface brightness along these components decreases smoothly; the gradient is almost exponential and steeper in I than in B. We decomposed the mean luminosity profiles in contributions from bulge and disc, using as fitting functions de Vaucouleurs' law and an exponentiallaw. The azimuthal profiles were studied by Fourier transformations to determine the main components in the bar region. Color profiles along the principal axis of the galaxies revealed that three of them have blue nucleus, suggesting · this is a common phenomenon among barred galaxies. A comparison of the nuclear colors with models of stellar population synthesis showed that bursts of star formation occurred in these nuclei during the last 108 years.

abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB. The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017