Den här studien har haft som avsikt att undersöka hur redovisning av intellektuellt kapital rapporteras av de fyra största bankerna i Sverige. Vi beskriver och analyserar vilka indikatorer bankerna fokuserar på i redovisningen av intellektuellt kapital. Vi har gjort en kvalitativ undersökning genom att analysera den icke-finansiella delen i årsredovisningar från Handelsbanken, SEB, Swedbank och Nordea från åren 1998, 2003 och 2008. Vi har valt att kategorisera intellektuellt kapital efter MERITUM’s definitioner av human-, struktur- och relationskapital. Resultatet av studien visar att redovisningen inte följer någon enhetlig standard för redovisning av intellektuellt kapital. Det presenteras mycket information men fokuseringen ligger på enstaka indikatorer. Detta gör att redovisningen blir svår att jämföra. Studien visar att bankerna fokuserar mest på indikatorerna kompetensutveckling, rutiner, policies, företagskultur och kundrelationer.

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.

Detta examensarbete undersöker effekter av en elektromagnetisk puls på IC-kretsar. För att kunna utvärdera inverkan har ett testobjekt, innehållande komponenter som skall testas, konstruerats. Detta testobjekt består av batteri, en enkel komponent och last. Ett pulsaggregat och en antenn användes för att generera de elektromagnetiska pulser som testobjektet utsattes för. Resultaten visar att inverkan på de testade komponenterna är möjlig. Inverkan visade sig vara beroende av bl.a. avståndet till antennen och den tid som testobjektet utsätts för störning. Störning har också utförts vid olika polariseringar. Ett mål var att kunna jämföra en elektromagnetisk störning via en antenn med en trådbunden störning, där pulsen genererats från samma pulsaggregat. Försöken att utföra trådbunden störning av testobjektet misslyckades då pulsen inte var tillräckligt bra. Detta examensarbete är en del av en artikel, High Power Ultra Wide Band and Vircator Source-Victim Experiment, som presenterades vid konferensen EMC Europe 2008. / This paper studies the effects of an electromagnetic pulse on IC-circuits. A DUT (device under test) has been constructed so that the effects of the pulse can be evaluated. The DUT consists of a battery, a load and the component, which is to be tested. A high voltage power supply and an antenna were used to generate the pulses that the DUT were exposed to. The results show that the effects were dependent on, among others, the distance between the antenna and the DUT and the time during which the DUT was exposed to the pulse. The DUT has also been exposed to different polarisations of the pulse. One of the objectives of the study was to compare the difference between a pulse from an antenna and from a wire. This was to be done with the same high voltage power supply. Attempts to use a wire, for injecting the pulse, were unsuccessful since the damped pulse was not satisfying. This paper is a part of a paper, High Power Ultra Wide Band and Vircator Source-Victim Experiment, that was presented at the conference EMC Europe 2008.

Abstract The more and more IC makers take the Research job in Silicon Valley, development in Taiwan and China, Design for Manufacturing in Taiwan and Marketing in China. There are plenty of complete Supplier Chains with organizing the companys of IC Resign, Foundry, Si-IP, Subcontracted Assembly & Test Service. The capacity offered is almost over 60% worldwide with very high technique and quality level. This is getting more dominantly important to provide turn-key service durin IDM shrinking trend. Meanwhile the great gap in the supply chain is expanding in IC testing design and manufacturing, which is the bottle neck of IC industry in either cost, technical or turn-around time. The research is subjected to get a workable business model of IC testing Design Service working with a right product Segmentation, Targeting, Positioning to compensate the gap. The research takes kinds of reference of Competitive Advantages, Competition Strategies, Co-petition Strategy, Competition, Strategy, and Disruptive Innovation to construct the research model. IC Testing Design is an innovative business model in Taiwan Industry. Conseguently the research collects opinions from high level managers of IC industry. It also does a case study by using the case of BEST-itech, which is the first supplier of IC Testing Service in Taiwan market. We could learn the SWOP to see how to provide the Testing Design Service in right positioning and strategy. The targeting customers are all in the Supply Chain of Virtual IDM, including IDM, Foundry, Design House, Design Service, Test & Assembly, ATE Vendor, FA House etc. During the resession of 2008, much more demand toward Virtual-IDM is firmed. The outsourcing demand of IC testing design is getting clear. ATE vendor¡¦s market scale growth is getting slow as well as the ASP. So the requirement and opportunity of IC Testing Design Service is happening. The research concludes the IC Testing Design is a workable and necessary sub-chain in IC-subcon supply. The Value Network is a good model to tell how to transfer the comptition to be the compensator or customers for all players in the supply chain. The research also concludes 4 segments necessary in the IC Testing Design business model. Those are 1. Tester Opt ionization of Utilization. 2. Device Interface Integrated with Testing Design. 3. Add-on Solution Implement in Testing Tech-Gap. 4. Test Floor Automation and SPC Testing. Hopefully this research could provide a good picture to start the innovative business model to help the IC industry.

Currently the trend of electronic product development is to ward ¡§light and thin, multi-functional, high density and durability¡¨. When the microelectronic chips tend to be high power, high density and high speed, the rapid increase of heat in a reduced unit area of package size, will lead to failure of electronic products. The contents of thesis is to find out the dominant factors in heat transfer by changing the geometries and material properties of QFN and BGA packages. It also aims to achieve the beat the thermal performance by reducing the probability of failure. In industries it needs a lot of cost and time in experiment work due to the changes of size and materials. Herein, the softwares of ANSYS and ICEPAK are adopted to model the QFN and BGA packages with the statistical experimental design of Taguchi method L18 (21¡Ñ37) orthogonal array setting parameters and obtain the degree of effect for each factor. Eventually, we use the analysis of variance ANOVA to obtain the contribution of each factor and to identify the significant degree for various parameters by variance error integration. From the results the die attach thermal conductivity affects the contribution of thermal performance up to 81.46% for QFN package in comparison with other controlling factors of high significance and high impact effects. Die attach thermal conductivity between 0.5 W/m•k and 1.5 W/m•k the Tj declines much larger than that between 1.5 W/m•k and 8 W/m•k. Die /PKG area ratio affects the contribution of the thermal performance to 64.24% and increasing Die /PKG area ratio can reduce the Tj for BGA package. The significant effect is also higher than other factors. However, the contribution of substrate layers is 18.83% at 99% confidence level.

With the advances in very large scale integration (VLSI) technology, hardware is going parallel. Software, which was traditionally designed to execute on single core microprocessors, now faces the tough challenge of taking advantage of this parallelism, made available by the scaling of hardware. The work presented in this dissertation studies the acceleration of electronic design automation (EDA) software on several hardware platforms such as custom integrated circuits (ICs), field programmable gate arrays (FPGAs) and graphics processors. This dissertation concentrates on a subset of EDA algorithms which are heavily used in the VLSI design flow, and also have varying degrees of inherent parallelism in them. In particular, Boolean satisfiability, Monte Carlo based statistical static timing analysis, circuit simulation, fault simulation and fault table generation are explored. The architectural and performance tradeoffs of implementing the above applications on these alternative platforms (in comparison to their implementation on a single core microprocessor) are studied. In addition, this dissertation also presents an automated approach to accelerate uniprocessor code using a graphics processing unit (GPU). The key idea is to partition the software application into kernels in an automated fashion, such that multiple instances of these kernels, when executed in parallel on the GPU, can maximally benefit from the GPU?s hardware resources. The work presented in this dissertation demonstrates that several EDA algorithms can be successfully rearchitected to maximally harness their performance on alternative platforms such as custom designed ICs, FPGAs and graphic processors, and obtain speedups upto 800X. The approaches in this dissertation collectively aim to contribute towards enabling the computer aided design (CAD) community to accelerate EDA algorithms on arbitrary hardware platforms.

Abstract Presently, IC is an important and absolutely necessary product that the thriving electronic industry is relying on in order to continue its development, therefore, it goes without saying that it is very important. In addition, the intellectual property right possessed by the IC itself is related to the development and progress of the industry technology. Therefore, in the early period, many countries and international organizations already enacted law to protect the intellectual property right of IC. In addition, the legislature protection on the intellectual property right of the integrated circuit was originated from the ¡uProtection of Semiconductor Chip Products¡vof United States. Thereafter, through the provision of the mutual benefit terms and its strong trading strength, United States influenced various countries like Japan, Taiwan and Mainland China to enact laws consecutively for the purpose of protection. Furthermore, between international countries, due to the importance of IC and the strength of United States, there were related treaties to protect the intellectual property right of IC. Amongst these the most important treaty was the ¡uAgreement on Trade-Related Aspects of Intellectual Property Rights (TRIPS)¡vestablished by the World Trade Organization (WTO). It replaced the ¡uthe Treaty on Intellectual Property in respect of Integrated Circuits (IPIC)¡v stipulated by the World Intellectual Property Organization (WIPO) and became the only international treaty with protection provision on the intellectual property right of IC. Up to this stage, the legal protection on the intellectual property right of IC has already become an international trend. Moreover, due to the long-time shut-off condition in Mainland China, only after it was re-opened again, its economy started to develop. With its own vast market and the advantage of low production cost, added with the full effort of encouragement on the development of IC industry by the Mainland China authority that stipulated many relative favorable policies, many international IC enterprises were attracted to invest in Mainland China. Of course, without exception, IC enterprise of Taiwan also went to set up factories in Mainland China. However, as Mainland China was at a shut-off condition for a long time, therefore related laws and regulations were not complete. Thereafter due to the practical pressure of international countries, Mainland China further established the ¡uIC Layout Drawing Design Protection Regulation¡v. However, as the development of the intellectual property right law was comparatively late, it resulted in failure in the performance of law execution. Therefore, it was extremely easy for the IC enterprises that went to invest in Mainland China to encounter infringement of intellectual property right and of course this also included enterprise of Taiwan, the trend of legal protection on the IC intellectual property right between United States and international countries is utilized to examine the protection structure of the intellectual property right of IC of Mainland China. The purpose is to understand when the international IC enterprise is developing in Mainland China, how it can utilize related legal protection structure to establish a set of its own intellectual property right protection system. Furthermore, suggestion on appropriate protection on the intellectual property right is presented to our IC enterprise in Mainland China so that the intellectual property right of our IC enterprise in Mainland China can obtain sufficient protection.

Taiwan¡¦s IC foundry has truly emerged as important roles in Taiwan¡¦s electronic industries, whose fast growth has successfully been in the construction of Taiwan¡¦s economic miracle. Through the differentiation strategy, TSMC, the largest and most successful dedicated IC foundry in the world, expands and develops its business from bottom to top. It also has well driven IC industries a Cluster Effect, prosperously fostering the industries in its supply chain, from IC design and manufacturing to packaging and testing, even rapid growth of Taiwan¡¦s personal computer and peripheral industries relatively. Long-term, increasing growth for IC industries had earned many companies to invest low entry barrier factories - IC packaging that needs lower technical expertise and less capital. However, against semiconductor industrial booming and bust cycles, and the phenomenon known as the Bullwhip Effect in supply chains, most packaging factories have been confronting with the challenges in worse and more competitive environments. Those factories, even the same for the new entrants, actively adopted all different types of competitive, cooperative and integrated strategies, not only for profits but survival. In this study, based on path dependence theory, the competitive strategies among ten new IC packaging companies were introduced to discuss, examine, and more further verify the linkages between their competitive strategies and developing paths. The conclusion indicates that competitive strategies of positive developing path may offer new entrants a successful, experienced model to copy with. 1.The advancement of Taiwan IC packaging new entrants gave evidence for developing path¡¦s model. That is to say, different competitive strategies will result in different developing paths. 2.The competitive strategies of the positively developing path¡¦s model are helpful for new entrants to develop positively. Strategic positioning helps to concentrate company¡¦s resources onto her beneficial path to develop. Innovative strategies will help to break through the limitations of path and guide the developing path to success. Competitive advantage helps the developing path come into positive cycles. 3.IC packaging companies have to review and react very often to manage their competitive strategies when the developing path is influenced by the variances of inner and outer environments.

According to the research of the Taiwan Semiconductor Industry Association in 2004 , IC design in Taiwan is becoming the second major clustering centre after America. IC design house seems to be the upcoming star in Taiwan semiconductor industry, by its highly brainstorming to create higher additional value, it is also the next leading role in hi-tech industry in Taiwan.To IC design house, the quality of employees is the key of competitiveness, therefore, only dependent on the staff's constant research and innovation, could occupy a space on the competitive market, so the reserch of management of professional human resources in IC design house seems even more important. This study adopts the in-deep interview of qualitative reserch, including six RD engineers, four product engineers and five human resources personnel as the research objects.The main purpose is to understand what the employees truely demand in IC design house? How is the operation of human resource management practice and the expectation to Human Resource Department? How the professional personnel of human resources understand the idea and demand of employees, make a right management system and offer the best welfare measure. Through the interview materials, along with domestic, international documents, the results come out as following: 1. The demand of RD engineers and product engineers learning development opportunity / excellent manager / good working environment / understand the employees demand / limitless creation and innovation / the balance of work and life 2. The expectation of RD engineers and product engineers to Human Resource Department to be intercommunication channel / complete training program / attract and retain outstanding talents / strengthen professional ability more actively 3. The contribution of Human Resource Department of IC design house to Human Resource Managemant Recruit high-quality talent / administration efficiency / salary and welfare policy / incentive system to keep talent / promote innovation ability of employees / complete training program / build a common vision /build a high-quality working environment / intercommunication channel / understand the employees truly need 4. IC Design House Human Resource Management Model (1)recruit and employ: recruit channel: manpower bank/ employee recommendation/ campus recruit / national defence labor recruit procedure: recruit by HR or department director employ characteristic: good team player/ dedicated/ learning spirit employ term: response ability/ professional ability/ communication coordinate ability/ innovation ability (2)salary and benefit: attractive payment/ cash allowance/ meal allowance/ entertainment/ group insurance/ society safety/ retirement plan (3)training and development: e-learning/ invite outside instructor/ lessons by senior employees/ seminar/ training plan evaluation/ training result check and accept (4)performance evaluation: fair/ justice/ team performance/ individual performance (5)labor relations: interaction frequently/ diversified encourage program/ resignation management

IC test socket and socket pogo pin are the major cost of consumption parts in IC testing house. Test yield is the key point to determine the profit for IC testing house. When the processing speed of CPU (Central Processing Unit) and GPU (Graphic Processing Unit) are boosting, heat generation and power dissipation became a serious problem for IC testing house. Most package type of CPU and GPU are packed by Flip-Chip BGA type. High temperature will melt the solder ball and cause test socket pogo pin to damage. The excellent cooling capability of impinging jet had been proofed by many literatures in past. In this article, impinging jet applied to IC test handler contact chuck is investigated. The contact chuck had been redesigned with thermal solution and uses a rectangle hot plate to simulate the thermal status of IC testing. A circular air jet impinged on the rectangle hot plate from the topside of contact chuck. Out flow open area, open area on the wall location and the distance between jet nozzle and hot plate are major parameters of this heat transfer problem. Parameter ¡§Z¡¨ is the distance between jet nozzle and hot plate; ¡§D¡¨ is the diameter of circular air jet. As shown in the result, ratio of Z/D and the location of out flow open area on the wall is obvious on heat transfer capability for redesigned contact chuck. Taguchi method and analysis of variance (ANOVA) method help to clarify the weighting of influence. The optimum Z/D is 0.5 and the optimum location of out flow open area is at dual side corner. Heat transfer capability can be improved approach to 70% after optimization. Width and height of out flow open area only made about 5% impact on heat transfer capability.