Quantitative Planar Laser Induced Fluorescence (QPLIF) is developed as a diagnostic technique and then applied to a prototype Jaguar optical internal combustion engine. QPLIF derives quantitative, two-dimensional, spatially-resolved measurements of fuel concentration. This work reports the first demonstration of a fully-fractionated surrogate fuel which exhibits all the characteristics of a typical gasoline. This 'pseudo' fuel, developed in association with Shell UK, is blended to accept a fluorescent tracer which may track one of the light, middle or heavy fractions of the fuel, each of different volatility. The traditional weaknesses of PLIF for quantitative measurements are addressed by use of a fired in-situ calibration method, which maps the quantum efficiency of the tracer and concurrently corrects for window fouling and exhaust gas residuals (EGR). Fuel distributions are presented with an estimated super-pixel accuracy of 10% at different operating conditions, and then compared to the computational fluid dynamics (CFD) predictions of an in-house Jaguar model. Fuel/Air Ratios by Laser Induced thermal Gratings (FARLIG) is developed theoretically, and results of validation experiments conducted in a laboratory setting are reported. FARLIG conceptually enables the measurement of fuel concentration, oxygen concentration and temperature within a spatially-localised probe volume. Uniquely, the technique exploits the dominant influence of molecular oxygen on non-radiative quenching processes in an aromatic tracer molecule. The changing character of a model quenching mechanism potentially allows the oxygen concentration in the measurement volume to be derived. Absolute signal strength is used to determine fuel concentration, while the oscillation period of the signal provides a precise measurement of temperature (~0.3% uncertainty), with accuracy limited by knowledge of the gas composition.

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

Esse trabalho apresenta uma proposta na área de Educação em Microeletrônica que visa enriquecer práticas de ensino adotadas na área de projetos de circuitos integrados através do uso de máquinas de ensino-aprendizagem (TLM Teaching-Learning Machine) em aulas de laboratórios como instrumentos auxiliares e complementares ao ensino teórico. As TLMs propostas permitem a verificação experimental de conceitos fundamentais em VLSI Design, tais como: polarização de transistores NMOS e PMOS, inversores CMOS, curvas de transferência do inversor CMOS, implementação de diversas portas lógicas CMOS estática e dinâmica usando transistores de passagem ou portas de transmissão (NAND, NOR, AND, OR, XOR, XNOR, MUX, DECODER, Half ADDERs e Full ADDERs), Latches, Flip-flops e células de memória (RAM e ROM). A metodologia usada foi baseada em pesquisa bibliográfica, observações em sala de aula, participação em projetos didáticos, entrevistas com alunos e professores de microeletrônica. As TLMs foram construídas na forma de painéis de papelão de 100 cm x 70 cm com eletrônica embarcada ou conjuntos de módulos de circuito impresso com tamanhos A4 até A10, interligados entre si por meio de conectores, cabos elétricos padronizados e acondicionados em caixas flexíveis de borracha sintética. Considerou-se o uso combinado desses materiais com diferentes técnicas de montagens eletrônicas. No leiaute das TLMs foram considerados aspectos da interação homem-máquina (HMI) e projetos de interações por PREECE (2002), e da transposição didática de CHEVALHARD e JOSHUA (1981). Os resultados efetivos da aprendizagem usando TLMs foram obtidos por meio de uma dinâmica em sala de aula baseada no microensino em ALLEN (1967). / This paper presents a proposal in the area of Education in Microelectronics which aims to enrich the educational practices adopted in the area of integrated circuits design through the use of teaching-learning machines (TLM) in classes, laboratories as auxiliary and complementary instruments to the theoretical ones. The proposed TLMs allow the experimental verification of fundamental concepts in VLSI design, such as: NMOS and PMOS transistors biasing, CMOS inverters, transfer curves of a CMOS inverter, implementation of various static and dynamic CMOS logic using the pass-transistor or transmission gates (NAND, NOR, AND, OR, XOR, XNOR, MUX, DECODER, Half ADDERs and Full ADDERs), Latches, flip-flops and memory cells (RAM and ROM). The used methodology was based on a literature search, observations in the classroom, participation in educational projects, interview of students and professors involved with microelectronics. The TLMs were assembled in the form of paper panels, 100 cm x 70 cm embedded with electronic modules, or sets of printed circuit boards with A4 size up to A10 size, connected with each other through connectors, electrical wires and packed in synthetic rubber flexible boxes. The combined use of these materials with different techniques of electronic assemblies has been very important. The layout of TLMs concerns about the aspects of human-machine interaction (HMI) and design interactions from PREECE (2002), and the didactical transposition from CHEVALHARD and JOSHUA (1981). The effective learning results using TLMs were obtained through a dynamic in classroom based on microteaching from ALLEN (1967).

Cette thèse interroge le destin de Judas chez cinq écrivains : Paul Claudel (Mort deJudas), Marcel Pagnol (Judas), Jean Ferniot (Saint Judas), Armel Job (Judas le bien-aimé)et Eric-Emmanuel Schmitt (L’Évangile selon Pilate). Passant du cadre général à celuiparticulier, la recherche se propose d’envisager la figure de Judas dans les transpositionsbibliques contemporaines et d’évaluer les nouvelles visions que le siècle a inventées.L’analyse comprend des approches s’appuyant sur les contributions du domaine du mythe,de l’exégèse biblique, historique, de la sociologie, de la psychanalyse. La plupart des récitscontemporains font de Judas un sujet moderne très complexe : il devient figure de l’artiste,du philosophe et de l’acteur.Les problématiques d’ordre social et politique se révèlent primordiales : dans uncontexte succédant à l’Holocauste, Judas renoue avec l’univers judaïque. Retranscrivant lemythe du Juif errant, Judas devient figure de la scission, du départ et de l’errance ; lesrelations au sein de la famille sont vivement remises en cause. La figure du traître devientaussi le support d’une parole restitutive. L’idiotie de filiation dostoïevskienne attribuée àJudas fait bon ménage avec le contexte littéraire contemporain ainsi qu’avec celuilégendaire réévalué.Constamment hésitant entre la réhabilitation de Judas proposée par Pagnol, Ferniot,Job, Schmitt et la réprobation du personnage par Claudel, le parcours propose un richeréseau construit autour de thématiques communes mais différemment évaluées. / This doctoral dissertation questions Juda's destiny in five authors: Paul Claudel(The Death of Juda), Marcel Pagnol (Juda), Jean Ferniot (Saint Juda), Armel Job (TheBeloved Juda) and Eric-Emmanuel Schmitt (The Gospel according to Pilate). Fromgeneral to specific, this research aims at outlining the image of Judas within thecontemporary biblical renditions and to evaluate new perspectives on it. This analysistouches upon myth, biblical and historical exegesis, sociology and psychoanalysis. Mostcontemporary stories make Juda a very complex and modern subject: he embodies theartist, the philosopher, the actor.Social and political issues prove to be crucial: in a context which follows theHolocaust, Juda reconnects with the Judaic universe. By rewriting the myth of thewandering Jew, Juda becomes the figure of the scission, of the departure and of the roving;family relationships are strongly questioned. Furthermore, the figure of the traitor becomesthe repository for a restitutive speech. The idiocy, in the Dostoievskian sense, associatedwith Judas, blends well both with the contemporary literary context as well as with thereconsidered mythical one.Constantly hesitating between Judas' redemption that Pagnol, Ferniot, Job andSchmitt adopt and the condemnation of Claudel's character, this thesis focuses on aconvoluted network built around common themes that are tackled differently.

本文從社會脈絡的角度來思考網際網路之傳播研究，認為單一網路傳播現象或傳播事件有助於簡化研究問題。因此本文試圖從網際網路中的一個重要傳播形態－全球資訊網－出發，目的在了解其特殊文本結構與傳播特質，如何影響其在某一社會議題傳播過程（或傳播內容的生產與消費）中的論述表現？以及此論述表現對社會議題的影響力和意義？作者挑選了一個曾是重要社會議題，也與全球資訊網傳播形態發生關連之國民卡事件作為討論對象，原因是「反國民卡網站」的成立讓反國民卡行動成為一個與網路傳播相關的社會事件。在研究方法上，作者嘗試應用論述分析方法於全球資訊網網站的分析中，並希望發展出全球資訊網的系統性分析方法。研究發現，論述活動接合了網際空間與社會空間，因此論述可以作為研究網路傳播之出發點。其次，全球資訊網超文本之開放性，提供社會成員更多操縱傳播媒體的機會以及一個多元論述的環境，讓社會成員依自身利益主動結合取得對事物的詮釋權力，而全球資訊網論述表現對社會議題所具有的意義，也就在它可以作為一個「團體的媒體」，讓社會成員可以結合起來對抗社會中的主流論述。最後，全球資訊網網站之論述分析可以從網站「文本」形態出發，進而討論文本背後所牽涉到的相關社會脈絡，以豐富對個案的詮釋。

處於競爭激烈、產品生命週期短暫和快速變動的時代裡，製程創新活動成為廠商競爭優勢的關鍵因素之一。Pisano（1995）研究指出廠商藉由製程創新活動來強化競爭優勢，包括：加速產品上市時間、加快爬坡速度、提高使用者接受性、強化專利產品地位等，其他學者也認為廠商應該重視製程創新活動，以因應未來的環境趨勢。國內製造業向來以製造能力見長於國際舞台，近年來半導體產業和資訊電子產業的表現更顯示廠商優異的製造實力。儘管如此，有關這方面的研究仍然非常少，因此本研究的目的是探討我國廠商製程創新活動之重要關鍵因素，期望能對這方面進行較為整體性的分析。 根據技術創新相關理論，本研究以技術網路、人員、組織和制度四構面探討半導體產業和主機板產業製程創新活動之重要因素和差異性，所得到的研究發現如下： 1. 製程創新活動可區分為四類型：獨立型、依賴型、主導型和協調型。獨立型廠商傾向於獨自開發新製程技術，依賴型廠商則傾向於透過技術網路提升製程技術水準；在對內和對外的製程創新活動上主導型廠商的整合能力較強，協調型廠商則較弱。 2. 不同製程創新類型有不同的製程知識來源。在來源方面，半導體產業（流程產業）顯示出較集中的現象，主機板產業（非流程產業）則顯得較分散。 3. 與設備供應商的互動關係為製程創新活動之重要影響因素，不同類型的廠商與設備供應商的互動關係不同。 4. 主機板廠商（非流程產業）藉由製程知識輸出來提高外包廠商的製程品質，製程創新程度越高的廠商與外包廠商的關係越密切。 5. 人員的技術和經驗為製程創新活動中重要的因素之一，半導體廠商（流程產業）特別強調研發人員的量產經驗。 6. 製程創新程度越高，廠商的製程技術單位之主導權越大。 7. 製程創新程度越高，廠商越傾向於設立製程技術協調單位。 目錄 / Abstract In highly competitive, short product life cycle and quickly changing environment, process innovation is one of a firm’s key competitive advantages. Pisano & Wheelwright (1995) consider that firms which do their best in process innovation can enhance their competitive advantages, including shortening time to market, increasing ramp-up speed, enhancing users’ acceptance, increasing product’s patent status and so on. Hayes & Wheelwright (1984) point out the concept of manufacturing strategy, consider that firms should escalate the role of the manufacturing division to decision-making on top management level, and claim that competitive advantages which are based on manufacturing capabilities will direct the decision-making process of marketing and engineering in future. To catch up adaptability for the trend of the future environment, other scholars also suggest that firms should actively make efforts to execute process innovation activities. Manufacturing firms in Taiwan display their manufacturing competence on international status, especially in IC industry and in information technology industry. Therefore, Taiwan is always named as “manufacture kingdom”. In the past, industrial firms’ process innovation is mainly thinking about employing cheaper labors and buying newer equipment. However, now they pay more attention to research and develop process technology, to enhance production process integration capabilities, to increase production flexibility and so on. For example, TSMC and UMC in Taiwan have more advanced process technology, which is about at the same technological level as IC industrial leading firms oversea. Their advanced process technology not only creates many benefits but also drives the development of other related industries. Their success shows us that process innovation will bring firms continuously high growing rate and take long-run competitive advantages. By forgoing observation, this paper wishes to discover what makes Taiwan the manufacturing kingdom and how do firms increase process advantages and execute process innovation activities. So the purpose of this paper is to find out what influences a firm’s performance of process innovation and how foregoing factors affect new process innovation and existing process innovation. Utterback (1994) finds assembled product and non-assembled product have different characteristics in innovation activities. Skinner (1992) explores how stakeholders are within their cognizance about a firm’s process innovation, and finds that there are different focuses between process industry and non-process industry. Therefore, this paper will go further to study how foregoing factors influence process performance in process industry and in non-process industry. According to some related technology innovation theories and innovation theories, this paper is conducted based on four key dimensions: technology network, people, structure and management. Then, this paper infers some important items of forgoing dimensions from past studies to build the research framework of the paper. These items in technology network dimension are equipment suppliers, material and component suppliers, satellite factories, group/strategic leaguer/consumer and research institutions. In people dimension, this paper mainly wants to explore how personnel’s skills and experience influence process performance. Structure dimension contains three items, which are organizational structure, task allocation and strategy. This paper lists important items in management dimension, including rewarding system, training & education, information system and coordination mechanism. Because related studies in the past explore only a part of process innovation, this paper employs case study to examine process innovation more systematically and completely. To explore a firm’s process innovation of high-tech industry in Taiwan, this paper chooses four IC manufacturing firms (process industry) and four motherboard firms (non- process industry) as research samples, which have better performance than others in their industry. Moreover, this paper classifies these samples into four groups according to the industrial characteristics and the process innovation level. In the field of IC industry (process industry), Fab-T and Fab-U are famous for advanced process technology and continuous research on advanced process technology. So this paper explores the development of the new process technology in Fab-T and Fab-U, and the improvement of existing process technology in Fab-M and Fab-K. In the field of motherboard industry, MB-A is the only motherboard firm in Taiwan, which has process patents in Taiwan now. And MB-G actively executes process innovation recently, including package and product vibrating tests. So this paper properly classifies MB-A and MB-G as a group with higher process innovation level, and explores their advanced process innovation activities. Then MB-T and MB-E are classified as lower process innovation on lower level group, and this paper explores how they improve existing process innovation. By a series of analysis about primary and secondary data of eight firms, the conclusions of this paper are: 1. There are four types in process innovation: Independent Firms, Dependent Firms, Directing Firms and Coordinating Firms. In IC industry, the Independent Firms almost develops new process innovation alone; the Dependent Firms tend to properly aided by members of technology network to enhance process innovation level. In motherboard industry, the Directing Firms have stronger relationship with menders of process innovation activities, which actively respond to the process technology unit, the Coordinating Firms have weaker relationship. 2. Different types in process innovation have different sources of process-related knowledge. The sources of IC Firms are more convergent, however the sources of motherboard firms are more divergent. 3. One of the key factors in process innovation is equipment suppliers, with which different types have different interaction. 4. Motherboard firms actively enhance the production quality of satellite factories through process knowledge output. Motherboard firms with higher process innovative level have more closely cooperating relation with their satellite factories. 5. The people is one of the key factors in process innovation. IC firms put more emphasis on the mass-production experience of engineers. 6. Whether it is in IC industry (process industry) or in motherboard industry (non-process industry), firms with higher process innovation level tend to give the process technology unit more power to integrate activities among different departments. 7. Whether it is in IC industry (process industry) or in motherboard industry (non-process industry), firms with higher process innovation level tend to set up the technology coordination unit. Finally, this paper has some advises from forgoing conclusions, and wishes to efficiently enhance a firm’s performance and production yields. These advises are: 1. The Depending Firms should do their best to improve relations with members of technology network. 2. To efficiently use resources and to increase performance in short terms, the first thing of the Coordinating Firms should do is to enhance process capabilities, instead of building good cooperative relation with members of technologic network. 3. Firms should set up a special technology-coordinating unit, which can efficiently increase interaction among different departments. 4. Firms should give more power to the process technology unit, so that it can cooperate with other departments more efficiently.

Le test en production des circuits intégrés analogiques RF (Radio Fréquences) est coûteux aussi bien en ressources (équipement spécifique) qu'en temps. Afin de réduire le coût du test, des techniques de DfT (Design for Test) et d'auto test (BIST, Built-in-Self-Test) sont envisagées bien qu'actuellement inutilisées par l'industrie du semi-conducteur. Dans cette thèse, nous concevons et évaluons une technique d'auto test pour un amplificateur faible bruit (LNA, Low Noise Amplifier) RF. Cette technique utilise des capteurs intégrés pour la mesure du courant de consommation et de la tension en sortie du circuit à tester. Ces capteurs fournissent en sortie un signal basse fréquence. La qualité de la technique de BIST est évaluée en fonction des métriques de test qui tiennent compte des déviations du process et de la présence de fautes catastrophiques et paramétriques. Pour obtenir une estimation des métriques de test avec une précision de parts-par-million, un premier échantillonnage du circuit à tester est obtenu par simulation électrique Monte Carlo. Par la suite, un modèle statistique de la densité de probabilité conjointe des performances et des mesures de test du circuit est obtenu. Finalement, l'échantillonnage de ce modèle statistique nous permet la génération d'un million de circuits. Cette population est alors utilisée pour la fixation des limites de test des capteurs et le calcul des métriques. La technique d'auto test a été validée sur un LNA en technologie BiCMOS 0.25m, utilisant différents modèles statistiques. Une validation au niveau layout a été faite afin d'obtenir des résultats aussi proches que possible lors d'un test en production d'une population de circuits.

Inductors are extensively used in the design of radio-frequency circuits. In the last decade, the integration of passive components, especially inductors on silicon chips, has led to the widespread development and implementation of Radio Frequency Integrated Circuits (RFICs) in CMOS technologies. However, on-chip passive inductors occupy a large silicon chip area and hardly scale down with technology scaling. Therefore, on-chip passive inductors become formidable obstacles to the realization of highly dense RFICs to be integrated with other highly dense digital circuits on a single chip using a common fabrication process. In recent years, researchers have focused on replacing passive inductors with transistor-only active circuits, namely active inductors. Active inductors can be realized with only a few transistors, which scale down with technology scaling. Therefore, they occupy a fraction of the chip area of their passive counterparts, and can be implemented densely in CMOS processes. Unlike passive inductors, bias dependent operations of active inductors allow for the tuning of their inductance and quality factor Q, and in turn, tuning the performance parameters of RFICs. This thesis focuses on the design and development of passive inductorless CMOS RFICs for ultra-wideband (UWB) receiver front-ends using active inductors. A new Q-enhanced and a new bandwidth-extended tunable active inductors are designed. Using the Q-enhanced active inductor, two tunable UWB low-noise amplifiers (LNAs) (two-stage and three-stage UWB LNAs), a UWB mixer and a wideband local-oscillator (LO) driver are designed. Active inductors are utilized to develop a novel wideband active shunt-peaking technique that decreases high-frequency losses to yield a flat gain over a wide bandwidth. A tunable multiband-UWB front-end integrating a two-stage UWB LNA, and a pair of UWB mixers driven by a pair of wideband LO drivers, is fabricated in a 90nm digital CMOS process. The passive inductorless two-stage UWB LNA, three-stage UWB LNA and UWB front-end occupy chip areas of only 0.0114mm2, 0.0227mm2, and 0.1485mm2, respectively. The active CMOS UWB front-end exhibits a measured flat gain of 22.5dB over 2.5-8.8 GHz bandwidth, and its tunability allows for varying the gain and bandwidth. / Integrated Circuits and Systems

Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads.

Orthogonal frequency division multiplexing (OFDM) is the major technique for next generation wireless communication system because of its high spectral efficiency. In addition, multiple-input multiple-output (MIMO) technique is usually used to further increase system capacity. There are two major coding schemes adopted in MIMO-OFDM systems, i.e. space-time block code (STBC) and space-frequency block code (SFBC). This thesis investigates the orthogonal-space-frequency block code OFDM (OSFBC-OFDM) system. In SFBC-OFDM systems, the channel frequency response is usually assumed to be the same for adjacent subcarriers. However, this assumption is not valid in frequency-selective fading environment. Therefore, the orthogonality of code structure is destroyed, leading to substantial increase in interference and significant decrease in system performance. This thesis proposes a receiver equalizer which adopts an interference cancellation (IC) mechanism to maximize the signal to interference plus noise ratio (SINR). Both the Lagrange multiplier method and eigenvalue method are adopted in the interference cancellation. Simulation experiments are conducted to verify the system performance and results demonstrate that the SINR performance is dramatically improved.