Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads.

Orthogonal frequency division multiplexing (OFDM) is the major technique for next generation wireless communication system because of its high spectral efficiency. In addition, multiple-input multiple-output (MIMO) technique is usually used to further increase system capacity. There are two major coding schemes adopted in MIMO-OFDM systems, i.e. space-time block code (STBC) and space-frequency block code (SFBC). This thesis investigates the orthogonal-space-frequency block code OFDM (OSFBC-OFDM) system. In SFBC-OFDM systems, the channel frequency response is usually assumed to be the same for adjacent subcarriers. However, this assumption is not valid in frequency-selective fading environment. Therefore, the orthogonality of code structure is destroyed, leading to substantial increase in interference and significant decrease in system performance. This thesis proposes a receiver equalizer which adopts an interference cancellation (IC) mechanism to maximize the signal to interference plus noise ratio (SINR). Both the Lagrange multiplier method and eigenvalue method are adopted in the interference cancellation. Simulation experiments are conducted to verify the system performance and results demonstrate that the SINR performance is dramatically improved.

For many years batteries have been used as the main power sources for portable electronic devices. However, the rate of scaling in integrated circuits and micro-electro-mechanical systems (MEMS) has been much higher than that of the batteries technology. Therefore, a need to replace these temporary energy reservoirs with small sized continuously charged energy supply units has emerged. These units, named as energy harvesters, use several types of ambient energy sources such as heat, light, and vibration to provide energy to intelligent systems such as sensor nodes. Among the available types, vibration based electromagnetic (EM) energy harvesters are particularly interesting because of their simple structure and suitability for operation at low frequency values (&lt / 10 Hz), where most vibrations exits. However, since the generated EM power and voltage is relatively low at low frequencies, high performance interface electronics is required for efficiently transferring the generated power from the harvester to the load to be supplied. The aim of this study is to design low power and efficient interface electronics to convert the low voltage and low power generated signals of the EM energy harvesters to DC to be usable by a real application. The most critical part of such interface electronics is the AC/DC converter, since all the other blocks such as DC/DC converters, power managements units, etc. rely on the rectified voltage generated by this block. Due to this, several state-of-the-art rectifier structures suitable for energy harvesting applications have been studied. Most of the previously proposed rectifiers have low conversion efficiency due to the high voltage drop across the utilized diodes. In this study, two rectifier structures are proposed: one is a new passive rectifier using the Boot Strapping technique for reducing the diode turn-on voltage values / the other structure is a comparator-based ultra low power active rectifier. The proposed structures and some of the previously reported designs have been implemented in X-FAB 0.35 &micro / m standard CMOS process. The autonomous energy harvesting systems are then realized by integrating the developed ASICs and the previously proposed EM energy harvester modules developed in our research group, and these systems have been characterized under different electromechanical excitation conditions. In this thesis, five different systems utilizing different circuits and energy harvesting modules have been presented. Among these, the system utilizing the novel Boot Strap Rectifier is implemented within a volume of 21 cm3, and delivers 1.6 V, 80 &micro / A (128 &micro / W) DC power to a load at a vibration frequency of only 2 Hz and 72 mg peak acceleration. The maximum overall power density of the system operating at 2 Hz is 6.1 &micro / W/cm3, which is the highest reported value in the literature at this operation frequency. Also, the operation of a commercially available temperature sensor using the provided power of the energy harvester has been shown. Another system utilizing the comparator-based active rectifier implemented with a volume of 16 cm3, has a dual rail output and is able to drive a 1.46 V, 37 &micro / A load with a maximum power density of 6.03 &micro / W/cm3, operating at 8 Hz. Furthermore, a signal conditioning system for EM energy harvesting has also been designed and simulated in TSMC 90 nm CMOS process. The proposed ASIC includes a highly efficient AC-DC converter as well as a power processing unit which steps up and regulates the converted DC voltages using an on-chip DC/DC converter and a sub-threshold voltage regulator with an ultra low power management unit. The total power consumption on the totally passive IC is less than 5 &micro / W, which makes it suitable for next generation MEMS-based EM energy harvesters. In the frame of this study, high efficiency CMOS rectifier ICs have been designed and tested together with several vibration based EM energy harvester modules. The results show that the best efficiency and power density values have been achieved with the proposed energy harvesting systems, within the low frequency range, to the best of our knowledge. It is also shown that further improvement of the results is possible with the utilization of a more advanced CMOS technology.

Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.

Αντικείμενο της παρούσας Ειδικής Επιστημονικής Εργασίας είναι η μελέτη, σχεδίαση, εξομοίωση και φυσική σχεδίαση ενός αναλογικού μιγαδικού ζωνοδιαβατού φίλτρου 6ης τάξης. Βασικές δομικές μονάδες του φίλτρου είναι ενισχυτές ρεύματος οι οποίοι χρησιμοποιούν τη βαθμίδα “Flipped Voltage Follower”. Με τη συγκεκριμένη βαθμίδα είναι εφικτή η σχεδίαση όλων των επιμέρους κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας-χαμηλής κατανάλωσης ισχύος. / The subject of this master thesis is the design, simulation and physical layout of a 6th order analog complex bandpass filter. The filter is constructed by current mirrors which are utilizing the cell "Fliped Voltage Follower". Thus, all of the circuits offer the benefit of operating in low-voltage/low-power environment.

No description available.

Le travail de doctorat réalisé s'attache à étudier les nouveaux types d'interconnexions comme les TSV (Through Silicon Via), les lignes de redistribution (RDL) et les piliers de cuivre (Cu-Pillar) présentes dans le domaine de l'intégration 3D en microélectronique avancée, par exemple pour des applications de type " imager " où une puce " capteur optique " est empilée sur une puce " processeur ". Afin de comprendre et quantifier le comportement électrique de ces nouveaux composants d'interconnexion, une première problématique de la thèse s'articulait autour de la caractérisation électrique, sur une très large bande de fréquence (10 MHz - 60 GHz) de ces éléments, enfouis dans leurs environnements complexes d'intégration, en particulier avec l'analyse de l'impact des pertes dans les substrats de silicium dans une gamme de conductivités allant de très faible (0 S/m) à très forte (10 000 S/m). Par la suite, une nouvelle problématique prend alors naissance sur la nécessité de développer des modèles mathématiques permettant de prédire le comportement électrique des interconnexions 3D. Les modèles électriques développés doivent tenir compte des pertes, des couplages ainsi que de certains phénomènes liés à la montée en fréquence (courants de Foucault) en fonction des caractéristiques matériaux, des dimensions et des architectures (haute à faible densité d'intégration). Enfin, à partir des modèles développés, une dernière partie propose une étude sur les stratégies de routage dans les empilements 3D de puces à partir d'une analyse sur l'intégrité de signaux. En opposant différents environnements, débit de signaux binaires ou dimensions des TSV et des RDL des conclusions émergent sur les stratégies à adopter pour améliorer les performances des circuits conçus en intégration 3D.

Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.

Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads.

本論文研究目的在於瞭解台灣IC產業聚集以及透過聚集構成的技術合作、專利引用網絡對於創新能力的影響，並且試圖回答以下的研究問題：台灣IC產業的地區空間分佈呈現什麼樣的型態?是否呈現空間的聚集性?台灣IC產業的技術合作網絡呈現何種區域化特性?台灣IC產業的上、中、下游，技術合作與競爭網絡的模式有何差異?台灣IC產業的聚集特性、技術合作與技術競爭網絡的性質，對創新的影響為何? 透過分析IC上市公司於2001~2009年的組織特性、技術合作契約與專利引用資料，本論文得到以下主要研究結論：(一) 台灣的IC業除了高比例聚集在新竹科學園區之外，在技術合作、專利授權等正式契約合作關係中也會傾向與台灣北部、美國矽谷與東北的聚集對象合作。(二) 台灣IC產業在技術合作與專利引用方面均具備高度網絡聯結的性質，且明顯有中游IC製造廠商帶動上游IC設計商與下游IC封測商發展的特性。(三) 比起產業聚集，技術網絡更能解釋影響IC廠商創新能力的因素，與較多不同地區的對象合作、掌握關鍵專利的廠商，創新能力的投入(研發經費)、產出(核准專利)與強度(技術優勢)越強。