對晶圓代工產業而言：生產的彈性及穩定的高良率是競爭優勢之所在，為維持這兩項核心能力，企業必須持續改進製程以提高生產績效。Vadgama, Trybula (1996)曾對晶圓廠生產績效之改善提出建議方案：作者認為將模型工具與作業制成本制整合的管理方式，可辨認出對生產績效具有重大影響的生產區域，再以作業分析找出影響因素並提出相對應的解決方案，進而達到持續改善的目標。 本研究擬以個案公司作業制成本制為分析的基礎資訊系統，以「作業」的資訊進行生產績效影響因素的分析，期能分析出生產績效的影響因子，並找出其與生產績效之關係，管理當局即可根據策略目標，藉由持續改善影響因素來達成企業的生產績效目標。 本研究係以實地(Field)及實地實證(Field Empirical)研究的方式進行，以國內某積體電路製造公司為研究對象。並透過實地對個案公司進行觀察、訪談及書面閱讀的方式，瞭解個案公司特色，以形成本研究的研究假說。 本研究將晶圓廠內影響生產績效的因素分為排程因素、派工因素及監控因素三大類。 （一）排程因素對生產績效之影響 就排程因素來看，生產需求影響生產計畫，因此產品複雜性、生產控制活動可能都是生產排程必須考量的因素，而這些因素亦可能進一步對生產績效造成影響。 （二）派工因素對生產績效之影響 就生產現場而言，原料投入時點、機台派工規則、機台運用狀況及批量大小等因素都會綜合影響生產效率與效果，因此若能有系統的將這些因素組織起來，再進一步探討其對生產績效的影響程度高低，將有助管理者決定改善的重點及資源的調配。 （三）監控因素對生產績效之影響 晶圓製造過程要求之精密度、潔淨度相當高，也使得製程中常有許多無法預期的變異發生，因此「檢查」、「重製」與「廢棄」可視為晶圓製造過程中的必要支出。 透過迴歸分析，本研究之結果如下： （一）排程因素對生產績效之影響 排程因素之代理變數包括：製程技術、光罩層數、製程優先順序與製程配方種類數。 就成本、生產週期時間與良率而言：緊急批量制度之採用確實能達到縮短生產週期時間的效果，但是卻會增加該批量之生產成本且降低其良率表現。 就成本因素而言：製程技術愈複雜、光罩層數愈多、製程配方筆數愈多，生產成本自然較高。 就生產週期時間而言︰顯示光罩層數每多一層，約需多耗費一個工作天；製程技術複雜性與製程配方筆數並不會影響生產週期時間，這樣的訊息對於交期的評估將具有一定的參考價值。 就良率而言︰愈新世代製程、製程配方筆數愈多，其良率表現愈差。 （二）派工因素對生產績效之影響 派工因素之代理變數包括：批量大小、批次待機時間、保養維護時間與當機時間。 就成本、生產週期時間與良率而言：保養維護時間愈短將可反應出較低的成本、較短的生產週期時間與較高的良率表現。 就成本而言︰批量愈接近滿批（25片），該批之總成本愈低，顯示控片、擋片等間接物料之支出，在ABC制度下獲得充分反應，相當值得生產單位進行併單、拆單時之參考︰「批次待機時間」之結論並不合理，經訪談廠方工程師後發現：樣本選取期間之產能利用率達100%，此時之待機時間相當短（每批次之平均值為0.98秒），此變數之具體影響必須進一步研究，才能得到驗證。 就良率而言︰愈接近滿批，良率表現愈佳，這應該也是控片、擋片制度採用之原因︰就「批次待機時間」而言，樣本期間之待機時間相當短，無法據以判斷對良率之影響︰而「當機時間」未達顯著水準，意味著無法解釋良率之變化。 （三）監控因素對生產績效之影響 監控因素之代理變數為晶圓重製片數。 晶圓重製決策將具體影響生產成本；晶圓重製與否無法據以解釋生產週期時間之長短；就良率而言︰重製與良率之間並未具有解釋關係。 根據實地實證研究結論，針對個案公司與後續研究者之建議如下所述： （一）對個案公司之建議 本研究所選定之影響變數可分為幾類，包括：產品特性相關，如製程技術複雜性與光罩層數；作業動因相關，如待機時間、保養維護時間、當機時間；生產管理相關：緊急批量、批量大小、機台設定次數、晶圓重製。 1.產品特性相關 若能以ABC為骨幹，結合作業分析與上述實證結果，在市場導向與目標成本概念下，組成跨功能之產品開發團隊，不僅能縮短開發時間，降低技術移轉造成之誤差，並在短期內提升新製程技術的生產績效，保有生產高複雜性產品組合所應具備之彈性。 就「獲利分析」而言，透過ABC成本資訊，依顧客獲利分析、產品獲利分析之結論，作為客戶篩選與產品技術組合比重之參考。 2.作業動因 在ABC系統下，應可建立作業動因分析的機制，據以評估待機時間、保養維護時間與當機時間之影響及效益，若能藉此導入品質成本之概念，將過去品質管理之相關措施，以預防性支出、鑑定性支出、內部失敗成本、外部失敗成本等方式將品質作業具體數字化，透過定期的覆核與檢視，不僅能評估品質保證暨可靠性政策之成本效益，亦能滿足管理者進行例外管理之需求。 3.生產管理制度 依此模式建立一套生產績效影響因素之分析模型，透過統計方法，分析各變數對績效表現之具體影響為何？並排定解決上述問題之優先順序，進行專案管理，若再加上ABC所提供之作業分析資訊，將能使問題的焦點明確至作業(Activity)層級，自然能兼具"Do The Right Things"及"Do The Things Right"之效。 （二）對未來研究之建議 1.依生產區域，進行影響因素之分析，研究結果將更具管理價值。 2.透過實證模型發展出一套綜合生產績效指標，以滿足績效管理之需求。 3.以品質成本之概念，配合作業制成本制之作業屬性，分析預防性支出、鑑定性支出、內部失敗成本與外部失敗成本對生產績效表現之影響。

Nano scale processing of IC chips has become the prime production technique as the microelectronic industry aims towards scaling down product dimensions while increasing accuracy and performance. Accurate control of temperature and a good monitoring mechanism for thickness of the deposition layers during epitaxial growth are critical parameters influencing a good yield. The two-fold objective of this thesis is to establish the feasibility of an alternative to the current pyrometric and ellipsometric techniques to simultaneously measure temperature and thickness during wafer processing. TAP-NDE is a non-contact, non-invasive, laser-based ultrasound technique that is employed in this study to contemporarily profile the thermal and spatial characteristics of the wafer. The Gabor wavelet transform allows the wave dispersion to be unraveled and the group velocity of individual frequency components to be extracted from the experimentally acquired time waveform. The thesis illustrates the formulation of a theoretical model that is used to identify the frequencies sensitive to temperature and thickness changes. The group velocity of the corresponding frequency components is determined and their corresponding changes with respect to temperature for different thickness are analytically modeled. TAP-NDE is then used to perform an experimental analysis on Silicon wafers of different thickness to determine the maximum possible resolution of TAP-NDE towards temperature sensitivity, and to demonstrate the ability to differentiate between wafers of different deposition layer thickness at temperatures up to 600?C. Temperature resolution is demonstrated for ?10?C resolution and for ?5?C resolution; while thickness differentiation is carried out with wafers carrying 4000? and 8000? of aluminum deposition layer. The experimental group velocities of a set of selected frequency components extracted using the Gabor Wavelet time-frequency analysis as compared to their corresponding theoretical group velocities show satisfactory agreement. As a result of this work, it is seen that TAP-NDE is a suitable tool to identify and characterize thickness and temperature changes simultaneously during thermal annealing that can replace the current need for separate characterization of these two important parameters in semiconductor manufacturing.

Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime silicon wafers for the IC industry. Lately, other substrates, such as silicon-on-insulator has become in use which requires a greater control of the silicon CMP process. CMP is used to planarize oxide interlevel dielectric and to remove excessive tungsten after plug filling in the Al interconnection technology. In Cu interconnection technology, the plugs and wiring are filled in one step and excessive Cu is removed by CMP. In front end processing, CMP is used to realize shallow trench isolation (STI), to planarize trench capacitors in dynamic random access memories (DRAM) and in novel gate concepts. This thesis is focused on CMP for front end processing, which is the processing on the device level and the starting material. The effects of dopants, crystal orientation and process parameters on silicon removal rate are investigated. CMP and silicon wafer bonding is investigated. Also, plasma assisted wafer bonding to form InP MOS structures is investigated. A complexity of using STI in bipolar and BiCMOS processes is the integration of STI with deep trench isolation (DTI). A process module to realize STI/DTI, which introduces a poly CMP step to planarize the deep trench filling, is presented. Another investigated front end application is to remove the overgrowth in selectively epitaxially grown collector for a SiGe heterojunction bipolar transistor. CMP is also investigated for rounding, which could be beneficial for stress reduction or to create microoptical devices, using a pad softer than pads used for planarization. An issue in CMP for planarization is glazing of the pad, which results in a decrease in removal rate. To retain a stable removal rate, the pad needs to be conditioned. This thesis introduces a geometrically defined abrasive surface for pad conditioning.

This thesis treats the development of packaging and integration methods for the cost-efficient encapsulation and packaging of microelectromechanical (MEMS) devices. The packaging of MEMS devices is often more costly than the device itself, partly because the packaging can be crucial for the performance of the device. For devices which contain liquids or needs to be enclosed in a vacuum, the packaging can account for up to 80% of the total cost of the device. The first part of this thesis presents the integration scheme for an optical dye thin film NO2-gas sensor, designed using cost-efficient implementations of wafer-scale methods. This work includes design and fabrication of photonic subcomponents in addition to the main effort of integration and packaging of the dye-film. A specific proof of concept target was for NO2 monitoring in a car tunnel. The second part of this thesis deals with the wafer-scale packaging methods developed for the sensing device. The developed packaging method, based on low-temperature plastic deformation of gold sealing structures, is further demonstrated as a generic method for other hermetic liquid and vacuum packaging applications. In the developed packaging methods, the mechanically squeezed gold sealing material is both electroplated microstruc- tures and wire bonded stud bumps. The electroplated rings act like a more hermetic version of rubber sealing rings while compressed in conjunction with a cavity forming wafer bonding process. The stud bump sealing processes is on the other hand applied on completed cavities with narrow access ports, to seal either a vacuum or liquid inside the cavities at room temperature. Additionally, the resulting hermeticity of primarily the vacuum sealing methods is thoroughly investigated. Two of the sealing methods presented require permanent mechanical fixation in order to complete the packaging process. Two solutions to this problem are presented in this thesis. First, a more traditional wafer bonding method using tin-soldering is demonstrated. Second, a novel full-wafer epoxy underfill-process using a microfluidic distribution network is demonstrated using a room temperature process. / <p>QC 20130325</p>

Bacterial adhesion is the first step of biofilm formation and in the focus of research interest since several decades. Biofilms cause many problems, sometimes dramatic, for example in health, food packing or waste water purification. Despite of high interest, bacterial adhesion process is only poorly understood yet. In this work, bacterial adhesion was investigated on well-organized and structured model surfaces with various chemistries at molecular scale. For that purpose a characterization methodology was developed to sufficiently analyze monolayers on silicon wafers, and controlled mixed monolayers surfaces with different densities of NH 2 backfilled with CH3 were developed and optimized. These controlled surfaces with different densities of 0 % NH2 up to 100% NH2 were eventually used as tool to study bacterial adhesion in batch and real time conditions. The results demonstrate a significant impact on bacterial adhesion of weak difference in the surface chemistry at molecular scale. In the batch experiments, two so-called "plateaus" zones were determined, in which bacterial adhesion is not significantly different despite the change of the amine concentration on the surface. On the contrary, one transition zone exists between the "plateaus" in which a slight chunge.in the amine concentration leads to a significant increase / decrease of the bacterial adhesion. The same trend of bacteria behavior was observed for different bacterial strains.

This thesis presents the development of wafer level vacuum packaging processes using Au-Si eutectic and glass frit bonding contributing to the improvement of packaging concepts for a variety of MEMS devices. In the first phase of this research, micromachined resonators and pirani vacuum gauges are designed for the evaluation of the vacuum package performance. These designs are verified using MATLAB and Coventorware finite element modeling tool. Designed resonators and pirani vacuum gauges and previously developed gyroscopes with lateral feedthroughs are fabricated with a newly developed Silicon-On-Glass (SOG) process. In addition to these, a process for the fabrication of similar devices with vertical feedthroughs is initiated for achieving simplified packaging process and lower parasitic capacitances. Cap wafers for both types of devices with lateral and vertical feedthroughs are designed and fabricated. The optimization of Au-Si eutectic bonding is carried out on both planar and non-planar surfaces. The bonding quality is evaluated using the deflection test, which is based on the deflection of a thinned diaphragm due to the pressure difference between inside and outside the package. A 100% yield bonding on planar surfaces is achieved at 390&ordm / C with a v holding time and bond force of 60 min and 1500 N, respectively. On the other hand, bonding on surfaces where 0.15&mu / m feedthrough lines exist can be done at 420&ordm / C with a 100% yield using same holding time and bond force. Furthermore, glass frit bonding on glass wafers with lateral feedthroughs is performed at temperatures between 435-450&ordm / C using different holding periods and bond forces. The yield is varied from %33 to %99.4 depending on the process parameters. The fabricated devices are wafer level vacuum packaged using the optimized glass frit and Au-Si eutectic bonding recipes. The performances of wafer level packages are evaluated using the integrated gyroscopes, resonators, and pirani vacuum gauges. Pressures ranging from 10 mTorr to 60 mTorr and 0.1 Torr to 0.7 Torr are observed in the glass frit packages, satisfying the requirements of various MEMS devices in the literature. It is also optically verified that Au-Si eutectic packages result in vacuum cavities, and further study is needed to quantify the vacuum level with vacuum sensors based on the resonating structures and pirani vacuum gauges.

Accelerometer sensors fabricated with micromachining technologies started to take place of yesterday&rsquo / s bulky sensors in many application areas. The application areas include a wide range from consumer electronics and health systems to military and aerospace applications. Therefore, the performance requirements extend form 1 &mu / g&rsquo / s to 100 thousand g&rsquo / s. However, high performance strategic grade MEMS accelerometer sensors still do not exist in the literature. Smart designs utilizing the MEMS technology is necessary in order to acquire high performance specifications. This thesis reports a high performance accelerometer with a new process by making the use of bulk micromachining technology. The new process includes the utilization of Silicon-on-Insulator (SOI) wafer and its buried oxide (BOX) layer. The BOX layer helps to realize interdigitated finger structures, which commonly find place in surface micromachined CMOS-MEMS capacitive accelerometers. The multi-metal layered CMOS-MEMS devices inherently incorporate interdigitated finger structures. Interdigitated finger structures are highly sensitive to acceleration in comparison with comb-finger structures, which generally find usage in bulk-micromachined devices, due to absence of anti-gap. The designed sensors based on this fabrication process is sought to form a fully-differential signal interfaced sensor with incorporation of the advantages of high sensitive interdigitated finger electrodes and high aspect ratio SOI wafer&rsquo / s bulk single crystal silicon device. Under the light of the envisaged process, sensor designs were made, and verified using a computing environment, MATLAB, and a finite element analysis simulator, CoventorWARE. The verified two designs were fabricated, and all the tests, except the centrifuge test, were made at METU-MEMS Research Center. Among the fabricated sensors, the one designed for the high performance achieves a capacitance sensitivity of 178 fF with a rest capacitance of 8.1 pF by employing interdigitated finger electrodes, while its comb-finger implementation can only achieve a capacitance sensitivity of 75 fF with a rest capacitance of 10 pF.

Nano scale processing of IC chips has become the prime production technique as the microelectronic industry aims towards scaling down product dimensions while increasing accuracy and performance. Accurate control of temperature and a good monitoring mechanism for thickness of the deposition layers during epitaxial growth are critical parameters influencing a good yield. The two-fold objective of this thesis is to establish the feasibility of an alternative to the current pyrometric and ellipsometric techniques to simultaneously measure temperature and thickness during wafer processing. TAP-NDE is a non-contact, non-invasive, laser-based ultrasound technique that is employed in this study to contemporarily profile the thermal and spatial characteristics of the wafer. The Gabor wavelet transform allows the wave dispersion to be unraveled and the group velocity of individual frequency components to be extracted from the experimentally acquired time waveform. The thesis illustrates the formulation of a theoretical model that is used to identify the frequencies sensitive to temperature and thickness changes. The group velocity of the corresponding frequency components is determined and their corresponding changes with respect to temperature for different thickness are analytically modeled. TAP-NDE is then used to perform an experimental analysis on Silicon wafers of different thickness to determine the maximum possible resolution of TAP-NDE towards temperature sensitivity, and to demonstrate the ability to differentiate between wafers of different deposition layer thickness at temperatures up to 600?C. Temperature resolution is demonstrated for ?10?C resolution and for ?5?C resolution; while thickness differentiation is carried out with wafers carrying 4000? and 8000? of aluminum deposition layer. The experimental group velocities of a set of selected frequency components extracted using the Gabor Wavelet time-frequency analysis as compared to their corresponding theoretical group velocities show satisfactory agreement. As a result of this work, it is seen that TAP-NDE is a suitable tool to identify and characterize thickness and temperature changes simultaneously during thermal annealing that can replace the current need for separate characterization of these two important parameters in semiconductor manufacturing.

Long cycle times in semiconductor manufacturing represent an increasing challenge for the industry and lead to a growing need of break-through approaches to reduce it. Small lot sizes and the conversion of batch processes to mini-batch or single-wafer processes are widely regarded as a promising means for a step-wise cycle time reduction. Our analysis with discrete-event simulation and queueing theory shows that small lot size and the replacement of batch tools with mini-batch or single wafer tools are beneficial but lot size reduction lacks persuasive effectiveness if reduced by more than half. Because the results are not completely convincing, we develop a new semiconductor tool type that further reduces cycle time by lot streaming leveraging the lot size reduction efforts. We show that this combined approach can lead to a cycle time reduction of more than 80%.

In der vorliegenden Arbeit wird ein neues Verfahren zur Dünnschichtverkappung von oberflächennahen Mikrostrukturen vorgestellt. Ausgehend von den speziellen Anforderungen an die Verkappung oberflächennaher Mikrostrukturen, insbesondere von Strukturen mit hohem Aspektverhältnis, wurden die Verwendung eines Fluor-Kohlenstoff-Polymers als Opferschichtmaterial und die Eignung unterschiedlicher Schichtstapel zur Realisierung der Dünnschichtkappe untersucht. Die resultierende Technologie ermöglicht eine durchgehend trockenchemische Prozessierung. Für die Abschätzung der notwendigen Schichtdicken und den geometrischen Entwurf der Kappenstrukturen, wurden auf Basis der Plattentheorie analytische und numerische Modelle erstellt. Verschiedene Materialkombinationen bestehend aus Siliziumoxid, Siliziumnitrid und Aluminium wurden hinsichtlich ihrer mechanischen und thermomechanischen Eigenschaften untersucht und bewertet. Ein weiterer Schwerpunkt lag auf der Entwicklung und Optimierung der Opferschichtprozesse, sowie deren Integration in die Gesamttechnologie. Die Eignung der plasmagestützten Prozesse zur Abscheidung und Strukturierung des Opferpolymers wurde durch die Fertigung von verkapselten Beschleunigungssensoren nachgewiesen. Ein ausreichender hermetischer Verschluss der Dünnschichtkappe konnte durch die Messung der viskosen Dämpfung an Feder-Masse-Schwingern bestätigt werden.