como cidades inteligentes e Internet das coisas demonstram que esta tecnologia está evoluindo em larga escala. Consequentemente, diversas aplicações desta tecnologia estão sendo desenvolvidas, muitas delas são altamente dependentes de redes de sensores sem fio, pois fazem a coleta de dados em ambientes inóspitos ou de difícil acesso. Para que estes dados coletados de diversos dispositivos possam ser analisados em conjunto é preciso que as coletas sejam simultâneas ou em intervalos próximos de tempo, o que implica que toda a rede de sensores tenha uma elevada precisão no sincronismo. Ademais, diversos protocolos de comunicação sem fio utilizam o sincronismo para estabelecer o compartilhamento do meio de propagação, tendo assim uma maior eficiência na troca de dados. Ao observar a importância de atender a essa necessidade de sincronização de tempo entre dispositivos usados em redes de sensores sem fio, este trabalho se concentra na proposta, implementação e teste de um serviço de sincronização de tempo para redes de sensores sem fio de baixa potência usando relógios de baixa frequência em tempo real em cada nó. Para implementar este serviço, são propostos três algoritmos baseados em estratégias diferentes para alcançar a sincronização desejada. O primeiro baseia-se em uma métrica simples de correção adaptativa; o segundo baseia-se em um mecanismo de predição; já o terceiro utiliza um mecanismo mais complexo, a correção analítica. Todos os algoritmos tem o mesmo objetivo: fazer com que os relógios dos nós sensores convirjam de forma ágil, em seguida, mantê-los com a maior similaridade possível. O objetivo deste trabalho é apresentar o melhor método que garanta a sincronização, mantendo o baixo consumo de energia em uma rede de sensores. Os resultados experimentais fornecem evidências do sucesso no cumprimento deste objetivo, bem como fornece meios para comparar estas três abordagens considerando os melhores resultados de sincronização e os seus custos em termos de consumo de energia. / Environmental monitoring systems are gaining more and more space, concepts such as smart cities and the Internet of things demonstrate that this technology has been developing a lot. Consequently, many applications of this technology are being developed, many of them are dependent on wireless sensor networks, which collect data in inhospitable or difficult-to-access environments. In order to these collected data from several devices to be analyzed together it is necessary that the data collection be simultaneous or at close intervals, which implies that the entire network of sensors has a high precision in the synchronism. In addition, several wireless communication protocols use the synchronism to establish sharing of medium networks, thus having a greater efficiency in the exchange of data. Observing the importance of time synchronization, this work focuses in proposing, implementing and testing time synchronization protocols for low power wireless sensor networks using real time low frequency clocks. To implement this service, three algorithms based on different strategies are proposed to achieve the desired synchronization. The first is based on the simple metric for self-correction; the second is based on a prediction mechanism; while the third uses a more complex mechanism for analytical correction. All the algorithms have the same goal: to make the clock of the sensor nodes converge in an agile way, then to keep them with the greatest possible similarity. The objective of this work is to present the best method to guarantee the synchronization, keeping the low power consumption in a network, sporadically, transmissions. The experimental results provide evidence of success in achieving this goal, as well as providing means to compare these three approaches considering the best synchronization results and their costs in terms of energy consumption. Keywords: Internet of things.

Introdução: A terapia com laser de baixa potência (LBP) vem sendo utilizada em Odontologia com diversos objetivos, em especial o de diminuir o tempo de cicatrização de feridas cirúrgicas. Objetivo: O objetivo do presente estudo in vivo foi avaliar qualitativamente e quantitativamente o efeito da irradiação com LBP no processo de remodelação óssea após a extração dentária em ratos jovens. Material e Método: Foram utilizados 60 ratos Wistar, distribuídos aleatoriamente nos seguintes grupos: Grupo Controle (n=30) animais com extração dentária sem aplicação do LBP, e Grupo Experimental (n=30) animais que tiveram extração dentária (Ext) e aplicação do LBP (Ext+LBP) nos três primeiros dias (54 J/cm2 por dia). Os animais foram sacrificados nos períodos de 1, 2, 3, 5, 7 e 10 dias após o procedimento de extração dentária. Neste estudo foram analisados os efeitos da aplicação do laser sobre o reparo alveolar através de microscopia de luz, luz polarizada e imunomarcação. Para isso foram avaliados os seguintes parâmetros: 1) porcentagem de formação óssea no interior do alvéolo; 2) grau de processo inflamatório; 3) grau de amadurecimento do colágeno; 4) imunomarcação para TRAP e RUNX-2. Todos os resultados obtidos foram submetidos à análise estatística através do teste ANOVA e teste de Mann-Whitney U (p<0.05). Resultados: Observou-se que os alvéolos do Grupo Experimental apresentaram processo de reparo mais evoluído quando comparados ao Grupo Controle, caracterizado pela organização mais rápida do coágulo sanguíneo, proliferação de fibroblastos nos restos do ligamento periodontal mais pronunciada, organização do colágeno e formação óssea mais precoce e mais intensa. Conclusão: A utilização do laser de baixa potência acelerou o processo de formação óssea durante as fases iniciais do experimento, embora nos períodos finais não houve diferença no processo de ossificação. / Introduction: Low Power Laser (LPL) therapy has been used in Dentistry to achieve many objectives, particularly to decrease the healing period on wound healing. Objectives: The purpose of this in vivo study was to evaluate qualitatively and quantitatively the irradiation effect with LPL in the bone remodeling process after tooth extraction in young rats. Material and Method: 60 Wistar rats were used, randomly distributed in the following groups: Control Group (n=30) animals with tooth extraction without LPL application, and Experimental Group (n=30) animals with tooth extraction (Ext) and LPL application (Ext+LPL) on the three fist days (54 J/cm2 per day). The animals were euthanized after the end periods of 1, 2, 3, 5, 7 and 10 days after the tooth extraction. This study looked into the effects of laser application on the alveolar repair through light microscopy, polarized light and immunostaining. After that, the following parameters were evaluated: 1) percentage of bone formation inside the dental alveolus; 2) degree of inflammatory process; 3) degree of collagen maturation; 4) immunostaining for TRAP and RUNX-2. All the results obtained were submitted to statistical analysis over the ANOVA and Mann- Whitney (p<0.05) test. Results: It was observed that the alveolus from the Experimental Group presented an improved repair process when compared to the Control Group, characterized by faster blood clot organization, more apparent fibroblasts proliferation on the remnants of the periodontal ligament, earlier and more intense collagen organization and bone generation. Conclusion: The use of Low Power Laser accelerated the bone generation process during the experimental initial period, although there was no difference in the ossification process in the final periods.

Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.

This thesis presents a new DC/AC inverter circuit which is based on a switched-capacitor circuit topology with reduced components (power switch and capacitor) count for low power applications. The proposed circuit has distinct features of both voltage boost-up and near sinusoidal (multi-level/staircase) AC output voltage. The main idea is to utilise a simple circuit technique called resonant-based Double Switch Single Capacitor Switched-Capacitor (DSSC SCC) with variable duty cycle Pulse Width Modulation (PWM) control technique in such a way that multi-level voltage can be realised across a capacitor. In order to show the superiority of the applied technique, comparisons with other techniques/circuits configurations are presented. The circuit technique can significantly reduce the number of multiple stages of switched-capacitor circuit cells of the recent switched-capacitor multi-level inverter topology. The proposed inverter (with integrated DSSC SCC technique) can generate a line-frequency with 13-levels near sinusoidal AC output voltage with low total harmonics distortion. The output voltage can be achieved with the least number of components use and only a single DC source is used as an input. The proposed inverter topology is also reviewed against other inverter-based switched-capacitor circuit topology and the well-known multi-level inverter topology. The proposed inverter has shown a tremendous reduction in the total harmonics distortion and circuit component count in comparison with the recent Switched-Capacitor Boost multi-level inverter and the classical Cascaded H-Bridge multi-level inverter. Mathematical analysis shows the design of the proposed inverter and PSPICE simulation result to verify the design is also presented. The practical experiment implementation of the proposed system is presented and proves the correct operation of the proposed inverter topology by showing consistency between simulation results and practical results.

Dagens stora miljöutmaningar i form av förbränning av fossila bränslen och medföljande koldioxidutsläpp har också gjort att många individer blivit allt mer miljömedvetna. Avancerade sensor för att mäta koldioxid finns numera på marknaden i form av lågenergiförbrukande alternativ som Senseairs LP8. Att utveckla firmware och att bedriva utveckling med sådana avancerade sensorer är något som inte är speciellt enkelt för vanliga användare. I detta projekt har en plattform byggd på bluetooth och enkla gratis utvecklingsverktyg tagits fram. Denna prototyp ugör en grund för utvecklingen av ett klimatsmycke där CO2 skall rapporteras till en molntjänst via mobiltelefon. Med prototypen har det utförts mätningar av strömförbrukningen genom att mäta urladdningstid av superkondensatorer, spänningsfallmätningar av cr2032 batterier samt kompletterande kapacitansmätningar av superkondensatorerna. Dessa mätningar visar att strömförbrukningen för prototypen ligger i intervallet 1-2 mA, beroende av vilka inställningar som önskas. Metoderna är väldigt enkla men ger en relativt god uppskattning av den totala strömförbrukningen.

This dissertation reports a high-speed wideband wireless transmission solution for the tight power constraints of cortical interface application. The proposed system deploysImpulse Radio Ultra-wideband (IR-UWB) technique to achieve very high-rate communication. However, impulse radio signals suffer from significant attenuation within the body,and power limitations force the use of very low-power receiver circuits which introduce additional noise and jitter. Moreover, the coils’ self-resonance has to be suppressed to minimize the pulse distortion and inter-symbol interference, adding significant attenuation. To compensate these losses, an Error correction code (ECC) layer is added for functioning reliably to the system. The performance evaluation is made by modeling a pair of physically fabricated coils, and the results show that the ECC is essential to obtain the system’s reliability. Furthermore, the gm/ID methodology, which is based on the complete exploration ofall inversion regions that the transistors are biased, is studied and explored for optimizingthe system at the circuit-level. Specific focuses are on the RF blocks: the low noise am-plifier (LNA) and the injection-locked voltage controlled oscillator (IL-VCO). Through the analytical deduction of the circuit’s features as the function of the gm/ID for each transistor, it is possible to select the optimum operating region for the circuit to achieve the target specification. Other circuit blocks, including the phase shifter, frequency divider,mixer, etc. are also described and analyzed. The prototype is fabricated in a 65-nm CMOS(Complementary Metal-Oxide-Semiconductor) process.

In this thesis, a new tool, named CHESS, is designed and developed for control and data-flow graph (CDFG) extraction and the high-level synthesis of VLSI systems. The tool consists of three individual modules for:(i) CDFG extraction, (ii) scheduling and allocation of the CDFG, and (iii) binding, which are integrated to form a comprehensive high-level synthesis system. The first module for CDFG extraction includes a new algorithm in which certain compiler-level transformations are applied first, followed by a series of behavioral-preserving transformations on the given VHDL description. Experimental results indicate that the proposed conversion tool is quite accurate and fast. The CDFG is fed to the second module which schedules it for resource optimization under a given set of time constraints. The scheduling algorithm is an improvement over the Tabu Search based algorithm described in [6] in terms of execution time. The improvement is achieved by moving the step of identifying mutually exclusive operations to the CDFG extraction phase, which, otherwise, is normally done during scheduling. The last module of the proposed tool implements a new binding algorithm based on a game-theoretic approach. The problem of binding is formulated as a non-cooperative finite game, for which a Nash-Equilibrium function is applied to achieve a power-optimized binding solution. Experimental results for several high-level synthesis benchmarks are presented which establish the efficacy of the proposed synthesis tool.

This PhD dissertation reports the development of miniature ion optics components of a mass spectrometer (MS) with the ultimate goal to lay the foundation for a compact low-power micromachined MS (µMS) for broad-range chemical analysis. Miniaturization of two specific components a) RF ion traps and b) an ion funnel have been investigated and miniature low-power versions of these components have been developed and demonstrated successfully in lab experiments. Power savings, simpler electronics and packaging schemes required to operate the micro-scale RF cylindrical ion traps have been the key motivation driving this research. Microfabricated cylindrical ion traps (µCITs) and arrays in silicon, silicon-on-insulator and stainless steel substrates have been demonstrated and average power of as low as 55 mW for a low mass range (28 to 136 amu) and mass spectra with better than a unit-mass-resolution have been recorded. For the ion funnel miniaturization effort, simple assembly, small form factor and ease of integration have been emphasized. A simplification of the conventional 3D ion funnel design, called the planar ion funnel, has been developed in a single plate and has been tested to demonstrate ion funneling at medium vacuum levels (1E-5 Torr) using DC voltages and power less than 0.5 W. Miniaturization of these components also enables use of other novel ion optics components, packaging and integration, which will allow a new class of µMS architectures amenable for radical miniaturization.

<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.</p>

<p>In this thesis a FIR filter generator has been designed. The program generates FIR filters in the form of VHDL-files. Four different filter structures have been implemented in the generator, Direct Form (DF), Differential Coefficients Method (DCM), polyphase filters and (2-by-2) filters. </p><p>The focus of the thesis was to implement filter structures that create FIR filters with as low power consumption and area as possible. </p><p>The generaterator has been implemented i C++. The C++ program creates text-files with VHDL-code. The user must then compile and synthesize the VHDL-files. The program uses an text-file with the filter coefficients as input.</p>