Este estudo teve por finalidade estudar os efeitos da fototerapia com laser em baixa intensidade (Low Level Laser Therapy LLLT) sobre a inflamação e reparação após lesão criogênica realizada no sitema nervoso central (SNC) de ratos. Foram realizados 3 experimentos. Em todos os experimentos foi utilizado um modelo de deformação cortical direta induzida por lesão criogênica. A LLLT foi realizada com laser de diodo em baixa intensidade emitindo no vermelho visível (InGaAlP, 660 nm) ou no infravermelho (AlGaAr, 780 nm). Os parâmetros de irradiação foram: potência de 40 mW, área do feixe de 0,04 cm2, densidades de energia de 3 J/cm2 (3 s) ou 5 J/cm2 (5 s) determinando energias por ponto de 0,12 J e 0,20 J, respectivamente. Foram realizadas 2 irradiações com intervalo de 3 h, no modo contato e em 2 pontos por lesão. No experimento 1, 50 ratos da linhagem Wistar foram utilizados para determinar os parâmetros de LLLT capazes de influenciar na dinâmica da produção de citocinas proinflamatórias (TNF-a, IL-1b, IL-6) e antiinflamatória (IL-10). As citocinas foram mensuradas pelo teste ELISA no cérebro e no sangue dos animais, 6 e 24h após a lesão. Os grupos experimentais foram: controle (não irradiado) e 4 grupos irradiados com 3 J/cm2 ou 5 J/cm2 para cada comprimento de onda (n=10 por grupo). Para os experimentos 2 e 3 foram utilizados 40 ratos (20 não irradiados controles e 20 irradiados). A LLLT foi realizada somente com o parâmetro de irradiação do laser no infravermelho e a densidade de energia de 3 J/cm2. Nestes experimentos o processo de reparação das lesões criogênicas no SNC foi acompanhado em 6 h, 1, 7 e 14 dias após a última irradiação (n=5 por grupo por tempo experimental). No experimento 2 foi realizada a análise morfométrica da região lesionada do SNC. No experimento 3 foi analisada a distribuição das células inflamatórias (linfócitos T, leucócitos e macrófagos). Os dados de cada experimento foram comparados estatísticamente por análise de variância (ANOVA) ou Kruskal-Wallis seguido dos testes de Tukey ou de Dunn, respectivamente (F=5%). O trauma criogênico foi capaz de criar lesões focais no córtex representadas por necrose, edema, hemorragia e infiltrado inflamatório. Os achados mais marcantes foram: no experimento 1 com a irradiação do laser no infravermelho e 3 J/ cm2, o TNF- a e a IL-6 se mantiveram nos mesmos níveis em 6 e 24 h, enquanto no controle houve aumento significativo. Experimento 2: as lesões não tratadas apresentaram maior perda tecidual em 6 h que as irradiadas. Experimento 3: as lesões irradiadas apresentaram menor quantidade de leucócitos e linfócitos T nas primeiras 24 h do que nas lesões controle. A quantidade de macrófagos foi similar nos dois grupos. Conclusões: Levando em consideração as condições experimentais deste estudo concluiu-se que LLLT exerce efeitos nos processos de inflamação e reparação diminuindo a concentração de citocinas próinflamatórias (TNF-F e IL-6) no sangue e mantendo a de IL-1I no cérebro. Adicionalmente, diminui a perda tecidual inicial pós- lesão criogênica e a infiltração inicial de leucócitos e linfócitos T. / This study aimed to study the effects of phototherapy with low-intensity laser (Low Level Laser Therapy - LLLT) on inflammation and repair after cryogenic injury held in central nervous system (CNS) of rats. There were 3 experiments. In all experiments a model of deformation induced by direct cortical cryogenic injury was used. The LLLT was carried out with a low intensity diode laser emitting in the visible red (InGaAlP, 660 nm) or infrared (AlGaAs, 780 nm). The irradiation parameters were: power of 40 mW, beam area of 0.04 cm2, energy densities of 3 J/cm2 (3 s) or 5 J/cm2 (5 s) providing energy per point of 0.12 J and 0.20 J, respectively. Two irradiations were performed at 3 h-intervals, in contact mode and in 2 points for lesion. In experiment 1, 50 Wistar rats were used to determine the parameters of LLLT able to influence the dynamics of production proinflammatory cytokines (TNF-, IL-1 and IL-6) and antiinflammatory cytokine (IL- 10). Cytokines were measured by ELISA in the brain and blood of animals, 6 and 24 hours after injury. The experimental groups were: control (non-irradiated) and 4 irradiated groups [3 J/cm2 and 5 J/cm2 for each wavelength (n = 10 per group)]. For experiments 2 and 3 40 rats (20 non-irradiated - controls and 20 irradiated).were used. The LLLT was performed only with the parameter of laser irradiation on the infrared and the energy density of 3 J/cm2. In these experiments, the process of repair of cryogenic injury in the CNS was followed in 6 h, 1, 7 and 14 days after the last irradiation (n = 5 per group and time trial). In experiment 2 a morphometric analysis of the injured area of the CNS was done. In experiment 3 the distribution of inflammatory cells (lymphocytes, leukocytes and macrophages) was analyzed. Data from each experiment were compared statistically by analysis of variance (ANOVA) or Kruskal-Wallis followed by tests of Tukey or Dunn, respectively ( = 5%). Cryogenic trauma was able to create focal lesions in the cortex represented by necrosis, edema, hemorrhage and inflammatory infiltrate. The most striking findings were: in experiment 1 with the laser irradiation in the infrared and 3 J/cm 2, TNF- and IL-6 remained at the same levels at 6 and 24 h, while in the control there was a significant increase. Experiment 2: untreated lesions showed greater tissue loss than irradiated lesions in 6 h. Experiment 3: lesions irradiated had fewer leukocytes and lymphocytes in the first 24 h than control lesions. The amount of macrophages was similar in both groups. Conclusions: Considering the experimental conditions of this study it was concluded that LLLT has effects in the processes of inflammation and repair by decreasing the concentration of proinflammatory cytokines (TNF- and IL-6) in blood and holding the IL-1 in the brain. Additionally, decreases the initial tissue loss after cryogenic injury and the initial infiltration of leukocytes and lymphocytes T.

Les récentes avancées technologiques des microphones de type microsystème électromécanique (MEMS) leurs permettent une utilisation sur une large gamme d’amplitudes sonores. Leur niveau de bruit ayant baissé, il devient possible de capter des sons provenant d’une distance plus lointaine, tandis que l’augmentation de leur pression acoustique maximale leur permet de ne pas saturer dans un environnement très bruyant de type concert ou évènement sportif. Ainsi le système électronique de conversion analogique-numérique connecté au microphone devient l’élément limitant les performances du système d’acquisition acoustique. Un besoin de nouvelles architectures de conversion analogique-numérique ayant une plage dynamique augmentée se fait donc ressentir. Par ailleurs, ces microphones étant de plus en plus utilisés dans des systèmes fonctionnant sur batterie, la contrainte de limitation de la consommation devient importante.Dans la bande de fréquences audio, les convertisseurs analogiques-numériques de type sigma-delta sont les plus aptes à obtenir une grande résolution combinée à une faible consommation. Ils sont divisés en deux grandes familles: ceux à temps discret utilisant principalement des circuits à capacités commutées, et ceux à temps continu utilisant des circuits classiques. Cette thèse se concentre sur l’étude et la conception de chacun des deux types de convertisseurs sigma delta, en insistant sur la faible consommation, le faible coût de production (surface occupée) et la robustesse du circuit, cela en vue d’une production de masse pour équipements portables.La conception d’un convertisseur analogique numérique de type sigma-delta à temps discret a été réalisé, ce dernier atteignant un rapport signal sur bruit de 100 décibels sur une bande de 24kHz, pour une puissance consommée de seulement 480μW. Pour limiter la consommation, de nouveaux amplificateurs à base d’inverseurs sont utilisés, et dont la robustesse contre les variations du procédé de fabrication ou de la température a été améliorée. Les spécifications ont été définies grâce au développement d’un modèle de haut-niveau précis, ce qui permet d’éviter le surdimensionnement tout en atteignant les performances voulues. Enfin, un grand ratio de suréchantillonnage a été choisi afin de réduire l’espace utilisé par les capacités commutées, minimisant le coût de fabrication.Après une étude théorique de l’équivalence entre les modulateurs sigma-delta à temps discret et à temps continu, ainsi que des spécificités propres aux modulateurs à temps continu, une réalisation de ces derniers a été effectuée. Celui-ci atteint un rapport signal sur bruit de 95 décibels sur une bande de fréquence de 24kHz, tout en consommant 142μW. Pour réduire la consommation ainsi que l’espace utilisé, un filtre de boucle du second-ordre a été réalisé avec un seul amplificateur, et le quantificateur fait aussi office d’intégrateur grâce à l’utilisation d’une structure d’oscillateurs contrôlés en tension. Ce quantificateur à base d’oscillateurs est réalisé par des cellules numériques, réduisant la consommation et l’espace utilisé, mais est hautement non-linéaire. Cette non-linéarité a été prise en compte par des choix architecturaux afin de ne pas réduire les performances finales du modulateur. / The recent technological advances in microelectromechanical system (MEMS) microphones allow them to be used on a large sound amplitude range. Due to their lower noise level, it becomes possible to capture sound from a faraway distance, while their increased acoustic overload point gives them the ability to capture sound without saturation in a loud environment like a concert or a sport event. Thus, the electronic analog / digital conversion system connected to the microphone becomes the limiting element of the acoustic acquisition system performance. There is then a need for a new analog / digital conversion architecture which has an increased dynamic range. Furthermore, since more and more of these microphones are used in battery-powered devices, the power consumption limitation constraint becomes of high importance.In the audio frequency band, the sigma-delta analog / digital converters are the ones most able to provide a high dynamic range combined to a limited power consumption. They are split in two families: the discrete-time ones using switched-capacitors circuits and the continuous-time ones using more classical structures. This thesis concentrates on the study and the design of both of these two types of sigma-delta converters, with an emphasis on the low-power consumption, the low production cost (area occupied) and the circuit robustness, in sight of a mass production for portable devices.A discrete-time sigma-delta modulator design has been made, the latter reaching a signal to noise ratio of 100dB on a 24kHz frequency bandwidth, for a power consumption of only 480μW. To limit the power consumption, new inverter-based amplifiers are used, with an improved robustness against the variations of the fabrication process or the temperature. Amplifier specifications are obtained thanks to an accurate high-level model developed, which allows to avoid over-design while ensuring that the wanted performances are reached. Finally, a large oversampling ratio has been used to reduce the switched-capacitors area, lowering the modulator cost.After a theoretical study of the equivalence between discrete-time and continuous-time modulators, and of continuous-time modulators specificities, a design of the latter has been made too. It reaches a signal to noise ratio of 95dB on a 24kHz bandwidth, while consuming 142μW. To reduce the power consumption and the occupied area, a second-order loop filter is implemented using a single amplifier, and the quantizer uses a VCO-based structure that provides inherently an integrating stage. The VCO-based quantizer is made using digital cells, lowering the consumption and area, but is highly non-linear. This non-linearity has been handled by architectural choices to not influence the final modulator performances.

L'augmentation de la densité des transistors dans les circuits électroniques conduit à une augmentation de la consommation d'énergie induisant des phénomènes thermiques plus complexes à maitriser. Dans le cas de systèmes embarqués en environnement où la température ambiante varie dans des proportions importantes (automobile par exemple), ces phénomènes peuvent conduire à des problèmes de fiabilité. Parmi les mécanismes de défaillance observés, on peut citer les cycles thermiques (CT) qui induisent des déformations dans les couches métalliques de la puce pouvant conduire à des fissurations. L’objectif de la thèse est de proposer pour des architectures de type multiprocesseur sur puce une technique de réduction des CT subis par les processeurs, et ce en respectant les contraintes temps réel des applications. L’exemple du circuit MPC5517 de Freescale a été considéré. Dans un premier temps un modèle thermique de ce circuit a été élaboré à partir de mesures par une caméra thermique sur ce circuit décapsulé. Un environnement de simulation a été mis en oeuvre pour permettre d’effectuer simultanément des analyses thermiques et d’ordonnancement de tâches et mettre en évidence l’influence de la température sur la puissance dissipée. Une heuristique globale pour réduire à la fois les CT et la température maximale des processeurs a été étudiée. Elle tient compte des variations de la température ambiante et se base sur les techniques DVFS et DPM. Les résultats de simulation avec les algorithmes d’ordonnancement globaux RM, EDF et EDZL et avec différentes charges processeur (sur un circuit type MPC5517 et un UltraSparc T1) illustrent l’efficacité de la technique proposée. / Increasing the density of transistors in electronic circuits leads to an increase in energy consumption resulting in more complex thermal phenomena to master. For systems embedded in environments where the ambient temperature can vary in large range (e.g. automotive), these thermal effects can induce reliability problems. Among classical failure mechanisms thermal cycles (CTs) produce deformations in materials and play a major role in the cracking of the metal layers in the chip. The aim of the thesis is to propose a reduction technique of CTs suffered by the processor cores in a multiprocessor on chip architecture such that real-time application constraints are met. The example of the Freescale MPC5517 circuit has been considered. In a first step a thermal model of this circuit was developed. This was achieved from measurements taken by a thermal camera on a decapsulated circuit. Next, a simulation environment has been implemented allowing both the analysis of thermal behavior and the scheduling of tasks so as to highlight the influence of temperature on the dissipated power. A global heuristic to reduce both the CTs and the maximum temperature of processors has been studied. It takes into account variations in the ambient temperature and is based on DVFS and DPM techniques. Simulation results with global scheduling algorithms RM, EDF and EDZL and different processor loads (for a MPC5517 type circuit and a T1 UltraSparc from Sun Microsystems) illustrate the effectiveness of the proposed technique.

Este estudo teve por finalidade estudar os efeitos da fototerapia com laser em baixa intensidade (Low Level Laser Therapy LLLT) sobre a inflamação e reparação após lesão criogênica realizada no sitema nervoso central (SNC) de ratos. Foram realizados 3 experimentos. Em todos os experimentos foi utilizado um modelo de deformação cortical direta induzida por lesão criogênica. A LLLT foi realizada com laser de diodo em baixa intensidade emitindo no vermelho visível (InGaAlP, 660 nm) ou no infravermelho (AlGaAr, 780 nm). Os parâmetros de irradiação foram: potência de 40 mW, área do feixe de 0,04 cm2, densidades de energia de 3 J/cm2 (3 s) ou 5 J/cm2 (5 s) determinando energias por ponto de 0,12 J e 0,20 J, respectivamente. Foram realizadas 2 irradiações com intervalo de 3 h, no modo contato e em 2 pontos por lesão. No experimento 1, 50 ratos da linhagem Wistar foram utilizados para determinar os parâmetros de LLLT capazes de influenciar na dinâmica da produção de citocinas proinflamatórias (TNF-a, IL-1b, IL-6) e antiinflamatória (IL-10). As citocinas foram mensuradas pelo teste ELISA no cérebro e no sangue dos animais, 6 e 24h após a lesão. Os grupos experimentais foram: controle (não irradiado) e 4 grupos irradiados com 3 J/cm2 ou 5 J/cm2 para cada comprimento de onda (n=10 por grupo). Para os experimentos 2 e 3 foram utilizados 40 ratos (20 não irradiados controles e 20 irradiados). A LLLT foi realizada somente com o parâmetro de irradiação do laser no infravermelho e a densidade de energia de 3 J/cm2. Nestes experimentos o processo de reparação das lesões criogênicas no SNC foi acompanhado em 6 h, 1, 7 e 14 dias após a última irradiação (n=5 por grupo por tempo experimental). No experimento 2 foi realizada a análise morfométrica da região lesionada do SNC. No experimento 3 foi analisada a distribuição das células inflamatórias (linfócitos T, leucócitos e macrófagos). Os dados de cada experimento foram comparados estatísticamente por análise de variância (ANOVA) ou Kruskal-Wallis seguido dos testes de Tukey ou de Dunn, respectivamente (F=5%). O trauma criogênico foi capaz de criar lesões focais no córtex representadas por necrose, edema, hemorragia e infiltrado inflamatório. Os achados mais marcantes foram: no experimento 1 com a irradiação do laser no infravermelho e 3 J/ cm2, o TNF- a e a IL-6 se mantiveram nos mesmos níveis em 6 e 24 h, enquanto no controle houve aumento significativo. Experimento 2: as lesões não tratadas apresentaram maior perda tecidual em 6 h que as irradiadas. Experimento 3: as lesões irradiadas apresentaram menor quantidade de leucócitos e linfócitos T nas primeiras 24 h do que nas lesões controle. A quantidade de macrófagos foi similar nos dois grupos. Conclusões: Levando em consideração as condições experimentais deste estudo concluiu-se que LLLT exerce efeitos nos processos de inflamação e reparação diminuindo a concentração de citocinas próinflamatórias (TNF-F e IL-6) no sangue e mantendo a de IL-1I no cérebro. Adicionalmente, diminui a perda tecidual inicial pós- lesão criogênica e a infiltração inicial de leucócitos e linfócitos T. / This study aimed to study the effects of phototherapy with low-intensity laser (Low Level Laser Therapy - LLLT) on inflammation and repair after cryogenic injury held in central nervous system (CNS) of rats. There were 3 experiments. In all experiments a model of deformation induced by direct cortical cryogenic injury was used. The LLLT was carried out with a low intensity diode laser emitting in the visible red (InGaAlP, 660 nm) or infrared (AlGaAs, 780 nm). The irradiation parameters were: power of 40 mW, beam area of 0.04 cm2, energy densities of 3 J/cm2 (3 s) or 5 J/cm2 (5 s) providing energy per point of 0.12 J and 0.20 J, respectively. Two irradiations were performed at 3 h-intervals, in contact mode and in 2 points for lesion. In experiment 1, 50 Wistar rats were used to determine the parameters of LLLT able to influence the dynamics of production proinflammatory cytokines (TNF-, IL-1 and IL-6) and antiinflammatory cytokine (IL- 10). Cytokines were measured by ELISA in the brain and blood of animals, 6 and 24 hours after injury. The experimental groups were: control (non-irradiated) and 4 irradiated groups [3 J/cm2 and 5 J/cm2 for each wavelength (n = 10 per group)]. For experiments 2 and 3 40 rats (20 non-irradiated - controls and 20 irradiated).were used. The LLLT was performed only with the parameter of laser irradiation on the infrared and the energy density of 3 J/cm2. In these experiments, the process of repair of cryogenic injury in the CNS was followed in 6 h, 1, 7 and 14 days after the last irradiation (n = 5 per group and time trial). In experiment 2 a morphometric analysis of the injured area of the CNS was done. In experiment 3 the distribution of inflammatory cells (lymphocytes, leukocytes and macrophages) was analyzed. Data from each experiment were compared statistically by analysis of variance (ANOVA) or Kruskal-Wallis followed by tests of Tukey or Dunn, respectively ( = 5%). Cryogenic trauma was able to create focal lesions in the cortex represented by necrosis, edema, hemorrhage and inflammatory infiltrate. The most striking findings were: in experiment 1 with the laser irradiation in the infrared and 3 J/cm 2, TNF- and IL-6 remained at the same levels at 6 and 24 h, while in the control there was a significant increase. Experiment 2: untreated lesions showed greater tissue loss than irradiated lesions in 6 h. Experiment 3: lesions irradiated had fewer leukocytes and lymphocytes in the first 24 h than control lesions. The amount of macrophages was similar in both groups. Conclusions: Considering the experimental conditions of this study it was concluded that LLLT has effects in the processes of inflammation and repair by decreasing the concentration of proinflammatory cytokines (TNF- and IL-6) in blood and holding the IL-1 in the brain. Additionally, decreases the initial tissue loss after cryogenic injury and the initial infiltration of leukocytes and lymphocytes T.

Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS). / This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).

Cette thèse aborde la performance du protocole KNX-RF utilisé dans les applications domotiques en termes de robustesse Radio Fréquences dans un environnement multi-protocoles potentiellement sujet aux interférences. Dans ces travaux, le but est d’évaluer les problématiques d’interférences rencontrées par KNX-RF en utilisant des modèles de simulation qui permettraient d’augmenter à sa fiabilité radio. Ainsi, un premier modèle a été développé sur MATLAB/Simulink et a permis de connaître les performances et les limitations de ce protocole au niveau de la couche physique dans un scénario d’interférence se produisant à l’intérieur d’une box/gateway domotique multi-protocoles. Ces simulations ont été complétées par des essais expérimentaux sur le terrain qui ont permis de vérifier les résultats obtenus. Un deuxième modèle a été développé pour évaluer les mécanismes de la couche MAC, cette fois-ci, grâce au simulateur OMNet++/MiXiM. Ce modèle reprend tous les mécanismes d’accès au canal et d’agilité en fréquence spécifiés par la norme KNX. Un scénario de collisions de trames a été simulé et plusieurs propositions d’améliorations sont discutées dans ce manuscrit. Les modèles développés permettent d’analyser et de prédire en avance de phase le comportement de KNX-RF dans un environnement radio contraignant. / This thesis addresses the performance of the KNX-RF protocol used for home automation applications in terms of radiofrequency robustness in a multi-protocol environment that is potentially subject to interferences. In this work, the aim is to assess the interference problems encountered by KNX-RF using simulation models that would increase its RF reliability. Thus, a first model was developed on MATLAB / Simulink and allowed to investigate the performance and limitations of this protocol at its physical layer in an interference scenario occurring inside a multiprotocol home and building automation box/gateway. These simulations were followed by field experimental tests in an indoor environment (house) to verify the results. A second model was developed to evaluate the MAC layer mechanisms of KNX-RF through the discrete event simulator OMNeT ++/Mixim. This model includes all the mechanisms of channel access and frequency agility specified by KNX-RF standard. A frame collision scenario was simulated and several improvement proposals are discussed in this manuscript. The developed models can be used to analyze and predict in advance phase the behavior of KNX-RF in a radio-constrained environment.

Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS). / This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).

Dans les dernières années, beaucoup de travail a été consacré par l’industrie électronique pour réduire la consommation d’énergie des composants micro-électroniques qui représente un fardeau important dans la spécification des nouveaux systèmes.Afin de réduire la consommation d’énergie, nombreuses stratégies peuvent être adoptées au niveau des systèmes micro-électroniques et des simples dispositifs nano-électroniques. Récemmentle Transistor Tunnel `a effet de champ (Tunnel-FET) s’est imposé comme un candidat possible pour remplacer les dispositifs MOSFET conventionnels pour applications de tr`es basse puissance à des tensions d’alimentation VDD < 0.5V. Nous présentons un modèle Multi-Subband Monte Carlo modifié (MSMC) qui a été adapté pour la simulation de TFET Ultra Thin Body Fully Depleted Seminconductor on Insulator (FDSOIUTB) avec homo- et hétéro-jonctions et des matériaux semi-conducteurs arbitraires. Nous prenons en considération la quantification de la charge avec une correction quantique heuristique mais précise, validée via des modèles quantiques complets et des résultats expérimentaux.Le modèle MSMC a été utilisé pour simuler et évaluer la performance de FD-SOI TFET sidéealisées avec homo- et hétéro-jonction en Si, alliages SiGe ou composés InGaAs. Dans la deuxième partie de l’activité de doctorat un travail de caractérisation à basse températurea été réalisé sur les TFETs en Si et SiGe homo- et hétéro-jonction fabriqués par le centre de recherche français du CEA -LETI. L’objectif est d’estimer la présence de l’effet Tunnel comme principal mécanisme d’injection et la contribution d’autres mécanismes d’injection comme le Trap Assisted Tunneling. / In the last years a significant effort has been spent by the microelectronic industry to reducethe chip power consumption of the electronic systems since the latter is becoming a majorlimitation to CMOS technology scaling.Many strategies can be adopted to reduce the power consumption. They range from thesystem to the electron device level. In the last years Tunnel Field Effect Transistors (TFET)have imposed as possible candidate devices for replacing the convential MOSFET in ultra lowpower application at supply voltages VDD < 0.5V. TFET operation is based on a Band-to-BandTunneling (BtBT) mechanism of carrier injection in the channel and they represent a disruptiverevolutionary device concept.This thesis investigates TFET modeling and simulation, a very challenging topic becauseof the difficulties in modeling BtBT accurately. We present a modified Multi Subband MonteCarlo (MSMC) that has been adapted for the simulation of Planar Ultra Thin Body (UTB)Fully Depleted Semiconductor on Insulator (FD-ScOI) homo- and hetero-junction TFET implementedwith arbitrary semiconductor materials. The model accounts for carrier quantizationwith a heuristic but accurate quantum correction validated by means of comparison with fullquantum model and experimental results.The MSMC model has been used to simulate and assess the performance of idealized homoandhetero-junction TFETs implemented in Si, SiGe alloys or InGaAs compounds.In the second part of the thesis we discuss the characterization of TFETs at low temperature.Si and SiGe homo- and hetero-junction TFETs fabricated by CEA-LETI (Grenoble,France) are considered with the objective to identify the possible presence of alternative injectionmechanisms such as Trap Assisted Tunneling. / Negli ultimi anni uno sforzo significativo `e stato speso dall’industria microelettronica per ridurreil consumo di potenza da parte dei sistemi microelettronici. Esso infatti sta diventando unadelle limitazioni pi`u significative per lo scaling geometrico della tecnologia CMOS.Diverse strategie possono essere adottate per ridurre il consumo di potenza considerando ilsistema microelettronico nella sua totalit`a e scendendo fino a giungere all’ottimizzazione delsingolo dispositivo nano-elettronico. Negli ultimi anni il transistore Tunnel FET (TFET) si`e imposto come un possibile candidato per rimpiazzare, in applicazioni a consumo di potenzaestremamente basso con tensioni di alimentazione inferiori a 0.5V, i transistori convenzionaliMOSFET. Il funzionamento del TFET si basa sul meccanismo di iniezione purament quantisticodel Tunneling da banda a banda (BtBT) e che dovrebbe permettere una significativa riduzionedella potenza dissipata. Il BtBT nei dispositivi convenzionali `e un effetto parassita, nel TFETinvece esso `e utilizzato per poter ottenere significativi miglioramenti delle performance sottosogliae pertanto esso rappresenta una nuova concezione di dispositivo molto innovativa erivoluzionaria.Questa tesi analizza la modellizazione e la simulazione del TFET. Questi sono argomenti moltocomplessi vista la difficolt`a che si hanno nel modellare accuratamente il BtBT. In questo lavoroviene presentata una versione modificata del modello di trasporto Multi Subband Monte Carlo(MSMC) adattato per la simulazione di dispositivi TFET planari Ultra Thin Body Fully DepletedSilicon on Insulator (UTB FD-SOI), implementati con un canale composto da un unicosemiconduttore (omogiunzione) o con differenti materiali semiconduttori (eterogiunzione). Ilmodello proposto tiene il conto l’effetto di quantizzazione dovuto al confinamento dei portatoridi carica, con un’euristico ma accurato sistema di correzione. Tale modello `e stato poivalidato tramite una comparazione con altri modelli completamente quantistici e con risultatisperimentali.Superata la fase di validazione il modello MSMC `e utilizzato per simulare e verificare le performancedi dispositivi TFET implementati come omo o eterogiunzione in Silicio, leghe SiGe,o composti semiconduttori InGaAs.Nella seconda parte della tesi viene illustrato un lavoro di caratterizazione di TFET planari abassa temperatura (fino a 77K). Sono stati misurati dispositivi in Si e SiGe a omo o eterogiuzioneprodotti nella camera bianca del centro di ricerca francese CEA-LETI di Grenoble. Tramite talimisure `e stato possibile identificare la probabile presenza di meccanismi di iniezione alternativial BtBT come il Tunneling assistito da trappole (TAT) dimostrando come questo effetto `e,con ogni probabilit`a, la causa delle scarse performance in sottosoglia dei dispositivi TFETsperimentali a temperatura ambiente.

Over the past decades, the shrinking transistor size enabled more transistors to be integrated into an IC chip, to achieve higher and higher computing performances. However, the semiconductor industry is now reaching a saturation point of Moore’s Law largely due to soaring power consumption and heat dissipation, among other factors. High chip temperature not only significantly increases packing/cooling cost, degrades system performance and reliability, but also increases the energy consumption and even damages the chip permanently. Although designing 2D and even 3D multi-core processors helps to lower the power/thermal barrier for single-core architectures by exploring the thread/process level parallelism, the higher power density and longer heat removal path has made the thermal problem substantially more challenging, surpassing the heat dissipation capability of traditional cooling mechanisms such as cooling fan, heat sink, heat spread, etc., in the design of new generations of computing systems. As a result, dynamic thermal management (DTM), i.e. to control the thermal behavior by dynamically varying computing performance and workload allocation on an IC chip, has been well-recognized as an effective strategy to deal with the thermal challenges. Over the past decades, the shrinking transistor size, benefited from the advancement of IC technology, enabled more transistors to be integrated into an IC chip, to achieve higher and higher computing performances. However, the semiconductor industry is now reaching a saturation point of Moore’s Law largely due to soaring power consumption and heat dissipation, among other factors. High chip temperature not only significantly increases packing/cooling cost, degrades system performance and reliability, but also increases the energy consumption and even damages the chip permanently. Although designing 2D and even 3D multi-core processors helps to lower the power/thermal barrier for single-core architectures by exploring the thread/process level parallelism, the higher power density and longer heat removal path has made the thermal problem substantially more challenging, surpassing the heat dissipation capability of traditional cooling mechanisms such as cooling fan, heat sink, heat spread, etc., in the design of new generations of computing systems. As a result, dynamic thermal management (DTM), i.e. to control the thermal behavior by dynamically varying computing performance and workload allocation on an IC chip, has been well-recognized as an effective strategy to deal with the thermal challenges. Different from many existing DTM heuristics that are based on simple intuitions, we seek to address the thermal problems through a rigorous analytical approach, to achieve the high predictability requirement in real-time system design. In this regard, we have made a number of important contributions. First, we develop a series of lemmas and theorems that are general enough to uncover the fundamental principles and characteristics with regard to the thermal model, peak temperature identification and peak temperature reduction, which are key to thermal-constrained real-time computer system design. Second, we develop a design-time frequency and voltage oscillating approach on multi-core platforms, which can greatly enhance the system throughput and its service capacity. Third, different from the traditional workload balancing approach, we develop a thermal-balancing approach that can substantially improve the energy efficiency and task partitioning feasibility, especially when the system utilization is high or with a tight temperature constraint. The significance of our research is that, not only can our proposed algorithms on throughput maximization and energy conservation outperform existing work significantly as demonstrated in our extensive experimental results, the theoretical results in our research are very general and can greatly benefit other thermal-related research.

Afin de réaliser un appareil innovant pour la mesure de gaz polluants, la société SVS@CAP s’est associée avec le laboratoire de physique corpusculaire en 2009 pour la création du projet EREBUS. Ce projet a pour but la réalisation d’un ensemble de dispositifs sans fil permettant d’effectuer une surveillance de la concentration de gaz polluants. L’autonomie et la compacité d’un tel dispositif étant essentielles, la problématique principale porte sur la réduction de la consommation. A partir d’une première étude menée sur les différentes technologies existantes, les capteurs électrochimiques ont été identifiés comme les moins consommateurs d’énergie. Pour chacun des gaz cibles, un modèle électrique du capteur associé a été déterminé. A partir de ces modèles, une architecture dédiée et épurée a pu être déduite. Pour atteindre et même dépasser les objectifs de consommation, les efforts ont aussi été portés sur un dimensionnement avec la méthode gm/id. La réalisation de cette électronique intégrée a permis d’atteindre une consommation de l’ordre du μW pour chaque voie de mesure. Enfin, pour compléter la chaîne de lecture, plusieurs architectures de convertisseurs ont été étudiées et réalisées pour fonctionner à des fréquences déchantillonnage proches du Hz. Les consommations obtenues pour les convertisseurs sont limitées avec comme ordre de grandeur la centaine de nW. / In order to realize an innovative product for pollutants in the atmosphere, SVS@CAP company started in 2009 the EUREBUS project in collaboration with the "Laboratoire de Physique Corpusculaire". The aim of this project is to design a wireless equipement to measure gas concentrations. The key issues of this project are concerning the autonomy as well as the small size of the product. In consequence an integrated and low power electronics remains essential. From a first study of the existing technologies to detect gaz concentrations, electrochemical sensors were selected because of their low power consumption. For each of the target gas, an electrical model was determined. From those models, a specific architecture was designed. A special effort was made on the energy consumption thanks to the use of the gm/id methodology which was necessary to achieve and exceed the specifications. The final order of the power consumption of the front-end developped and realized is around the μW. Finally, in order to complete the chain of acquisition, some architectures of analog to digital converter were studied, developped and realized with sample frequencies close to the Hz. The power consumptions of the converters developped are limited to the order of the hundreds of nW.