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With the upcoming 5G networks and expected growth of the Internet of Things (IoT), the demand for fast and reliable encryption algorithms will increase. As many systems might be time critical and run on internal power sources, the algorithms must be small, fast, energy efficient and have low latency. A new stream cipher called Espresso has been proposed to answer these demands, optimizing for several parameters unlike other stream ciphers such as Trivium and Grain. Espresso has previously been compared to the industry standard, Advanced Encryption Standard (AES), in a FPGA implementation and has shown promising results in terms of power usage but further testing needs to be done to gain knowledge about the ciphers characteristics. The purpose of this thesis is to implement and evaluate Espresso in 65nm CMOS technology and compare it to AES. Espresso is implemented in VHDL in several configurations, optimizing for size and latency. The implementations are then compared to AES is in terms of area, throughput, energy efficiency and latency through simulation. This is done using the UMC 65nm CMOS library and Synopsys Design Vision. It is found that Espresso, implemented with 1 bit sequential loading of the key and IV, is 18.2x smaller, 3.2x faster, uses 9.4x less power and has 1.5x less latency than AES. When implemented with full parallel loading, Espresso still is 13.6x smaller, 3.2x faster, draws 7.1x less power while also having 3.2x lower latency than AES. Espressos energy efficiency can further be improved by applying low- power techniques although some techniques, like clock gating and power gating, have limited applicability due to of the nature of stream ciphers. / Med de kommande 5G nätverken och den förväntade tillväxten av Internet of Things (IoT) kommer efterfrågan på snabba och pålitliga krypteringsalgoritmer att öka. Eftersom många system kan vara tidskritiska och drivas av interna kraftkällor måste algoritmerna vara små, snabba, energieffektiva och ha låg latens. Ett nytt strömchiffer vid namn Espresso har föreslagits som ett svar på dessa krav och har optimiserats för flera parametrar till skillnad från andra strömchiffer såsom Trivium och Grain. Espresso har tidigare jämförts med branschstandarden, Advanced Encryption Standard (AES), i en FPGA implementation och visat lovande resultat för strömförbrukning men ytterligare tester måste utföras för att få kunskap om algoritmens egenskaper. Syftet med detta examensarbete är att implementera och utvärdera Espresso i 65nm CMOS teknologi och jämföra den med AES. Espresso implementeras i flera konfigurationer i VHDL som optimiserar för storlek och latens. Implementationerna jämförs sedan med AES i area, genomströmning, energieffektivitet och latens genom simulering. Detta görs med hjälp av UMC 65nm CMOS biblioteket och Synopsys Design Vision. Resultaten visar att Espresso implementerad med sekventiell laddning av nyckel och IV är 18.2x mindre, 3.2x snabbare, använder 9.4x mindre ström och har 1.5x mindre latens än AES. När Espresso implementeras med full parallel laddning är den fortfarande 13.6x mindre, 3.2x snabbare, drar 7.1x mindre ström men har samtidigt 3.2x lägre latens än AES. Espresso’s energieffektivitet kan förbättras ytterligare genom att applicera strömsparande tekniker, även om vissa tekniker såsom clock gating och power gating har begränsad användbarhet på grund av strömchiffers natur.

Detta examensarbete fokuserar på utveckling och utvärdering av en ny metod för att räkna dubbelriktade personflöden inomhus med hjälp av Ultrasonic Time-of-Flight teknik. Projektets huvudsyfte är att skapa en kostnadseffektiv, strömsnål och integritetsvänlig lösning som är i linje med lagar som GDPR. Studien börjar med en kort genomgång av tillgängliga tekniker för personflödesmätning, men det blir tydligt att dessa tekniker brister i kraven för den önskade tekniken. Mot denna bakgrund framstår Ultrasonic Time-of-Flight som en lovande kandidat på grund av sin förmåga att detektera objekt och rörelseriktningar utan att samla in personligt identifierbar information. För att realisera detta projekt har ett utvecklingskit baserat på sensorn CH201 från Chirp Microsystems använts. Sensorns låga strömförbrukning och förmåga att mäta avstånd i ett brett synfält är det som är lovande i tekniken. Ett akustiskt hölje optimerar sensorernas synfält och minimerar störningar. Experimentdelen av arbetet inkluderar uppbyggnaden av en testmiljö där sensorernas förmåga att korrekt räkna individer och bestämma deras rörelseriktning testas. Resultaten från dessa tester visar på hög noggrannhet i detektering av enskilda individer som passerar, men har lägre noggrannhet då flera personer passerar samtidigt. Vidare diskuteras potentialen för att vidareutveckla systemet för att även kunna hantera större personflöden och mer komplexa scenarion, som flera personer som rör sig bredvid varandra i olika riktningar. En kritisk granskning av systemets prestanda under längre tidsperioder och i olika miljöer föreslås som framtida forskningsarbete för att ytterligare validera och förbättra tekniken. Sammanfattningsvis demonstrerar detta arbete potentialen hos tekniken som en säker och integritetsvänlig lösning för effektiv övervakning av personflöden. Med ytterligare utveckling och anpassning förväntas tekniken kunna uppfylla en ännu högre noggrannhet. / This thesis focuses on the development and evaluation of a new method for measuring bidirectional indoor people flows using Ultrasonic Time-of-Flight technology. The main purpose of the project is to create a cost-effective, low-power, and privacy-friendly solution that complies with laws like the GDPR. It begins with a short review of existing techniques for measuring people flow, concluding that these technologies do not support the goal of the new technology. Ultrasonic Time-of-Flight emerges as a promising candidate due to its ability to detect objects and directions of movement without collecting personally identifiable information. To realize this project, a development kit based on the CH201 sensor from ChirpMicrosystems has been used. The sensor’s low power consumption and ability to measure distances in a wide field of view are what made the technology promising. An acoustic enclosure optimizes the sensors’ field of view and minimizes interference. The experimental part of the work includes the construction of a test environment where the sensors’ ability to accurately count individuals and determine their direction of movement is tested. The results from these tests show high accuracy in detecting individual passersby but encounter more problems with multiple individuals simultaneously. Further discussions will explore the potential for developing the system to manage larger crowds and more complex scenarios, such as multiple people moving side by side in different directions. A critical review of the system’s performance over longer periods and in different environments is proposed as future research work to further validate and improve the technology. In conclusion, this work demonstrates the potential of the technology as a secure and privacy-friendly solution for effective monitoring of people flows. With further development and adaptation, the technology is expected to offer significantly better accuracy.

[EN] SRAM technology has traditionally been used to implement processor caches since it is the fastest existing RAM technology.However,one of the major drawbacks of this technology is its high energy consumption.To reduce this energy consumption modern processors mainly use two complementary techniques: i)low-power operating modes and ii)low-power memory technologies.The first technique allows the processor working at low clock frequencies and supply voltages.The main limitation of this technique is that manufacturing defects can significantly affect the reliability of SRAM cells when working these modes.The second technique brings alternative technologies such as eDRAM, which provides minimum area and power consumption.The main drawback of this memory technology is that reads are destructive and eDRAM cells work slower than SRAM ones. This thesis presents three main contributions regarding low-power caches and heterogeneous technologies: i)an study that identifies the optimal capacitance of eDRAM cells, ii)a novel cache design that tolerates the faults produced by SRAM cells in low-power modes, iii)a methodology that allows obtain the optimal operating frequency/voltage level when working with low-power modes. Regarding the first contribution,in this work SRAM and eDRAM technologies are combined to achieve a low-power fast cache that requires smaller area than conventional designs and that tolerates SRAM failures.First,this dissertation focuses on one of the main critical aspects of the design of heterogeneous caches:eDRAM cell capacitance.In this dissertation the optimal capacitance for an heterogeneous L1 data cache is identified by analyzing the compromise between performance and energy consumption.Experimental results show that an heterogeneous cache implemented with 10fF capacitors offers similar performance as a conventional SRAM cache while providing 55% energy savings and reducing by 29% the cache area. Regarding the second contribution,this thesis proposes a novel organization for a fault-tolerant heterogeneous cache.Currently,reducing the supply voltage is a mechanism widely used to reduce consumption and applies when the system workload activity decreases.However,SRAM cells cause different types of failures when the supply voltage is reduced and thus they limit the minimum operating voltage of the microprocessor. In the proposal,memory cells implemented with eDRAM technology serve as backup in case of failure of SRAM cells, because the correct operation of eDRAM cells is not affected by reduced voltages. The proposed architecture has two working modes: high-performance mode for supply voltages that do not induce SRAM cell failures, and low-power mode for those voltages that cause SRAM cell failures. In high-performance mode, the cache provides full capacity, which enables the processor to achieve its maximum performance. In low-power mode, the effective capacity of the cache is reduced because some of the eDRAM cells are dedicated to recover from SRAM failures. Experimental results show that the performance is scarcely reduced (e.g. less than 2.7% across all the studied benchmarks) with respect to an ideal SRAM cache without failures. Finally,this thesis proposes a methodology to find the optimal frequency/voltage level regarding energy consumption for the designed heterogeneous cache. For this purpose, first SRAM failure types and their probabilities are characterized.Then,the energy consumption of different frequency/voltage levels is evaluated when the system works in low-power mode.The study shows that, mainly due to the impact of SRAM failures on performance,the optimal combination of voltage and frequency from the energy point of view does not always correspond to the minimum voltage. / [ES] La tecnología SRAM se ha utilizado tradicionalmente para implementar las memorias cache debido a que es la tecnología de memoria RAM más rápida existente.Por contra,uno de los principales inconvenientes de esta tecnología es su elevado consumo energético.Para reducirlo los procesadores modernos suelen emplear dos técnicas complementarias:i) modos de funcionamiento de bajo consumo y ii)tecnologías de bajo consumo.La primeras técnica consiste en utilizar bajas frecuencias y voltajes de funcionamiento.La principal limitación de esta técnica es que los defectos de fabricación pueden afectar notablemente a la fiabilidad de las celdas SRAM en estos modos.La segunda técnica agrupa tecnologías alternativas como la eDRAM,que ofrece área y consumo mínimos.El inconveniente de esta tecnología es que las lecturas son destructivas y es más lenta que la SRAM. Esta tesis presenta tres contribuciones principales centradas en caches de bajo consumo y tecnologías heterogéneas: i)estudio de la capacitancia óptima de las celdas eDRAM, ii)diseño de una cache tolerante a fallos producidos en las celdas SRAM en modos de bajo consumo, iii)metodología para obtener la relación óptima entre voltaje y frecuencia en procesadores con modos de bajo consumo. Respecto a la primera contribución,en este trabajo se combinan las tecnologías SRAM y eDRAM para conseguir una memoria cache rápida, de bajo consumo, área reducida, y tolerante a los fallos inherentes a la tecnología SRAM.En primer lugar,esta disertación se centra en uno de los aspectos críticos de diseño de caches heterogéneas SRAM/eDRAM: la capacitancia de los condensadores implementados con tecnología eDRAM.En esta tesis se identifica la capacitancia óptima de una cache de datos L1 heterogénea mediante el estudio del compromiso entre prestaciones y consumo energético.Los resultados experimentales muestran que condensadores de 10fF ofrecen prestaciones similares a las de una cache SRAM convencional ahorrando un 55% de consumo y reduciendo un 29% el área ocupada por la cache. Respecto a la segunda contribución,esta tesis propone una organización de cache heterogénea tolerante a fallos.Actualmente,reducir el voltaje de alimentación es un mecanismo muy utilizado para reducir el consumo en condiciones de baja carga.Sin embargo,las celdas SRAM producen distintos tipos de fallos cuando se reduce el voltaje de alimentación y por tanto limitan el voltaje mínimo de funcionamiento del microprocesador. En la cache heterogénea propuesta,las celdas de memoria implementadas con tecnología eDRAM sirven de copia de seguridad en caso de fallo de las celdas SRAM, ya que el correcto funcionamiento de las celdas eDRAM no se ve afectado por tensiones reducidas.La arquitectura propuesta consta de dos modos de funcionamiento: high-performance mode para voltajes de alimentación que no inducen fallos en celdas implementadas en tecnología SRAM, y low-power mode para aquellos que sí lo hacen. En el modo high-performance mode,el procesador dispone de toda la capacidad de la cache.En el modo low-power mode se reduce la capacidad efectiva de la cache puesto que algunas de las celdas eDRAM se dedican a la recuperación de fallos de celdas SRAM.El estudio de prestaciones realizado muestra que éstas bajan hasta un máximo de 2.7% con respecto a una cache perfecta sin fallos. Finalmente, en esta tesis se propone una metodología para encontrar la relación óptima de voltaje/frecuencia con respecto al consumo energético sobre la cache heterogénea previamente diseñada. Para ello,primero se caracterizan los tipos de fallos SRAM y las probabilidades de fallo de los mismos.Después,se evalúa el consumo energético de diferentes combinaciones de voltaje/frecuencia cuando el sistema se encuentra en un modo de bajo consumo.El estudio muestra que la combinación óptima de voltaje y frecuencia desde el punto de vista energético no siempre corresponde al mínimo voltaje debido al imp / [CA] La tecnologia SRAM s'ha utilitzat tradicionalment per a implementar les memòries cau degut a que és la tecnologia de memòria RAM més ràpida existent.Per contra, un dels principals inconvenients d'aquesta tecnologia és el seu elevat consum energètic.Per a reduir el consum els processadors moderns solen emprar dues tècniques complementàries: i)modes de funcionament de baix consum i ii)tecnologies de baix consum.La primera tècnica consisteix en utilitzar baixes freqüències i voltatges de funcionament.La principal limitació d'aquesta tècnica és que els defectes de fabricació poden afectar notablement a la fiabilitat de les cel·les SRAM en aquests modes.La segona tècnica agrupa tecnologies alternatives com la eDRAM, que ofereix àrea i consum mínims.L'inconvenient d'aquesta tecnologia és que les lectures són destructives i és més lenta que la SRAM. Aquesta tesi presenta tres contribucions principals centrades en caus de baix consum i tecnologies heterogènies: i)estudi de la capacitancia òptima de les cel·les eDRAM, ii)disseny d'una cau tolerant a fallades produïdes en les cel·les SRAM en modes de baix consum, iii)metodologia per a obtenir la relació òptima entre voltatge i freqüència en processadors amb modes de baix consum. Respecte a la primera contribució, en aquest treball es combinen les tecnologies SRAM i eDRAM per a aconseguir una memòria cau ràpida, de baix consum, àrea reduïda, i tolerant a les fallades inherents a la tecnologia SRAM.En primer lloc, aquesta dissertació se centra en un dels aspectes crítics de disseny de caus heterogènies: la capacitancia dels condensadors implementats amb tecnologia eDRAM.En aquesta dissertació s'identifica la capacitancia òptima d'una cache de dades L1 heterogènia mitjançant l'estudi del compromís entre prestacions i consum energètic.Els resultats experimentals mostren que condensadors de 10fF ofereixen prestacions similars a les d'una cau SRAM convencional estalviant un 55% de consum i reduint un 29% l'àrea ocupada per la cau. Respecte a la segona contribució, aquesta tesi proposa una organització de cau heterogènia tolerant a fallades.Actualment,reduir el voltatge d'alimentació és un mecanisme molt utilitzat per a reduir el consum en condicions de baixa càrrega.Per contra, les cel·les SRAM produeixen diferents tipus de fallades quan es redueix el voltatge d'alimentació i per tant limiten el voltatge mínim de funcionament del microprocessador. En la cau heterogènia proposta, les cel·les de memòria implementades amb tecnologia eDRAM serveixen de còpia de seguretat en cas de fallada de les cel·les SRAM, ja que el correcte funcionament de les cel·les eDRAM no es veu afectat per tensions reduïdes.L'arquitectura proposada consta de dues maneres de funcionament: high-performance mode per a voltatges d'alimentació que no indueixen fallades en cel·les implementades en tecnologia SRAM,i low-power mode per a aquells que sí ho fan.En el mode high-performance,el processador disposa de tota la capacitat de la cau.En el mode low-power es redueix la capacitat efectiva de la cau posat que algunes de les cel·les eDRAM es dediquen a la recuperació de fallades de cel·les SRAM.L'estudi de prestacions realitzat mostra que aquestes baixen fins a un màxim de 2.7% pel que fa a una cache perfecta sense fallades. Finalment,en aquesta tesi es proposa una metodologia per a trobar la relació òptima de voltatge/freqüència pel que fa al consum energètic sobre la cau heterogènia prèviament dissenyada.Per a açò,primer es caracteritzen els tipus de fallades SRAM i les probabilitats de fallada de les mateixes.Després,s'avalua el consum energètic de diferents combinacions de voltatge/freqüència quan el sistema es troba en un mode de baix consum.L'estudi mostra que la combinació òptima de voltatge i freqüència des del punt de vista energètic no sempre correspon al mínim voltatge degut a l'impacte de les fallades de SRAM en les pres / Lorente Garcés, VJ. (2015). Cache architectures based on heterogeneous technologies to deal with manufacturing errors [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/58428

Among the low-power wireless technologies that have emerged in recent years, ultra-wideband (UWB) has successfully established itself as the reference for accurate ranging and localization, both outdoors and indoors. Due to its unprecedented performance, paired with relatively low energy consumption, UWB is going to play a central role in the next wave of location-based applications. As the trend of integration in smartphones continues, UWB is also expected to reach ordinary users, revolutionizing our lives the same way GPS and similar technologies have done. But the impact of UWB may not be limited to ranging and localization. Because of its considerable data rate, and its robustness to obstacles and interference, UWB communication may hold untapped potential for sensing and control applications. Nevertheless, several research questions still need to be answered to assess whether UWB can be adopted widely in the communication and localization landscapes. On one hand, the rapid evolution of UWB radios and the release of ever more efficient chips is a clear indication of the growing market for this technology. However, for it to become pervasive, full-fledged communication and localization systems must be developed and evaluated, tackling the shortcomings affecting current prototypes. UWB systems are typically single-hop networks designed for small areas, making them impractical for large-scale coverage. This limitation is found in communication and localization systems alike. Specifically for communication systems, energy-efficient multi-hop protocols are hitherto unexplored. As for localization systems, they rely on mains-powered anchors to circumvent the issue of energy consumption, in addition to only supporting small areas. Very few options are available for light, easy to deploy infrastructures using battery-powered anchors. Nonetheless, large-scale systems are required in common settings like industrial facilities and agricultural fields, but also office spaces and museums. The general goal of enabling UWB in spaces like these entails a number of issues. Large multi-hop infrastructures exacerbate the known limitations of small, single-hop, networks; notably, reliability and latency requirements clash with the need to reduce energy consumption. Finally, when device mobility is a factor, continuity of operations across the covered area is a challenge in itself. In this thesis, we design energy-efficient UWB systems for large-scale areas, supporting device mobility across multi-hop infrastructures. As our opening contribution, we study the unique interference rejection properties of the radio to inform our design. This analysis yields a number of findings on the impact of interference in communication and distance estimation, that are directly usable by developers to improve UWB solutions. These findings also suggest that concurrent transmissions in the same frequency channel are a practical option in UWB. While the overlapping of frames is typically avoided to prevent collisions, concurrent transmissions have counter-intuitively been used to provide highly reliable communication primitives for a variety of traffic patterns in narrowband radios. In our first effort to use concurrent transmissions in a full system, we introduce the UWB version of Glossy, a renowned protocol for efficient network-wide synchronization and data dissemination. Inspired by the success of concurrency-based protocols in narrowband, we then apply the same principles to define a novel data collection protocol, Weaver. Instead of relying on independent Glossy floods like state-of-the-art systems, we weave multiple data flows together to make our collection engine faster, more reliable and more energy-efficient. With Glossy and Weaver supporting the communication aspect in large-scale networks, we then propose techniques for large-scale localization systems. We introduce TALLA, a TDoA solution for continuous position estimation based on wireless synchronization. We evaluate TALLA in an UWB testbed and in simulations, for which we replicate accurately the behavior of the clocks in our real-world platforms. We then offer a glimpse of what TALLA can be employed for, deploying an infrastructure in a science museum to track visitors. The collected movement traces allow us to analyze fine-grained stop-move mobility patterns and infer the sequence of visited exhibits, which is only possible because of the high spatio-temporal granularity offered by TALLA. Finally, with SONAR, we tackle the issue of large-scale ranging and localization when the infrastructure cannot be mains-powered. By blending synchronization and scheduling operations into neighbor discovery and ranging, we drastically reduce energy consumption and ensure years-long system lifetime. Overall, this thesis enhances UWB applicability in scenarios that were previously precluded to the technology, by providing the missing communication and localization support for large areas and battery-powered devices. Throughout the thesis, we follow an experiment-driven approach to validate our protocol models and simulations. Based on the evidence collected during this research endeavor, we develop full systems that operate in a large testbed at our premises, showing that our solutions are immediately applicable in real settings.

The survival rate for a suddent cardiac arrest (SCA) is incredibly low, with less than one in ten surviving; most SCAs occur outside of a hospital setting. There is a need to develop an effective and efficient system that can sense, communicate and remediate potential SCA situations on a near real-time basis. This research presents a novel Zeolite-PDMS-based optically unobtrusive flexible dry electrodes for biosignal acquisition from various subjects while at rest and in motion. Two zeolite crystals (4A and 13X) are used to fabricate the electrodes. Three different sizes and two different filler concentrations are compared to identify the better performing electrode suited for electrocardiogram (ECG) data acquisition. A low-power, low-noise amplifier with chopper modulation is designed and implemented using the standard 180nm CMOS process. A commercial off-the-shelf (COTS) based wireless system is designed for transmitting ECG signals. Further, this dissertation provides a framework for Machine Learning Classification algorithms on large, open-source Arrhythmia and SCA datasets. Supervised models with features as the input data and deep learning models with raw ECG as input are compared using different methods. The machine learning tool classifies the datasets within a few minutes, saving time and effort for the physicians. The experimental results show promising progress towards advancing the development of a wireless ECG recording system combined with efficient machine learning models that can positively impact SCA outcomes.

Data acquisition through wireless sensor networks (WSNs) has enormous potential for scalable, distributed, real-time observations of monitored environmental parameters. Despite increasing versatility and functionalities, one critical factor that affects the operation of WSNs is limited power. WSN sensor nodes are usually battery powered, and therefore the long-term operation of the WSN greatly depends on battery capacity and the node's power consumption rate. This thesis focuses on WSN node design to reduce power consumption in order to achieve sustainable power supply. For this purpose, this thesis proposes a Moteino-based WSN node and an energy efficient duty cycle that reduces current consumption in standby mode using an enhanced watchdog timer. The nodes perform radio communication at 915 MHz, for short intervals (180ms) every 10 minutes, and consume 6.8 mA at -14dBm. For testing, the WSN node monitored a low-power combined air temperature, relative humidity, and barometric pressure sensor, together with a typical soil moisture sensor that consumes more power. Laboratory tests indicated average current consumption of ~30µA using these short radio transmission intervals. After transmission tests, field deployment of a star-configured network of nine of these nodes and one gateway node provides a long-term platform for testing under rigorous conditions. A webserver running on a Raspberry Pi connected serially to the gateway node provides real-time access to this WSN.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.